III-VVs:’s: From THz HEMT to CMOS 158 slides.pdf•t ch↓ Æperformance degradation Æincrease InAs composition in channel 100 d ec] t ins = 3-4 nm L side = 150 nm 105 InAs HEMTs

III-V’s:III V s: From THz HEMT to CMOS

J. A. del Alamo and D.-H. Kim1

Microsystems Technology Laboratories, MIT1presently with Teledyne Scientific

2009 Topical Workshop on Heterostructure Microelectronics

Sponsors: Intel, FCRP-MSD

Acknowledgements:

August 25-28, 2009

1

Acknowledgements:

Niamh Waldron, Tae-Woo Kim, Donghyun Jin, Ling Xia,

Dimitri Antoniadis, Robert Chau

MTL, NSL, SEBL

Outline

• Introduction

• Near-THz III-V HEMTs

• Logic characteristics of III-V HEMTs

• III-V CMOS

• Conclusions

2

The High Electron Mobility Transistor

3Mimura, JJAPL 1980

Modulation doping

• High electron mobility in modulation-doped AlGaAs/GaAs heterostructures

• 2 DEG at AlGaAs/GaAs interface

Dingle, APL 1978Stormer, Solid St

4

Comm 1979

HEMT circuits

27-stage ring oscillator

E/D logic

“The switching delay of 17 1 ps is the lowest of all17.1 ps is the lowest of all the semiconductor logic technologies reported thus f ”

5

Mimura, JJAPL 1981far.”

HEMTs in other material systems

InAlAs/InGaAs on InP AlGaAs/InGaAs PHEMT

K tt EDL 19851982 Ketterson, EDL 1985Kastalsky, APL 1982

Also in AlGaN/GaN, Si/SiGe, AlSb/InAs, etc

6

Also with holes in many heterojunction systems

HEMT Electronics: “You’ve come a long way baby!”ou e co e a o g ay baby

77

Near THz HEMTs

• fT vs time:800

800

800

800800

800

800

800 Kim EDL 2008

600

GH

z] 600

GH

z] 600

GH

z] 600

GH

z]III-V HBTs

III-V HEMTs600

GH

z] 600

GH

z] 600

GH

z] 600

GH

z]III-V HBTs

III-V HEMTs

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

400

eque

ncy

[G

200

Cut

off F

re

200

Cut

off F

re

200

Cut

off F

re

200

Cut

off F

re

SiGe HBTs

200

Cut

off F

re

200

Cut

off F

re

200

Cut

off F

re

200

Cut

off F

re

SiGe HBTs

1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year

Si CMOSSiGe HBTs

1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year1985 1990 1995 2000 2005 20100

Year

Si CMOSSiGe HBTs

8

YearYearYearYearYearYearYearYear

For over 20 years, fT (III-V’s) > fT (Si)

Near THz HEMTs

• fT vs fmax:1000

max ffτ

300 400 500 600 700 = favg =

800

1000 MIT HEMTs III-V HEMTs III-V HBTs

maxτavg

400

600

ax [

GH

z ] Kim IEDM 2008

200

400f m

0 200 400 600 800 10000

fT [ GHz ]

9III-V HEMT: only device with ft, fmax>600 GHz

III-Vs for CMOS?

• Si scaling running into increasing difficulties:

3

< Historical >< Extrapolated >

33


The scaled Si CMOS “performance gap”

3


33


33


33


The scaled Si CMOS “performance gap”Courtesy of Dimitri Antoniadis (MIT)x 10-15

n)

GS D

1 5

2

2.5

Del

ay (p

s)


1 5

2

2.5

Del

ay (p

s)

1 5

2

2.5

Del

ay (p

s)


1 5

2

2.5

Del

ay (p

s)


1 5

2

2.5

Del

ay (p

s)

1 5

2

2.5

Del

ay (p

s)


1 5

2

2.5

Del

ay (p

s)

1 5

2

2.5

Del

ay (p

s)


1 5

2

2.5

Del

ay (p

s)

1 5

2

2.5

Del

ay (p

s)


1

rge

(C/m

icro

“parasitic” charge

“15 nm” target0.5

1

1.5

Intr

insi

c


1

1.5

Intr

insi

c

0.5

1

1.5

Intr

insi

c


1

1.5

Intr

insi

c


1

1.5

Intr

insi

c

0.5

1

1.5

Intr

insi

c


1

1.5

Intr

insi

c

0.5

1

1.5

Intr

insi

c


1

1.5

Intr

insi

c

0.5

1

1.5

Intr

insi

c

0.5

Gat

e C

hachannel charge

15 nm target

0 20 40 60 80 100 1200

CMOS Generation (nm)

15 nm target

0 20 40 60 80 100 1200

CMOS Generation (nm)0 20 40 60 80 100 120

0


15 nm target

0 20 40 60 80 100 1200


15 nm target

0 20 40 60 80 100 1200


0


15 nm target

0 20 40 60 80 100 1200


0


15 nm target

0 20 40 60 80 100 1200


0



10

Parasitics becoming overwhelming need higher current

Transistor as switchIn logic applications transistor operates as switch

Interested in:

• ON current (ION)

• OFF current (IOFF)( OFF)

• VT

• VT dependence on Lgg

• VT dependence on VDS (DIBL)

• Subthreshold swing (S)

• Device footprint

• Gate capacitance

1111

• Operating voltage (VDD)

How Do III-V FETs Look for Logic?

Logic Characteristics of InGaAs High-Electron Mobility Transistor

Kim, IEDM 2006

Lg ~ 60 nm

Source Drainsource draingateSubstrate is InPSource

InP

InGaAs cap

InAlAs insulator

• Substrate is InP• Channel is In0.7Ga0.3As

μ > 10 000 cm2/V s at 300K

1212

InGaAs channel

InAlAs buffer

μ > 10,000 cm /V.s at 300K

• Barrier is In0.52Al0.48As

60 nm InGaAs HEMT

10-4

10-3

ID IG

VDS = 0.5 V0.5

VGS = 0.5 V

10-6

10-5

10

VDS

= 0.05 VID

A/μ

m]

G

Id0.3

0.4

VGS = 0.4 V

GS

mm

]

10-9

10-8

10-7

VDS = 0.5 V

I D &

I G [A

IGIg0.1

0.2

VGS = 0.2 V

VGS = 0.3 V

I D [A

/m

-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.5010-10

10 9

VGS [V]0.0 0.2 0.4 0.6 0.8

0.0VGS = 0.1 V

VDS [V]

At 0.5 V: Kim, IEDM 2006

1313

VT= -0.02 V, S= 88 mV/dec, DIBL= 93 mV/V, Ion/Ioff > 104

Benchmarking Against Si MOSFET: Gate Delay (CV/I) vs LGate Delay (CV/I) vs. Lg

10

For V at 1 μA/μm

psec

]

For VT at 1 μA/μm

Kim IEDM 2006

1In0.7Ga0.3As HEMTs (VDD = 0.5V)

E D

ELA

Y [p

Si data from Chau, T-Nano 2005

Kim, IEDM 2006

GA

TE

Si NMOSFETs(VDD = 1.1~1.3V)

100 101 102 1030.1

Gate Length, Lg [nm]

1414

Gate delay comparable to Si, in spite of lower voltage

Benchmarking Against Si MOSFET: S & DIBL vs LS & DIBL vs. Lg

Kim, IEDM 2006180

]

180Si FETs (IEDM) InGaAs HEMTs

]

400400Si FETs (IEDM) InGaAs HEMTs

120

140

160

ope

[mV/

dec]

120

140

160

ope

[mV/

dec]

200

300

mV/

V]

200

300

mV/

V]

80

100

120

thre

shol

d Sl

o

80

100

120

thre

shol

d Sl

o

100

200

DIB

L [m

100

200

DIB

L [m

10 10060

80

Gate Length [nm]

Sub

10 10060

80

Gate Length [nm]

Sub

10 1000

Gate Length [nm]10 100

0

Gate Length [nm]

At Lg=60 nm, InGaAs HEMT as good as Si MOSFET

C thi d i t l t th 15 d ?

1515

Can this device concept scale to the 15 nm node?

How will its performance compare with Si?

HEMT scaling

• Key dimensions: Lg, tins, tch, Lside

• Scaling trajectory:– Lg ↓Lg ↓

• tins ↓• tch ↓• Lside?

1616

Impact of gate length

VDS=0.5 V

6 x 104

VDS = 0.5 V

4

I OFF

2

I ON/

tch = 13 nmtins = 10 nmL id = 150 nm

0 100 200 300 400 5000

Lg [nm]

Lside 150 nm

• Lg↓– Ion/Ioff drops in the sub-200 nm regime

17

on off p g– SCE worsen

17Kim, IEDM 2006

Impact of barrier thickness

VDS=0.5 V

6 x 104

tch = 13 nmL 150

4

OFF

Lside = 150 nm

2

tins = 10 nm tins = 6.5 nm

I ON/I

0 100 200 300 400 5000

tins = 3 nm

Lg [nm]

• tins↓– Ion/Ioff worsens for long Lg due to IG↑ and Rs↑

18

on off g g G↑ s↑– SCE and scalability improve

18Kim, IEDM 2006

Impact of side recess length

200 Lside = 50 nm Lside = 150 nmL = 350 nm

VDS=0.5 V105

150

Lside = 350 nm

mV/

dec]

tch = 13 nm

104

ON/I O

FF

100S [m ch

tins = 10 nm103

Lside = 50 nm Lside = 150 nm Lside = 350 nm

I O

L

0 100 200 300 40050

Lg [nm]

0 100 200 300 400102

side

LG [nm]

• Lside↑– Ion/Ioff scalability improves

B tt SCE

Kim, ISDRS 2007

19

– Better SCE– But… minimum Lside shortens as tins↓ tch↓

19

Impact of channel thickness

• tch↓ performance degradationincrease InAs composition in channel

100

dec]

tins = 3-4 nmLside = 150 nm

105

InAs HEMTstch = 10 nm

80

90

swin

g [m

V/d

In0.7Ga0.3As HEMTs

10μn = 13,000 cm2/V-s

ON/I O

FF

70 InAs HEMTs

ubth

resh

old

VDS=0.5 VVDS = 0.5 V

I O

In0.7Ga0.3As HEMTstch = 13 nm

μn = 10,000 cm2/V-s

10 10060

S

Lg [nm]

100104

DS

LG [nm]

2020

• tch↓ + x(InAs)↑ Ion/Ioff↑, better scalability, better SCE Kim, IEDM 2007

Scaled HEMTs: Benchmarking with Si

160

180

ec.]

Si FETs (IEDM)Triple recess: IEDM 07Pt sinking160

180

ec.]

Si FETs (IEDM)Triple recess: IEDM 07Pt sinking160

180

ec.]

Si FETs (IEDM)*

Pt sinking: IEDM 08160

180

ec.]

Si FETs (IEDM)*

Pt sinking: IEDM 08

10

c]

iedm06

120

140

dsw

ing

[mV/

de

120

140

dsw

ing

[mV/

de

120

140

dsw

ing

[mV/

de

120

140

dsw

ing

[mV/

de

1iedm07

DEL

AY

[pse

c

80

100

Subt

hres

hold

80

100

Subt

hres

hold

80

100

Subt

hres

hold

80

100

Subt

hres

hold

iedm06

iedm07iedm08

InAs HEMTs(VCC = 0.5V)

GA

TE D

Si NMOSFETs(VCC = 1.1~1.3V)

iedm08VDD=0.5 V

10 10060


60


60


60

Gate Length [nm]

iedm08

100 101 1020.1

Gate Length, Lg [nm]

• Scaled to Lg=30 nm• Superior short-channel effects as compared to Si

MOSFETsMOSFETs• Lower gate delay than Si MOSFETs at lower VDD

21

What’s behind such performance?

3E+7

4E+7VDS=0.5 V

2E+7

3E+7

nj (cm

/s)

In0.7Ga0.3As channelt 13

ITRS

0E 0

1E+7

vi tch = 13 nmtins = 4 nmLside = 150 nm

Strained Si

0E+0

0 50 100 150

Lg (nm)

• High electron velocity in channel (vinj>3x107 cm/s)• Medium-K barrier• Quantized channel• 2DEG extrinsic region

22

outstanding SCE

30 nm InAs HEMT

0 8

40H

Lg = 30 nm

tch = 10 nm

0.6

0.8

0.3 V

VGS = 0.4 V

30 U

H21tins = 4 nmLside = 80 nm

0.4

I D [A

/mm

]

10

20

fT = 628 GHz

MAG

Gai

n [d

B]

0.0 0.2 0.4 0.6 0.80.0

0.2

109 1010 1011 10120

10

VGS = 0.1 VVDS = 0.6 V

fmax = 331 GHz

• Paying attention to SCE pays off in frequency response

VDS [V]10 10 10 10

Frequency [Hz]

23

• fT=628 GHz: highest fT reported on any FET on any material system

23Kim, EDL 2008

30 nm InAs HEMT by Pt Sinkingby t S g

Lg = 30 nm

tch = 10 nmKim, IEDM 20080.8

50ch

tins = 4 nmLside = 150 nm0.6

VGS = 0.4 Vm]

VGS = 0.5 V

30

40

[dB

] H21

0 2

0.4GS

I D [m

A/μ

m

20

30

H21

, Ug, M

AG Ug

MAG

fT=601 GHzfmax=609 GHz

0.0 0.2 0.4 0.6 0.80.0

0.2

109 1010 1011 10120

10

HVDS = 0.5 V, VGS = 0.3 V

• 180 nm gate stem height to reduce parasitic capacitance

VDS [V]10 10 10 10

Frequency [GHz]

24

• Enhancement mode FET: VT = 0.08 V• First transistor with both fT and fmax > 600 GHz

24

III-V HEMT vs. Si CMOS

Intel’s 65 nm CMOS60 nm HEMT

http://www chipworks com/uploadedImages/Inthttp://www.chipworks.com/uploadedImages/Intel_PMOS.bmp

Some issues: • Gate shape • Big! [footprint 1000x too big]

25

• Non self-aligned contacts

Self-Aligned InGaAs HEMT

V V

0.4

0.5

0.6

/μm

)

Vgs – VT = 0.55 V

0 35 V

Waldron, IEDM 2007

Lg=90 nm

0

0.1

0.2

0.3

Id (m

A 0.35 V

0.15 V

SiOW

Air spacer0

0 0.2 0.4 0.6 0.8 1

Vds (V)1.E-02 Vds = 0.05 V, 0.5 V

90 nm 60 nm

Id

1.E-08

1.E-06

1.E-04

Ig (A

/μm

)

Ig

VT=60 mV

Self-aligned W non-alloyed ohmic t t

1.E-12

1.E-10

-0.6 -0.4 -0.2 0 0.2 0.4

Id, I

26

contacts Vgs (V)

DIBL=55 mV/V, SS=70 mV/dec, Ion/Ioff=8x104, RS=0.24 Ω.mm

Contact scaling PadcR

WR

contact length

WR capcR

sideRBarrierR a ie(54% of RS)

To achieve target, need to eliminate barrier under contact high-K gate dielectric required

27

High-K gate dielectric also required for tins scalingequ ed o tins sca g

10-4

10-3

tins

= 10 nm tins = 7 nm Lg = 30 nm

10-6

10-5

10m

] t

ins = 4 nm

Lg 30 nmtch = 10 nmLside = 150 nm

ID

10-8

10-7

10

I D, I G

[A/μ

m

IG

10-10

10-9

10

VDS

= 0.5 V

t ↓ I ↑

-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.5010

VGS [V]

28

tins ↓ IG↑Further scaling requires high-K gate dielectric

28

From THz HEMT to III-V CMOS

Future III-V CMOSModern III-V HEMT

2929

The High-K/III-V System by ALD

• Ex-situ ALD produces high-quality interface:– Surface inversion demonstrated on p-type InGaAsp yp– Dit in mid ~1011 cm-2.eV-1 demonstrated

Al2O3/In0.52Ga0.47As

f=100 Hz-1 MHz

3030

Lin, SISC 2008

Al2O3/In0.75Ga0.25As MOSFETs

101

102

103

Vds=0.8V

m)

10-1

100

I d (μA

/ μm

Vds=0.05V

400

Vgs=0.8VL =160nm 0 8 0 4 0 0 0 4 0 8

10-4

10-3

10-2

Lg= 160 nm

300 0.6V

A/μ

m)

Lg=160nm -0.8 -0.4 0.0 0.4 0.8Vgs (V)

For Vdd=0.8 V:VT=0.2V

100

200

0.2V

0.4VI ds (μ

A TId(ON)= 399 µA/µmGmpk= 633 µS/µmIon/Ioff=1.6x103

SS 141 mV/dec 0.0 0.2 0.4 0.6 0.80 0V

Vds (V)

SS= 141 mV/dec DIBL= 116 mV/V

Wu, EDL 2009 31

The Al2O3/InGaAs InterfaceDensity-Functional Theory Molecular Dynamics (DFT-MD) simulations show high quality Al2O3/InGaAs interface

EEf

CBVB

Low InGaAs lattice

• No midgap states• Fermi level midgap consistent Low InGaAs lattice

distortion with low interface dipole

Chagarov, Surf. Sci., in press 32

ALD “Clean-up” Effecta+3 Ga‐O/S Ga‐AsAs2p Ga2pAs‐Ga

s‐S As ‐As

s+3

a+3 Ga‐O/S Ga‐AsAs2p Ga2pAs‐Ga

s‐S As ‐As

s+3

ALD half-cycle study

ect

Al2O3/In0.2Ga0.8AsSample treated in (NH ) S

Ga

After (NH4)2S etch

AsAs

Ga

After (NH4)2S etch

AsAs

- Sample treated in (NH4)2S- Precursors: TMA + H2O- In-situ XPS analysis

After TMA pulse 1After TMA pulse 1

In situ XPS analysisAfter H2O pulse 1

Aft TMA l 2

After H2O pulse 1

Aft TMA l 2

experiment evolutionAfter TMA pulse 2

After H O pulse 2

After TMA pulse 2

After H O pulse 2

• Clean-up of all As oxides and reduction of Ga+3 oxidesAfter H2O pulse 2

After 1nm Al2O3

After H2O pulse 2

After 1nm Al2O3

and reduction of Ga oxides after first TMA pulse• As-As bonding persistent

1122 1120 1118 1116 1114

e 2O3

Binding Energy (eV)

1329 1326 1323 1320 1122 1120 1118 1116 1114

e 2O3

Binding Energy (eV)

1329 1326 1323 1320Milojevic, APL 2008

33

III-V MOSFET architecture 1: Implanted Self-Aligned MOSFET

2

103Direct deposition of HfO2

Vd=1VLg=95nmS.S.=164mV/dec

p a ted Se g ed OS

100

101

102Vd=50mV

mA

/mm

)

DIBL=105mV/V

350

400Direct deposition of HfO2

V =0~2V in 0 5V step

10-2

10-1

10

I d (m150

200

250

300

d (mA

/mm

)

Vg=0 2V in 0.5V stepLg=95nm

-0.5 0.0 0.5 1.0 1.5 2.0Vg (V)

0.0 0.5 1.0 1.5 2.00

50

100

I d

Vd (V)

• 10 nm HfO2 by MOCVD• Si I/I + RTA 600 C, 60 s

34

• Lg=95 nm

34Lin, IEDM 2008

III-V MOSFET architecture 2: MOSFET with regrown ohmic contactsOS t eg o o c co tacts

G

In-situ Doped S/D for RSReduction

500Step = 0.5 V

μm) VG-VT = 0 to 3 V 10-3

μm)

V = 1 2 VG

In0.4Ga0.6As

Reduction

x

y

300

400p

re

nt I D

(μA

/μ LG = 250 nm

10-6

10-5

10-4

ur

rent

I D (A

/μ VDS 1.2 V

VDS = 0.1 V

In0.53Ga0.47As

InP

y Channel Strain Engineeringfor Mobility Enhancement

0

100

200

Dra

in C

urr

10-8

10-7

10 6

Dra

in C

u

LG = 250 nm

• 15 nm HfAlO by MOCVD

0.0 0.5 1.0 1.5 2.00

Drain Voltage VD (V)-1 0 1 2 3

Gate Voltage VG (V)

y• TaN gate, SiON spacers• In-situ Si doped InGaAs S/D by MOCVD (635 C, 2 min)

35

• Lg=250 nm

35Chin, EDL 2009

III-V MOSFET architecture 3: Implant-free gate-last MOSFETp a t ee gate ast OS

• 10 nm GGO by MBE• 5 nm AlGaAs/GaAs barrier• 5 nm AlGaAs/GaAs barrier• 10 nm In0.3Ga0.7As channel• Pt/Au gate

36

g• Lg=180 nm

Hill, EL 2007

VDS=1.5 V

Worries…

• Can we make 15 nm-class III-V MOSFETs with higher performance than equivalent Si devices?

Wh t i t d b t th t d i ?• What are we going to do about the p-type devices?

• Will III-V MOSFETs be reliable?• Will III-V MOSFETs be reliable?

• Will III-V CMOS be ready on time?y

3737

Conclusions

• III-Vs attractive for CMOS

• III-V CMOS will strongly leverage Sirather than “beyond Silicon” a III V channel will be an add on to Sirather than beyond Silicon , a III-V channel will be an add-on to Si

technology (as Cu, strain and high-K dielectrics have been in the past)

• Great challenges ahead: – Growth of III-V heterostructures on Si with thin buffer layers– Stable and reliable high-K/III-V interface with high interfacial qualityg g q y– Nanometer-scale, self-aligned, E-mode FET architecture– High quality p-channel device

38

Documents

III-VVs:’s: From THz HEMT to CMOS 158 slides.pdf•t ch↓ Æperformance degradation Æincrease InAs composition in channel 100 d ec] t ins = 3-4 nm L side = 150 nm 105 InAs HEMTs