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III-V MOSFETs for Future CMOS
J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao
Microsystems Technology LaboratoriesMassachusetts Institute of Technology
IEEE Compound Semiconductor IC SymposiumNew Orleans, LA; October 11-14, 2015
Acknowledgements:• Sponsors: DTRA, Lam Research, Northrop Grumman, NSF, Samsung• Labs at MIT: MTL, EBL
Contents
1. Motivation: Moore’s Law and MOSFET scaling2. Planar InGaAs MOSFETs 3. InGaAs FinFETs4. Nanowire InGaAs MOSFETs 5. Conclusions
2
1. Moore’s Law at 50: the end in sight?
3
Moore’s Law
Moore’s Law = exponential increase in transistor density
4
Intel microprocessors
Moore’s Law
5
?
How far can Si support Moore’s Law?
0
1
2
3
4
5
6
1980 1985 1990 1995 2000 2005 2010 2015
Supp
ly v
olta
ge (V
)
Year of introduction
Transistor scaling Voltage scaling Performance suffers
Transistor current density (planar MOSFETs):
Transistor performance saturated in recent years
Intel microprocessorsIntel microprocessors
Supply voltage:
6
7
Moore’s Law: it’s all about MOSFET scaling
Enhanced gate control improved scalability
1. New device structures:
8
Moore’s Law: it’s all about MOSFET scaling
2. New materials:Si Strained Si SiGe InGaAs
Si Strained Si SiGe Ge InGaSb
Future CMOS might involve twodifferent channel materials with two different relaxed lattice constants!
del Alamo, Nature 2011 (updated)9
III-V electronics in your pocket!
10
2. Self-aligned Planar InGaAs MOSFETs
Lin, IEDM 2012, 2013, 2014
WMo
Lee, EDL 2014; Huang, IEDM 2014
selective MOCVD
Sun, IEDM 2013, 2014 Chang, IEDM 2013
reacted NiInAs
dry-etched recess
implanted Si + selective epi
11
Self-aligned Planar InGaAs MOSFETs @ MIT
Lin, IEDM 2012, 2013, 2014
Recess-gate process:• CMOS-compatible• Refractory ohmic contacts (W/Mo)• Extensive use of RIE
WMo
0.0 0.1 0.2 0.3 0.4 0.50.00.20.40.60.81.0 Lg=20 nm
Ron=224 Ω.µm 0.4 V
I d (m
A/µm
)
Vds (V)
Vgs-Vt= 0.5 V
12
• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As • Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)
Highest performance InGaAs MOSFET
• Record gm,max = 3.1 mS/µm at Vds= 0.5 V• Ron = 190 Ω.µm
-0.4 -0.2 0.0 0.20.00.51.01.52.02.53.03.5
gm,max= 3.1 mS/µm
Lg = 80 nmVds= 0.5 V
g m (m
S/µ m
)Vgs (V)
0.0 0.1 0.2 0.3 0.4 0.50.00.20.40.60.81.01.21.4
I d (m
A/µm
)
Vds (V)
Vgs = -0.3 to 0.4 V in 0.1 V stepLg = 80 nmRon=190 Ω.µm
Lg =80 nm, tc=9 nm
Lin, IEDM 201413
Excess OFF-state current
OFF-state current enhanced with Vds
Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013
-0.6 -0.4 -0.2 0.010-11
10-9
10-7
10-5 Lg=500 nm
Vds=0.3~0.7 Vstep=50 mV
I d(A/µ
m)
Vgs (V)
Transistor fails to turn off:
Vds ↑
14
-0.4 -0.2 0.0 0.210-11
10-9
10-7
10-5 W/ BTBT+BJT W/O BTBT
Vds=0.3~0.7 Vstep=50 mV
I d (A/
µm)
Vgs (V)
Excess OFF-state current
Lg↓ OFF-state current ↑ additional bipolar gain effect due to floating body
Lin, EDL 2014
-0.6 -0.4 -0.2 0.010-11
10-9
10-7
10-5 Lg=500 nm
Vds=0.3~0.7 Vstep=50 mV
I d(A/µ
m)
Vgs (V)-0.6 -0.4 -0.2 0.0
10-8
10-7
10-6
10-5
10-4
500 nm280 nm
120 nm
T=200 KVds=0.7 V
I d (A/
µm)
Vgs-Vt (V)
Lg=80 nm
Vds ↑
Simulationsw/ BTBT+BJTw/o BTBT+BJT
Lg=500 nmLin, TED 2015
15
Planar InGaAs MOSFET scaling
• tc ↓ S ↓ but also gm,max ↓• Even at tc=3 nm, Lg,min~40 nm
planar MOSFET at limit of scaling
Lin, IEDM 2014Lin, TED 2015
0.01 0.1 1 100
1
2
3
g m,m
ax (m
S/µm
)Lg(µm)
4 nm
tc=9 nm
11 nm
12 nm7 nm
3 nm
8 nmVds=0.5 V
0.01 0.1 1 100
100
200
300
400
S min (m
V/de
c)
Lg(µm)
Vds=0.5 Vtc ↓
3 nm
Vds=0.5 V
tc=12 nm
16
0
500
1000
1500
2000
2500
3000
3500
1980 1990 2000 2010
g m(μ
S/μm
)
Year
InGaAs HEMT
InGaAs MOSFET
Benchmarking: gm in MOSFETs vs. HEMTs
del Alamo, ESSDERC 2013 (updated)
MIT MOSFETs
– Very rapid recent progress in MOSFET gm
– Best MOSFETs now match best HEMTs– No sign of stalling more progress ahead!
gm of InGaAs MOSFETs vs. HEMTs (any VDD, any Lg):
17
3. InGaAs FinFETs and Trigate MOSFETs
Kim, IEDM 2013
60 nmDry-etched fins
Epi-grownfin insidetrench
Si
Wf=30 nm
Waldron, VLSI Tech 2014
Aspect-Ratio Trapping
18
InGaAs FinFETs @ MIT
Vardi, DRC 2014, EDL 2015, IEDM 2015
0.0 0.1 0.2 0.3 0.4 0.50
5
10
15
20 Wf=12 nm
VGS=0 VI D [µ
A/µm
]
VDS [V]
VGS=0.5 VLg=5 μm
Fin etch by RIE
19
4. Nanowire InGaAs MOSFETs
Waldron, EDL 2014
Tomioka, Nature 2012Persson, EDL 2012
Nanowire MOSFET: ultimate scalable transistor
Tanaka, APEX 2010
20
Lateral vs. Vertical Nanowire MOSFETs
Yakimets, TED 2015Bao, ESSDERC 2014
Vertical NW: uncouples footprint scaling from Lg and Lc scaling power, performance and area gains wrt. Lateral NW
5 nm node
30% area reduction in 6T-SRAM19% area reduction in 32 bit multiplier
21
InGaAs Vertical Nanowires on Si by direct growth
Björk, JCG 2012
Selective-Area Epitaxy
Au seed
Vapor-Solid-Liquid (VLS) Technique
InAs NWs on Si by SAE
Riel, MRS Bull 2014
22
InGaAs VNW-MOSFETs fabricated via top-down approach @ MIT
Zhao, IEDM 2013
Top-down approach: flexible and manufacturable
15 nm
240 nm
Key enabling technologies: • BCl3/SiCl4/Ar RIE • digital etch
23
Process flowTomioka, Nature 2012Persson, DRC 2012
24
D=30 nm NW-MOSFET
Single nanowire MOSFET: • D=30 nm• Lch= 80 nm • 4.5 nm Al2O3 (EOT = 2.2 nm)
At VDS=0.5 V:• gm,pk=280 μS/μm• Ron=759 Ω.μm
0.0 0.1 0.2 0.3 0.4 0.5Vds (V)
Vgs=-0.6 V to 0.8 V in 0.1 V stepRon=759 Ω.µm (at Vgs=1 V)
0
50
100
150
200
I d (µ
A/µm
)
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60
50
100
150
200
Vgs (V)0
50
100
150
200
250
300gm, pk(Vds=0.5 V)=280 µS/µm
Vds=0.5 V
I d (µ
A/µm
)
g m (µ
S/µm
)
Zhao, IEDM 2013 25
Conclusions
1. Great recent progress on planar, fin and nanowire III-V MOSFETs
2. Vertical Nanowire III-V MOSFET: superior scalability and power/performance characteristics
3. Vertical Nanowire n- and p-type III-V MOSFET: plausible path for co-integration on Si
4. Many demonstrations of InGaAs VNW MOSFETs by bottom-up and top-down approaches
5. Many issues to work out…
26
A lot of work ahead but…exciting future for III-V electronics
27