IGLOO PLUS Starter Kit User’s Guide

IGLOO PLUS Starter Kit User’s Guide


Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5IGLOO PLUS Starter Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1 Board Components and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

IGLOO PLUS Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Connectors, Jumpers, and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 FPGA Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Key Features of AGLP125-CSG289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Decaps and Ground Post Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Potentiometer and Voltage-Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 Operation of Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Flash*Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

.DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

I/O Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

OLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Low-Cost Programming Stick (LCPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6 IGLOO PLUS Board Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Demos Included in the Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Getting Started with the IGLOO PLUS Starter Kit Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

A Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

B List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Revision 1 3

Table of Contents

C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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Introduction

IGLOO PLUS Starter Kit ContentsThe RoHS-compliant, environmentally friendly IGLOO® PLUS Starter Kit is packaged in a recyclablecardboard box made from recycled materials. This development kit includes an on-board programmerand demonstrates the ultra-low power of Microsemi® IGLOO PLUS devices. Table 1 lists the contents ofthe box.

Table 1 • IGLOO PLUS Starter Kit Contents

Quantity Contents

1 IGLOO PLUS board with AGLP125 IGLOO PLUS field programmable gate array (FPGA)

1 Programmer for use with IGLOO PLUS board

1 5 V power supply

2 USB 2.0 high-speed cables

1 Packet of jumpers

1 Microsemi Libero® System-on-Chip (SoC) software DVD

1 Quickstart Guide

Figure 1 • IGLOO PLUS Starter Kit Board

Revision 1 5

1 – Board Components and Settings

This chapter describes the components and settings for the IGLOO PLUS Starter Kit Board.

Board DescriptionThe IGLOO PLUS Starter Kit board is intended to provide a low-cost system platform for evaluatingIGLOO PLUS (AGLP) technology, such as low power, I/O state preservation during Flash*Freeze mode,and Schmitt Triggered I/Os. Other advanced features include the ability to use the FPGA I/Os of theExpansion Header as hot-swappable and the Schmitt Triggered FPGA inputs for improved noiseimmunity.

This evaluation board enables you to measure power consumption (dynamic, static, and Flash*Freezemodes) with the core operating between 1.2 V and 1.5 V. When using the board in conjunction with theMicrosemi power analysis tools, you will have a clear picture of application power consumption at eachstage in your design. In addition, the Libero SoC tool suite now includes power-driven layout (PDL),which can reduce the power consumption of designs up to 30 percent.

The evaluation board has a small form factor, measuring 3.7 inches by 4 inches, and supports anAGLP125 IGLOO PLUS device in the 14 mm × 14 mm CSG289 package. All components used on theboard, such as LEDs, reset (µA range), and oscillator, are low-power components. Also included on theevaluation board is a USB-to-UART interface to allow HyperTerminal on a PC to communicate with theIGLOO PLUS device on the board.

The top of the board has a programming stick header which allows the low-cost programming stickLCPS) to be attached to the board for programming the IGLOO PLUS AGLP125-CSG289 device(Figure 1-1). FPGA I/Os have been wired to test pin pads on the board for debug and expandability.

Note: The clock oscillator for the IGLOO PLUS Starter Kit Board is behind the board.

Figure 1-1 • IGLOO PLUS Starter Kit Board

Revision 1 7

Board Components and Settings

IGLOO PLUS Board StackupThe IGLOO PLUS board is built on a 10-layer PCB. Figure 1-1 and Figure 1-1 on page 7 show the top(L1) and bottom (L10) silkscreens. The full PCB design layout is provided on the Microsemi SoCProducts Group website, on the IGLOO PLUS Starter Kit page:

www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. To view the PCBdesign layout files, you can use the Allegro Free Physical Viewer, which can be downloaded from theCadence Allegro Downloads page.

• Top Signal (Figure 1-1 on page 7)

• GND 1

• Signal

• GND 2

• PWR 1

• PWR 2

• GND 3

• Signal

• GND 4

• Bottom Signal (Figure 1-2 on page 9)

8 Revision 1

http://www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx

http://www.cadence.com/products/pcb/pages/Downloads.aspx


Figure 1-2 • IGLOO PLUS Top Silkscreen (L1)

Revision 1 9


Figure 1-3 • IGLOO PLUS Bottom Silkscreen (L10)

10 Revision 1


Connectors, Jumpers, and Switch SettingsRecommended default jumper settings are defined in Table 1-1. The voltage selection jumpers arehighlighted in grey. Connect jumpers in the default settings described in Table 1-1 to enable the pre-programmed demo design to function correctly.

Table 1-1 • Jumper and Connector Settings

Jumper Default Setting Comment

J1 Ground post header

J2 Ground post header

J3 LC JTAG header for programmer

J4 JTAG header

J5 USB mini receptacle

J6 Pin 2-3 Remove jumper to disconnect VCCI_0 power

J7 Remove Remove jumper to disconnect external battery source

J8 Pin 2-3 Remove jumper to disconnect VCCI_1 power

J9 Pin 1-4 Select WALL, BAT, VUSB for 5V_SOURCE

Pin 1-4 = VUSB

Pin 2-4 = BAT

Pin 3-4 = WALL

J10 5 V Brick

J11 Pin 1-2 Select VCC or VCC_SWEEP for VCORE

Pin 1-2 = VCC

Pin 3-2 = VCC_SWEEP

J12 Pin 2-3 Current measurement header for VCORE

J13 Pin 2-3 Current measurement header for VCCI_3

J14 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_1

Pin 1-2 = VCC

Pin 3-2 = VCC_SWEEP

J15 Pin 3-2 Select VJTAGENB or 3.3 V

Pin 3-2 = VJTAGENB

Pin 1-2 = 3.3 V

J16 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_1

Pin 2-4 = 3.3 V

Pin 3-4 = 1.5 V or 1.2 V

Pin 1-4 = 2.5 V

J17 Pin 2-3 Current measurement header for VCCI_2

J18 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_0

Pin 1-2 = VCC

Pin 3-2 = VCC_SWEEP

Revision 1 11


J19 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_0

Pin 2-4 = 3.3 V

Pin 3-4 = 1.5 V or 1.2 V

Pin 1-4 = 2.5 V

J20 Pin 2-3 Current measurement header for VJTAG

J21 Pin 1-2 Select 3.3 V or 1.5 / 1.2 V for VJTAG

Pin 1-2 = 3.3 V

Pin 2-3 = 1.5 V or 1.2 V

J22 Pin 2-3 Current measurement header for VPUMP

J23-J24 Pin 1-2 Remove each jumper to disconnect any of the 2 FET Switches[1:2] from FPGA.

J23 = 3V3_SWITCH1

J24 = 3V3_SWITCH2

J25-J27 Pin 1-2 Remove each jumper to disconnect any of the 3 FET LEDs from FPGA.

J25 = FET_P1

J26 = FET_N

J27 = FET_P2

J28-J35 Pin 1-2 Remove each jumper to disconnect any of the 8 user DIP switches[1:8] from FPGA.

J28 = D_SWITCH1

J29 = D_SWITCH2

J30 = D_SWITCH3

J31 = D_SWITCH4

J32 = D_SWITCH5

J33 = D_SWITCH6

J34 = D_SWITCH7

J35 = D_SWITCH8

J36-J39 Pin 1-2 Remove each jumper to disconnect any of the 4 push-button switches[1:4] from FPGA.

J36 = SWITCH1

J37 = SWITCH2

J38 = SWITCH3

J39 = SWITCH4

J40-J47 Pin 1-2 Remove each jumper to disconnect any of the 8 user LEDs[1:8] from FPGA.

J42 = LED1

J41 = LED2

J40 = LED3

J47 = LED4

J46 = LED5

J45 = LED6

J44 = LED7

J43 = LED8

Table 1-1 • Jumper and Connector Settings (continued)

Jumper Default Setting Comment

12 Revision 1


Table 1-2 • Switch Settings

Switch Default Setting Comment

SW1–SW4 Push-button switches for SWITCH[1:4]

SW5 CLOSE Contains DIP switches for 3V3_SWITCH[1:2]

DSW5 CLOSE Contains DIP switches for D_SWITCH[1:8]

SW7 Push-button switch for system reset PBRESET_N

SW8 OFF Flash*Freeze: To enable Flash*Freeze mode, SW8 toward ON.

In Flash*Freeze mode, current consumption of FPGA goes below 50 µA.

Revision 1 13

2 – FPGA Description

The IGLOO PLUS board is populated with an IGLOO PLUS AGLP125-CSG289 FPGA.

Key Features of AGLP125-CSG289• Low power

• 1.2 V to 1.5 V core voltage support for low power

• Supports single-voltage system operation

• 5 µW power consumption in Flash*Freeze mode

• Low-power active FPGA operation

• Flash*Freeze technology enables ultra-low power consumption while maintaining FPGA content

• Configurable hold previous state, tristate, HIGH, or LOW state per I/O in Flash*Freeze mode

• Easy entry to / exit from ultra-low-power Flash*Freeze mode

• Reprogrammable flash technology

• In-system programming (ISP) and security

• High-performance routing hierarchy

• Advanced I/O

• Selectable Schmitt trigger inputs

• Clock conditioning circuit (CCC) and PLL

• Embedded memory

Table 2-1 lists specifications for the AGLP125-CSG289 FPGA.

For further information, refer to the IGLOO PLUS datasheet: www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf

Table 2-1 • IGLOO PLUS AGLP125-CSG289 FPGA Features

Feature Specification

System Gates 125,000

Typical Equivalent Macrocells 1,024

VersaTiles (D-flip-flops) 3,120

Flash*Freeze Mode (Typical, µW) 16

RAM kbits (1,024 bits) 36

4,608-Bit Blocks 8

FlashROM (bits) 1 K

Secure (AES) ISP Yes

Integrated PLLs in CCCs 1

VersaNet Globals 18

I/O Banks 4

Maximum User I/Os 212

Revision 1 15

http://www.actel.com/documents/IGLOOPLUS_DS.pdf

http://www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf

FPGA Description

Power and Ground PinsFigure 2-1 shows the power and ground pins for AGLP125-CSG289.

Figure 2-1 • Power and Ground Pins for AGLP125-CSG289

VCCPLF

VCCIB0_1B7

VCCIB0_2B12

VCCIB0_3C5

VCCIB0_4E11

VCCIB1_1E16

VCCIB1_2H15

VCCIB1_3L14

VCCIB1_4M17

VCCIB2_1N10

VCCIB2_2P13

VCCIB2_3R6

VCCIB2_4T9

VCCIB3_1E1

VCCIB3_2F4

VCCIB3_3J3

VCCIB3_4M2

VCC1L9

VCC2G9

VCC3J7

VCC4J11

VCOMPLFH1

VCCPLFJ1

GND1A4

GND2A9

GND3A14

GND4B2

GND5B17

GND6C10

GND7C15

GND8D3

GND9D8

GND10D13

GND11F14

GND12G2

GND13G7

GND14G8

GND15G10

GND16G11

GND17G17

GND18H7

GND19H8

GND20H9

GND21H10

GND22H11

GND23J8

GND24J9

GND25J10

GND26K1

GND27K7

GND28K8

GND29K9

GND30K10

GND31K11

GND32K16

GND33L4

GND34L7

GND35L8

GND36L10

GND37L11

GND38N5

GND39N15

GND40P3

GND41P8

GND42R1

GND43R11

GND44T4

GND45T14

GND46U2

GND47U7

GND48U12

SEC 5/6AGLP125 CSG289

POWER G

ND

U5E

AGLP125-CSG289

SEC 5/6

POWER G

ND

U5E

16 Revision 1


Bank I/O SignalsFigure 2-2 through Figure 2-5 on page 19 show the schematics for the bank I/O signals.

Figure 2-2 • Bank 0 I/O Signals for AGLP125-CSG289

AGL_B0_PIN_D5

AGL_B0_PIN_A3

AGL_B0_PIN_A2

AGL_B0_PIN_D6

AGL_B0_PIN_F7

AGL_B0_PIN_B4

AGL_B0_PIN_C6

AGL_B0_PIN_E7

AGL_B0_PIN_F8

AGL_B0_PIN_A5

AGL_B0_PIN_C7

AGL_B0_PIN_E8

AGL_B0_PIN_A7

AGL_B0_PIN_F9

AGL_B0_PIN_A8

AGL_B0_PIN_E9

AGL_B0_PIN_D9

AGL_B0_PIN_E10

AGL_B0_PIN_D12

AGL_B0_PIN_E12

AGL_B0_PIN_E5

AGL_B0_PIN_C16

AGL_B0_PIN_A1

AGL_B0_PIN_E13

AGL_B0_PIN_B16

AGL_B0_PIN_D14

AGL_B0_PIN_B3

AGL_B0_PIN_C4

AGL_B0_PIN_E6

AGL_B0_PIN_B5

AGL_B0_PIN_D7

AGL_B0_PIN_B6

AGL_B0_PIN_A6

AGL_B0_PIN_C8

AGL_B0_PIN_C2

AGL_B0_PIN_C3

AGL_B0_PIN_D15

AGL_B0_PIN_A17

AGL_B0_PIN_D4

AGL_B0_PIN_B1

AGL_B0_PIN_F10

AGL_B0_PIN_B9

AGL_B0_PIN_B8

AGL_B0_PIN_C9

AGL_B0_PIN_A10

AGL_B0_PIN_B10

GPIOA_29 {3}

GPIOA_33 {3}

GPIOA_31 {3}

GPIOA_35 {3}

GPIOA_9 {3}

GPIOA_13 {3}

GPIOA_15 {3}

GPIOA_17 {3}

GPIOA_19 {3}

GPIOA_21 {3}

GPIOA_23 {3}

GPIOA_7 {3}

GPIOA_5 {3}

GPIOA_1 {3}

GPIOA_3 {3}

GPIOA_25 {3}

GPIOA_27 {3}

IO06RSB0B3

IO07RSB0D5

IO08RSB0A3

IO09RSB0C4

IO10RSB0D6

IO11RSB0A2

IO12RSB0E6

IO13RSB0B4

IO14RSB0F7

IO15RSB0B5

IO16RSB0E7

IO17RSB0C6

IO18RSB0D7

IO19RSB0A5

IO20RSB0F8

IO21RSB0B6

IO22RSB0E8

IO23RSB0C7

IO24RSB0A6

IO25RSB0F9

IO26RSB0A7

IO27RSB0C8

IO28RSB0B8

IO29RSB0F10

IO30RSB0A8

IO31RSB0B9

IO32RSB0E9

IO33RSB0C9

IO34RSB0D9

IO35RSB0A10

IO36RSB0E10

IO37RSB0B10

IO56RSB0E12

IO55RSB0D12

IO54RSB0A16

IO53RSB0F12

IO52RSB0C14

IO51RSB0F11

IO50RSB0C13

IO49RSB0B15

IO48RSB0A15

IO47RSB0D11

IO46RSB0B14

IO45RSB0C12

IO44RSB0B13

IO43RSB0C11

IO42RSB0A13

IO41RSB0D10

IO40RSB0A12

IO39RSB0B11

IO38RSB0A11

GAA0/IO00RSB0C2

GAA1/IO01RSB0B1

GAB0/IO02RSB0D4

GAB1/IO03RSB0A1

GAC0/IO04RSB0C3

GAC1/IO05RSB0E5

GBA0/IO61RSB0C16

GBA1/IO62RSB0D15

GBB0/IO59RSB0D14

GBB1/IO60RSB0E13

GBC0/IO57RSB0A17

GBC1/IO58RSB0B16

BANK0

AGLP125 CSG289SEC 1/6

U5A

AGLP125-CSG289

BANK0

SEC 1/6

U5A

TP86TP

TP86TP

TP69TP

TP69TP

TP99TP

TP99TP

TP71TP TP71TP

TP106TP TP106TP

TP239TP

TP239TP

TP102 TPTP102 TP

TP83TP

TP83TP

TP80 TPTP80 TP

TP92 TPTP92 TP

TP123TP

TP123TP

TP75TP TP75TP

TP95TP

TP95TP

TP207TP

TP207TP

TP109TP

TP109TP

TP76 TPTP76 TP

TP124 TPTP124 TP

TP120TP

TP120TP

TP100 TPTP100 TP

TP103TP

TP103TP

TP111TP

TP111TP

TP101TP

TP101TP

TP94TP

TP94TP

TP97 TPTP97 TP

TP105TP

TP105TP

TP240TP

TP240TP

TP119 TPTP119 TP

TP22 TPTP22 TP

TP98TP

TP98TP

TP91TP

TP91TP

TP74TP TP74TP

TP82 TPTP82 TP

TP88 TPTP88 TP

TP96TP

TP96TP

TP247TP

TP247TP

TP117 TPTP117 TP

TP112TP

TP112TP

TP77 TPTP77 TP

TP81 TPTP81 TP

TP68 TPTP68 TP

TP89TP

TP89TP

TP121TP

TP121TP

TP236TP

TP236TP

TP118TP

TP118TP

TP114TP

TP114TP

TP90TP

TP90TP

TP122TP

TP122TP

TP93TP

TP93TP

TP115TP

TP115TP

TP87TP

TP87TP

TP85TP

TP85TP

TP72TP

TP72TP

TP73TP

TP73TP

TP116TP

TP116TP

TP78 TPTP78 TP

TP113TP

TP113TP

TP107TP TP107TP

TP110TP

TP110TP

TP84TP

TP84TP

TP222TP

TP222TP

TP70TP

TP70TP

TP108TP

TP108TP

TP79 TPTP79 TP

Revision 1 17

FPGA Description


AGL_B1_PIN_L16

AGL_B1_PIN_K15

AGL_B1_PIN_K14

AGL_B1_PIN_M16

AGL_B1_PIN_L15

AGL_B1_PIN_L13

AGL_B1_PIN_N17

AGL_B1_PIN_L12

AGL_B1_PIN_N16

AGL_B1_PIN_E14

AGL_B1_PIN_F13

AGL_B1_PIN_J17

AGL_B1_PIN_J16

AGL_B1_PIN_J12

AGL_B1_PIN_M14

AGL_B1_PIN_K13

AGL_B1_PIN_M15

AGL_B1_PIN_E15

AGL_B1_PIN_H14

AGL_B1_PIN_H16

AGL_B1_PIN_J13

AGL_B1_PIN_H17

AGL_B1_PIN_M13

AGL_B1_PIN_H12

AGL_B1_PIN_K17

GPIOA_34{3}

GPIOA_36{3}

GPIOA_26{3}

GPIOA_28{3}

GPIOA_30{3}

GPIOA_32{3}

GPIOA_10{3}

GPIOA_8{3}

GPIOA_6{3}

GPIOA_12{3}

GPIOA_16{3}

GPIOA_18{3}

GPIOA_20{3}

GPIOA_24{3}

GPIOA_22{3}

GPIOA_2{3}

GPIOA_4{3}

TP19 TPTP19 TP

TP37TP

TP37TP

TP49TP

TP49TP

TP44TP

TP44TP

TP38TP

TP38TP

TP21TP

TP21TP

TP28TP

TP28TP

TP40TP

TP40TP

TP47TP

TP47TP

TP46TP TP46TP

TP50 TPTP50 TP

TP20 TPTP20 TPTP32

TPTP32

TP

TP27TP

TP27TP

TP34TP TP34TP

TP33TP

TP33TP

TP223 TPTP223 TP

TP43TP

TP43TP

TP36TP

TP36TP

TP16TP

TP16TP

TP26TP TP26TP

TP210TP

TP210TP

TP183TP

TP183TP

TP30TP

TP30TP

TP42 TPTP42 TP

TP226TP

TP226TP

TP208 TPTP208 TP

TP17TP

TP17TP

TP48 TPTP48 TP

TP142TP

TP142TP

TP25TP

TP25TP

TP45TP TP45TP

TP35TP TP35TP

TP162TP

TP162TP

TP41TP

TP41TP

IO64RSB1G13

IO66RSB1D16

IO68RSB1C17

IO69RSB1G14

IO70RSB1D17

IO71RSB1F16

IO72RSB1G12

IO73RSB1E17

IO74RSB1H13

IO75RSB1F15

IO76RSB1G16

IO77RSB1F17

IO78RSB1G15

IO88RSB1K12

IO89RSB1J15

IO90RSB1J14

IO91RSB1L17

IO92RSB1L16

IO93RSB1K15

IO94RSB1K13

IO95RSB1K14

IO96RSB1M16

IO97RSB1M15

IO98RSB1L15

GBA2/IO63RSB1E14

GBB2/IO65RSB1E15

GBC2/IO67RSB1F13

GCA0/IO84RSB1H14

GCA1/IO83RSB1J17

GCA2/IO85RSB1H16

GCB0/IO82RSB1J16

GCB1/IO81RSB1J13

GCB2/IO86RSB1J12

GCC0/IO80RSB1H17

GCC1/IO79RSB1H12

GCC2/IO87RSB1K17

GDA0/IO104RSB1M14

GDA1/IO103RSB1M13

GDB0/IO102RSB1N16

GDB1/IO101RSB1L13

GDC0/IO100RSB1N17

GDC1/IO99RSB1L12

BANK

1


U5B

BANK

1

SEC 2/6

U5B

AGLP125-CSG289

TP104 TPTP104 TP

TP29 TPTP29 TP

TP24TP

TP24TP

TP18TP TP18TP

TP39TP

TP39TP

TP31 TPTP31 TP

TP23TP

TP23TP


AGL_B2_PIN_P12

AGL_B2_PIN_M12

AGL_B2_PIN_T15

AGL_B2_PIN_R13

AGL_B2_PIN_R12

AGL_B2_PIN_N11

AGL_B2_PIN_M11

AGL_B2_PIN_T13

AGL_B2_PIN_U13

AGL_B2_PIN_T12

AGL_B2_PIN_P10

AGL_B2_PIN_T11

AGL_B2_PIN_M10

AGL_B2_PIN_R10

AGL_B2_PIN_T10

AGL_B2_PIN_P9

AGL_B2_PIN_U10

AGL_B2_PIN_R9

AGL_B2_PIN_M9

AGL_B2_PIN_U9

AGL_B2_PIN_N9

AGL_B2_PIN_U8

AGL_B2_PIN_R3

AGL_B2_PIN_M7

AGL_B2_PIN_P4

AGL_B2_PIN_M8

AGL_B2_PIN_R2

AGL_B2_PIN_P15

AGL_B2_PIN_N13

AGL_B2_PIN_P16

AGL_B2_PIN_T2

AGL_B2_PIN_N8

AGL_B2_PIN_U5

AGL_B2_PIN_N7

AGL_B2_PIN_T5

AGL_B2_PIN_U4

AGL_B2_PIN_T6

AGL_B2_PIN_U6

AGL_B2_PIN_R8

AGL_B2_PIN_T7

AGL_B2_PIN_N12

AGL_B2_PIN_R14

AGL_B2_PIN_U15

AGL_B2_PIN_U14

AGL_B2_PIN_U11

AGL_B2_PIN_P11

AGL_B2_PIN_P7

AGL_B2_PIN_R4

AGL_B2_PIN_R5

AGL_B2_PIN_U3

AGL_B2_PIN_T3

AGL_B2_PIN_P6

AGL_B2_PIN_N6

AGL_B2_PIN_P5

AGL_B2_PIN_T8

AGL_B2_PIN_R7

IGLOO_FF [6]

PACER_D2[6]

PACER_D0[6]

PACER_RES#[6]

TP143TP

TP143TP

TP147TP

TP147TP

TP177TP

TP177TP

TP144TP

TP144TP

TP137TP

TP137TP

TP149TP

TP149TP

TP171TP

TP171TP

TP182TP

TP182TP

TP168TP

TP168TP

TP128TP

TP128TP

TP179TP

TP179TP

TP154TP TP154TP

TP133TP

TP133TP

TP151TP

TP151TP

TP134TP

TP134TP

TP175TP

TP175TP

TP138TP

TP138TP

TP136TP

TP136TP

TP172 TPTP172 TP

TP148TP

TP148TP

TP140TP

TP140TP

TP173TP

TP173TP

TP178TP

TP178TP

TP130TP

TP130TP

TP126TP

TP126TP

TP141TP

TP141TP

TP127TP

TP127TP

TP163TP

TP163TP

IO108RSB2P14

IO109RSB2N14

IO110RSB2R15

IO111RSB2N12

IO112RSB2P12

IO113RSB2M12

IO114RSB2R14

IO115RSB2T15

IO116RSB2R13

IO117RSB2U15

IO118RSB2R12

IO119RSB2N11

IO120RSB2U14

IO121RSB2M11

IO122RSB2T13

IO123RSB2U13

IO124RSB2T12

IO125RSB2P10

IO126RSB2P11

IO127RSB2T11

IO128RSB2M10

IO129RSB2U11

IO130RSB2R10

IO131RSB2T10

IO132RSB2P9

IO133RSB2U10

IO134RSB2R9

IO135RSB2M9

IO136RSB2U9

IO137RSB2N9

IO138RSB2U8

IO139RSB2T8

IO140RSB2T7

IO141RSB2R8

IO142RSB2U6

IO143RSB2T6

IO144RSB2N8

IO145RSB2R7

IO146RSB2U5

IO147RSB2T5

IO148RSB2N7

IO149RSB2U4

IO150RSB2R5

IO151RSB2U3

IO152RSB2P7

IO153RSB2T3

IO154RSB2P6

IO155RSB2R4

IO156RSB2N6

IO157RSB2P5

IO158RSB2R3

IO159RSB2M7

IO160RSB2P4

IO161RSB2M8

FF/GEB2/IO163RSB2U1

GDA2/IO105RSB2P15

GDB2/IO106RSB2N13

GDC2/IO107RSB2P16

GEA2/IO164RSB2R2

GEC2/IO162RSB2T2


BANK

2

U5C

AGLP125-CSG289

SEC 3/6

BANK

2

U5C

TP155TP TP155TP

TP170TP

TP170TP

TP160TP

TP160TP

TP158TP

TP158TP

TP164TP

TP164TP

TP153TP

TP153TP

TP181TP

TP181TP

TP288TP TP288TP

TP174TP TP174TP

TP161TP

TP161TP

TP125TP TP125TP

TP145TP TP145TP

TP150TP

TP150TP

TP157TP

TP157TP

TP135TP

TP135TP

TP180TP

TP180TP

TP132TP

TP132TP

TP139TP

TP139TP

TP131TP

TP131TP

TP289TP TP289TP

TP152TP

TP152TP

TP287TP TP287TP

TP169TP

TP169TP

TP156TP TP156TP

TP176TP TP176TP

TP167TP

TP167TP

TP159TP

TP159TP

TP129TP

TP129TP

18 Revision 1



AGL_B3_PIN_H4

AGL_B3_PIN_G3

AGL_B3_PIN_H5

AGL_B3_PIN_G5

AGL_B3_PIN_G4

AGL_B3_PIN_G6

AGL_B3_PIN_F6

AGL_B3_PIN_J2

AGL_B3_PIN_L1

AGL_B3_PIN_H2

AGL_B3_PIN_H6

AGL_B3_PIN_K2

AGL_B3_PIN_K3

AGL_B3_PIN_F5

AGL_B3_PIN_E3

AGL_B3_PIN_N4

AGL_B3_PIN_T1

AGL_B3_PIN_E4

AGL_B3_PIN_M6

AGL_B3_PIN_N3

AGL_B3_PIN_L6

AGL_B3_PIN_M5

AGL_B3_PIN_N2

AGL_B3_PIN_P1

AGL_B3_PIN_M3

AGL_B3_PIN_M4

AGL_B3_PIN_P2

AGL_B3_PIN_L5

AGL_B3_PIN_K5

AGL_B3_PIN_K6

AGL_B3_PIN_J6

AGL_B3_PIN_L3

AGL_B3_PIN_J5

AGL_B3_PIN_H3

AGL_B3_PIN_J4

AGL_B3_PIN_G1

OSC_CLK [6]

PBRESET_N [6]

TP242 TPTP242 TP

TP235 TPTP235 TP

TP248 TPTP248 TP

TP215TP

TP215TP

TP241 TPTP241 TP

IO171RSB3P2

IO172RSB3M4

IO173RSB3L5

IO174RSB3P1

IO175RSB3K5

IO176RSB3M3

IO177RSB3K6

IO178RSB3N2

IO179RSB3K4

IO180RSB3N1

IO181RSB3J6

IO182RSB3L3

IO183RSB3J5

IO184RSB3M1

IO185RSB3J4

IO195RSB3H3

IO196RSB3F2

IO197RSB3H4

IO198RSB3G3

IO199RSB3H5

IO200RSB3E2

IO201RSB3G5

IO202RSB3F3

IO203RSB3G4

IO204RSB3D1

IO205RSB3D2

IO206RSB3G6

IO208RSB3F6

IO210RSB3C1

GAA2/IO211RSB3E4

GAB2/IO209RSB3F5

GAC2/IO207RSB3E3

GEA0/IO165RSB3N4

GEA1/IO166RSB3T1

GEB0/IO167RSB3M5

GEB1/IO168RSB3M6

GEC0/IO169RSB3N3

GEC1/IO170RSB3L6

GFA0/IO189RSB3K2

GFA1/IO190RSB3J2

GFA2/IO188RSB3L1

GFB0/IO191RSB3H2

GFB1/IO192RSB3H6

GFB2/IO187RSB3K3

GFC0/IO193RSB3G1

GFC1/IO194RSB3F1

GFC2/IO186RSB3L2BA

NK3


U5D

AGLP125-CSG289

BANK

3

SEC 4/6

U5D

TP206 TPTP206 TP

TP213TP

TP213TP

TP209TP

TP209TP

TP225TP

TP225TP

TP203TP

TP203TP

TP218 TPTP218 TP

TP214 TPTP214 TP

TP245 TPTP245 TP

TP227TP

TP227TP

TP224 TPTP224 TP

TP249 TPTP249 TP

Revision 1 19

FPGA Description

JTAG PinsThe AGLP125-CSG289 has advanced I/O features such as JTAG pins for IEEE 1149.1 JTAG BoundaryScan Test. These pins are utilized during programming of the FPGA (Figure 2-6). Low-power flashdevices have a separate bank for these dedicated JTAG pins. The JTAG pins can be run at any voltagefrom 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even ifthe device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must besupplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/Obank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAGinterface is neither used or planned for use, the VJTAG pin together with the TRST pin could be tied toGND.

VJTAG is the ability to switch between 3.3 V and 1.5 V / 1.2 V source using jumper J21. Four-pin headers can be used for current measurement of the VJTAG and VPUMP rails.

Figure 2-6 • JTAG Pins

V3P3

1V5_1V2

V3P3

VJTAG [6]

VPUMP [6]

VJTAG [6]

VPUMP [6]

TDI[6]

TCK[6]

TRST[6]

TMS[6]

TDO [6]R48 39R48 39

1234

J20

HDR_4PIN

J20

HDR_4PIN

TCKU16

TDIT16

TMSR16

TRSTR17

VJTAGP17

TDOT17

VPUMPU17


JTAG

U5F

SEC 6/6

JTAG

U5F

AGLP125-CSG289

1

2

3

J21

HDR_3PIN

J21

HDR_3PIN

1234

J22

HDR_4PIN

J22

HDR_4PIN

20 Revision 1


Decaps and Ground Post SchematicsThe schematics for the decaps and ground post are shown in Figure 2-7.

Figure 2-7 • Schematics for Decaps and Ground Post

VCCI_1 VCCI_2 VCCI_3

VCORE

VCCI_0

DECAPS FOR I/O BANK0 , BANK1 ,BANK2 & BANK3

DECAPS FOR VCORE

GROUND POST

C2

90

.1u

FC

29

0.1

uF

C5

50

.1u

FC

55

0.1

uF

C5

60

.1u

FC

56

0.1

uF

C5

70

.01

uF

C5

70

.01

uF

C5

10

.01

uF

C5

10

.01

uF

C4

80

.1u

FC

48

0.1

uF

C5

80

.01

uF

C5

80

.01

uF

C3

00

.1u

FC

30

0.1

uF

C4

40

.01

uF

C4

40

.01

uF

C4

90

.01

uF

C4

90

.01

uF

C5

20

.01

uF

C5

20

.01

uF

+C5

4

10

uF

16

V

+C5

4

10

uF

16

V

+C3

1

10

uF

16

V

+C3

1

10

uF

16

V

+C4

3

10

uF

16

V

+C4

3

10

uF

16

V

C3

80

.1u

FC

38

0.1

uF

1

J2

HEADER 1

J2

HEADER 1

C3

60

.1u

FC

36

0.1

uF

1

J1

HEADER 1

J1

HEADER 1

C2

80

.01

uF

C2

80

.01

uF

C4

10

.1u

FC

41

0.1

uF

+C5

3

10

uF

16

V

+C5

3

10

uF

16

V

C2

70

.01

uF

C2

70

.01

uF

C4

00

.1u

FC

40

0.1

uF

C4

50

.01

uF

C4

50

.01

uF

C4

60

.01

uF

C4

60

.01

uF

C4

70

.01

uF

C4

70

.01

uF

+C3

3

10

uF

16

V

+C3

3

10

uF

16

V

Revision 1 21

3 – Power

The IGLOO PLUS development board is powered through an external voltage power brick or USB. Theboard does not switch seamlessly between the power brick and USB, so the 4-pin header and jumpermust be used to select the desired power source. In the USB option, the in-rush current meets the USBspecifications (see Figure 3-1). The power brick option is provided in applications when 100% of the totalI/Os are utilized and USB power is insufficient. A green LED next to the USB jack is ON whenever theUSB power supply is connected.

The development board has an input of a 5 V supply from the power brick or USB. Protection diodes areused to protect against negative voltage. Three voltage rails are provided, as shown in Table 3-1 (3.3 V,2.5 V, and 1.5 V).

The regulator can be switched between the 1.5 V and 1.2 V rail because the FPGA core functions at1.2 V, but is programmed at 1.5 V.

Table 3-1 • Power Regulator Current Ratings

Regulator Current Rating

3.3 V 2 A

2.5V 1 A

1.5 V / 1.2 V 500 mA

Figure 3-1 • USB Active Inrush Limiter

5V

WALL

VUSB5V_USB

5V_SOURCE

VUSB

BAT

ACTIVE INRUSH LIMITER

Q1 ONLYINSTALLED ONFACTORY DEMO

5V BRICK

C5

0.1uF

C5

0.1uF

1

2

3

4

J9

4PIN_HEADER

J9

4PIN_HEADER

C40.027UF

C0402

C40.027UF

C0402 3

1 4256 Q1

SI3407DV

Q1

SI3407DV

231

J10

CONN JACK PWRMfg P/N = PJ-002AHManufacturer = CUI INC

J10

CONN JACK PWRMfg P/N = PJ-002AHManufacturer = CUI INC

R522 OHMR0402

R522 OHMR0402

R65

10K

R65

10K

C8

0.1uF

C8

0.1uF

R8220KR0402

R8220KR0402

R622 OHMR0402

R622 OHMR0402

R42.7KR0402

R42.7KR0402

3

14256Q2

Si3407DV

Q2

Si3407DV

C3

0.1uF

C3

0.1uF

C6

0.1uF

C6

0.1uF

13

2

D10

BAT54

D10

BAT54

C7

0.1uF

C7

0.1uF

Revision 1 23

Power

Power ModesIn addition to the board, the IGLOO PLUS FPGA offers power advantages. Some key power advantagesof the IGLOO PLUS FPGAs are as follows:

• Flash*Freeze technology enables easy entry and exit from the static Low-power mode, whereIGLOO consumes as little as 5 µW while retaining the contents of the system memory and dataregisters.

• Sleep (and shutdown) mode allows the IGLOO PLUS FPGA core power supply (or all powersupplies) to be powered down when functionally is not required, while the rest of the systemremains powered.

• The user low static ICC macro (ULSICC) reduces IGLOO PLUS FPGA dynamic and static powerconsumption. The ULSICC macro, when enabled, disables the FlashROM, reducing the overallpower of the device.

Table 3-2 gives a summary of the power modes available with IGLOO PLUS devices in general and isextracted from the “Flash*Freeze Technology and Low Power Modes” chapter of the IGLOO PLUSFPGA Fabric User’s Guide.

Table 3-2 • Power Modes

Mode VCC VCCI Core ClocksULSICC Macro

To Enter Mode

To Resume Operation Trigger

Active On On On On N/A Initiate clock None –

Static Idle On On On Off N/A Stop clock Initiate clock External

Flash*Freeze Type 1

On On On On* N/A Assert FF pin Deassert FF pin

External

Flash*Freeze Type 2

On On On Ona Used to enter Flash*Freeze mode

Assert FF pin and LSICC

Deassert FF pin

External

Sleep On Off Off Off N/A Shut down VCC

Turn on VCC supply

External

Shutdown Off Off Off Off N/A Shut down VCCand VCCI supplies

Turn on VCC and VCCI supplies

External

a. External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL will be turned off automatically.

24 Revision 1

http://www.actel.com/documents/IGLOOPLUS_UG.pdf



BatteryIn addition to the power brick and USB, this board provides the option to power-up via battery. No batterycasing is provided on the board. Jumpers should be set correctly to select the option of either poweringthrough a wall/USB or through batteries hooked up externally. To provide a 3 V input source from battery,two AA Alkaline cells may be used. A 2-pin jumper for VBAT and GND must be provided to the input ofthe main regulator to give the option of either powering through a wall/USB or powering through batterieshooked up externally.

Potentiometer and Voltage-Sweep A potentiometer is located on the left hand side of the board to provide the voltage-sweep function tosweep VCC (Figure 3-3). One primary function of the potentiometer is to show battery operation on theIGLOO PLUS device and how the FPGA can operate successfully even if VCC experiences a drop involtage. You can measure the lowest possible VCC for battery operations. When using the potentiometer,you should also monitor the VCC via current measurement headers (Figure 3-4 on page 26) to make sureit does not go beyond the specified value.

Figure 3-2 • Battery Header and Power Input Schematics

BATEXTERNALBATTERYSOURCE1

2

J7

BATTERY1x2_100MIL

J7

BATTERY1x2_100MIL

Figure 3-3 • Current Measurement Headers

VCCI_0

VCCI_1

VCCI_2

VCCI_3

VCC

VJTAG

VPUMP

3.3 V

CurrentMeasurement IGLOO PLUS

2.5 V

VCCI-Sweep

VCCI-Sweep

VCCI-Sweep

3.3 V

3.3 V

1.5 V

3.3 V

3.3 V

Revision 1 25

Power

Current MeasurementOnce the IGLOO PLUS evaluation board is powered up, you can evaluate power consumption using thecurrent measurement four-pin headers on the board (Figure 3-5). Current measurement can be madewithout powering down the board.

Four-pin headers are used for current measurement of the rails shown in Figure 3-6 on page 27. Allbanks are separated and two of the banks have an option to power-up though a 3.3 V or 2.5 V source, asshown in Figure 3-7 on page 27. Voltage sources can be selected using jumpers or can be selected tosweep between 1.2 V and 1.5 V using the potentiometer on the development board.

Figure 3-4 • Schematic for Potentiometer

1V5_1V2

VCC_SWEEP

13

2

RV1

5K pot

RV1

5K pot

C3

51

uF

C3

51

uF

Set the multimeter to measure current and attach the probes to pins 1 and 4 when the board is in normal operation.

Remove jumper from pins 2-3 for current measurement without

powering down.

Figure 3-5 • Current Measurement 4-Pin Headers

26 Revision 1


The schematic in Figure 3-7 shows the options for power-up.

Figure 3-6 • Current Measurement Headers for Power Rails

VCCI_0

VCCI_1

VCCI_2

VCCI_3

VCC

VJTAG

VPUMP

CurrentMeasurement IGLOO PLUS

3.3 V

3.3 V

3.3 V

1.5 V

3.3 V or 2.5 V

3.3 V or 2.5 V

3.3 V

Figure 3-7 • Power-Up Options

VCORE

VCCI_1

VCCI_0

VCCI_2

VCCI_3

1V5_1V2

V3P3

V3P3

V3P3

2V5

1V5_1V2

V3P3

2V5

1V5_1V2

VCC_SWEEP

VCC_SWEEP

VCC_SWEEP

1234

J12

HDR_4PIN

J12

HDR_4PIN

1234

J8

HDR_4PIN

J8

HDR_4PIN

1

2

3

J18

HDR_3PIN

J18

HDR_3PIN

1

2

3

J14

HDR_3PIN

J14

HDR_3PIN

1

2

3

4

J16

4PIN_HEADER

J16

4PIN_HEADER

1

2

3

J11

HDR_3PIN

J11

HDR_3PIN

1234

J17

HDR_4PIN

J17

HDR_4PIN

1

2

3

4

J19

4PIN_HEADER

J19

4PIN_HEADER

1234

J13

HDR_4PIN

J13

HDR_4PIN

1234J6

HDR_4PIN

J6

HDR_4PIN

Revision 1 27

4 – Operation of Board Components

This chapter describes operation of the IGLOO PLUS evaluation board.

Clock OscillatorOne 20 MHz clock oscillator with 50 PPM is provided on the board. This clock oscillator is connected tothe FPGA to provide a system or reference clock. The PLL can be configured and instantiated in theFPGA to generate a wide range of clock frequencies.

ReferenceFor more information, refer to the IGLOO PLUS Starter Kit website page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.

SchematicFigure 4-1 shows the schematic for the clock oscillator.

ResetAn RC type push-button reset switch to the FPGA is provided on-board. The Schmitt Trigger chip (U13),however, is NOT populated. An on-board Schmitt Trigger chip is not required because Schmitt Trigger isone of the many advanced I/O features of the IGLOO PLUS FPGA family. To improve noise immunity,ensure that the Schmitt Trigger option for this reset input pin is enabled in the FPGA design. If the IGLOOPLUS FPGA is swapped out with a device that does not have the advance Schmitt Trigger I/O feature,the Schmitt Trigger chip (U13) should be populated.

Figure 4-1 • Clock Oscillator Schematic

V3P3

OSC_CLK [4]

R4310KR4310K

R64

22

R64

22C39

0.1

uF

C39

0.1

uF

OUT_EN1

GND2

OUTPUT3

VDD4

U10

OSCILLATORMfg P/N = SIT8002AC-43-33EManufacturer = SI TIME

U10

OSCILLATORMfg P/N = SIT8002AC-43-33EManufacturer = SI TIME

Revision 1 29

http://www.actel.com/products/hardware/devkits_boards/iglooplus_starter.aspx

Operation of Board Components

SchematicFigure 4-2 shows the schematic for reset.

Flash*Freeze ModeThe IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which retainsall SRAM and register information and can still quickly return to normal operation (Figure 4-1).

Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode byactivating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os,and clocks can still be driven and can be toggling without impact on power consumption, and the deviceretains all core registers, SRAM information, and I/O states. I/Os can be individually configured to eitherhold their previous state or can be tristated during Flash*Freeze mode.

There are two ways to use Flash*Freeze mode. In Flash*Freeze type 1, entering and exiting the mode isexclusively controlled by the assertion and deassertion of the FF pin. This enables an external processoror human interface device to directly control Flash*Freeze mode. In Flash*Freeze mode type 2, enteringand exiting the mode is controlled by both the FF pin AND user-defined logic. Flash*Freeze managementIP can be used in type 2 mode for clock and data management while entering and exiting Flash*Freezemode.

For more information and detailed usage of Flash*Freeze modes, refer to the “Microsemi’s Flash*FreezeTechnology and Low Power Modes” chapter of the IGLOO PLUS FPGA Fabric User’s Guide.

Figure 4-2 • Reset Schematic

V3P3

V3P3

PBRESET_N [4]

Mfr P/N :KSC403J 50SH LFGMfr:ITT INDUSTRIES

Mfr P/N :DS1818R-20+T&RMfr: Dallas

RST

C65 0.1uFC65 0.1uF

VCC2

GND3

RST1

U13

DNP

U13

DNP

R63

0

R63

0

12

34

SW7

KSC403J

SW7

KSC403J

R62

10K

R62

10K

C66

0.1

uF

C66

0.1

uF

Figure 4-3 • Flash*Freeze Mode Control

IGLOO PLUSFPGA

Flash*FreezeMode Control

Flash*Freeze Pin

30 Revision 1



Flash*Freeze TypesType 1: Controlled by dedicated Flash*Freeze Pin.

Type 2: Controlled by dedicated Flash*Freeze Pin and Internal Logic.

Flash*Freeze Type 1: Controlled by Dedicated Flash*Freeze PinFlash*Freeze type 1 is intended for systems where either the device is reset upon exiting Flash*Freezemode, or data and clock are managed externally. The device enters Flash*Freeze mode 1 µs after thededicated FF pin is asserted (active low), and returns to normal operation when the FF pin is deasserted(high). In this mode, FF pin assertion or deassertion is the only condition that determines entering orexiting Flash*Freeze mode (Figure 4-4). An INBUF_FF I/O buffer macro must be used to identify theFlash*Freeze input in your design.

Figure 4-4 • Flash*Freeze Mode Type 1 – Controlled by the Flash*Freeze Pin

User Design

IGLOO, IGLOO PLUS, IGLOO nano,ProASIC3L, or RT ProASIC3 Device

Flash*FreezeMode

Enables EnteringFlash*Freeze Mode

Flash*FreezeSignal

Flash*FreezeTechnology

Flash*Freeze (FF) Pin

INBUF_FFFlash*Freeze

Mode Control

AND

To FPGA Core or Floating

1

Figure 4-5 • Flash*Freeze Mode Type 1 – Timing Diagram

NormalOperation

Flash*FreezeMode

NormalOperation

Flash*Freeze Pin

t = 1 µs t = 1 µs

Revision 1 31


Flash*Freeze Type 2: Controlled by Dedicated Flash*Freeze Pin andInternal LogicThe device can be made to enter Flash*Freeze mode by activating the FF pin together with theFlash*Freeze management IP core or user-defined control logic (Figure 4-6) within the FPGA core. Thismethod enables the design to perform important activities before allowing the device to enterFlash*Freeze mode, such as transitioning into a safe state, completing the processing of a critical event.Designers are encouraged to take advantage of the Flash*Freeze Management IP of Microsemi tohandle clean entry and exit of Flash*Freeze mode. The device will only enter Flash*Freeze mode whenthe Flash*Freeze pin is asserted (active low) and the User Low Static ICC (ULSICC) macro input signal,called the LSICC signal, is asserted (high). One condition is not sufficient to enter Flash*Freeze modetype 2; both the FF pin and LSICC signal must be asserted.

Figure 4-7 shows the timing diagram for entering and exiting Flash*Freeze mode type 2. After exitingFlash*Freeze mode type 2 by deasserting the Flash*Freeze pin, the LSICC signal must be deasserted bythe user design. This will prevent entering Flash*Freeze mode by asserting the Flash*Freeze pin only.Refer to Figure 4-1 on page 29 for Flash*Freeze (FF) pin and LSICC signal assertion and deassertionvalues.

Figure 4-6 • Flash*Freeze Mode Type 2 – Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal)

INBUF_FF

Auto-Connected to IP

ULSICC Macro

Flash*FreezeManagement IP

User Design

IGLOO, IGLOO PLUS, IGLOO nano,ProASIC3L, or RT ProASIC3 Device

Flash*FreezeMode

Enables EnteringFlash*Freeze Mode

Flash*FreezeSignal

Flash*FreezeTechnology

Flash*Freeze (FF) Pin

AND

Connect to Top-Level Port

32 Revision 1


IGLOO PLUS I/O State in Flash*Freeze ModeIn IGLOO PLUS devices, users have multiple options in how to configure I/Os during Flash*Freezemode:

1. Hold the previous state.

2. Set I/O pad to weak pull-up or pull-down.

3. Tristate I/O pads.

The I/O configuration must be configured by the user in the I/O Attribute Editor or in a PDC constraint file,and can be done on a pin-by-pin basis. The output hold feature will hold the output in the last registeredstate, using the I/O pad weak pull-up or pull-down resistor when the FF pin is asserted. When inputs areconfigured with the hold feature enabled, the FPGA core side of the input will hold the last valid state ofthe input pad before the device entered Flash*Freeze mode. The input pad can be driven to any value,configured as tristate, or configured with the weak pull-up or pull-down I/O pad feature duringFlash*Freeze mode, without affecting the hold state. If the weak pull-up or pull-down feature is usedwithout the output hold feature, the input and output pads will maintain the configured weak pull-up orpull-down status during Flash*Freeze mode and normal operation. If a fixed weak pull-up or pull-down isdefined on an output buffer or as bidirectional in output mode, and a hold state is also defined for thesame pin, the pin will be configured in hold state mode during Flash*Freeze mode. During normaloperation, the pin will be configured with the predefined weak pull-up or pull-down. Any I/Os that do notuse the hold state or I/O pad weak pull-up or pull-down features will be tristated during Flash*Freezemode and the FPGA core will be driven high by inputs. Inputs that are tristated during Flash*Freezemode may be left floating without any reliability concern or impact to power consumption.

Figure 4-7 • Flash*Freeze Mode Type 1 and Type 2 – Signal Assertion and Deassertion Values

LSICC Signal

NormalOperation

Flash*FreezeMode

NormalOperation

Flash*Freeze Pin

t = 1 µs t = 1 µs

Table 4-1 • Flash*Freeze Mode Type 1 and Type 2 – Signal Assertion and Deassertion Values

Signal Assertion Value Deassertion Value

Flash*Freeze (FF) pin Low High

LSICC signal High Low

Note:

1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal.

2. The LSICC signal is used only in Flash*Freeze mode type 2.

Revision 1 33


Table 4-2 shows the I/O pad state based on the configuration and buffer type.

Table 4-2 • IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)—I/O Pad State

Buffer Type Hold StateI/O Pad

Weak Pull-Up/-DownI/O Pad State in Flash*Freeze

Mode

Input Enabled Enabled Weak pull-up/pull-down 1

Disabled Enabled Weak pull-up/pull-down 2

Enabled Disabled Tristate 1

Disabled Disabled Tristate 2

Output Enabled “Don't care” Weak pull to hold state

Disabled Enabled Weak pull-up/pull-down

Disabled Disabled Tristate

Bidirectional /Tristate Buffer

E = 0(input/tristate)

Enabled Enabled Weak pull-up/pull-down 1

Disabled Enabled Weak pull-up/pull-down 2

Enabled Disabled Tristate 1

Disabled Disabled Tristate 2

E = 1 (output) Enabled “Don't care” Weak pull to hold state 3

Disabled Enabled Weak pull-up/pull-down

Disabled Disabled Tristate

Note:1) Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode.2) Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode.3) For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state.

34 Revision 1


Flash*Freeze SwitchAn F*F switch is provided on the board for designs that utilize the Flash*Freeze technology. Setting theF*F switch to FF_ON will enable the Flash*Freeze mode of the IGLOO PLUS device. Since the SchmittTrigger chip (U12) is NOT populated on-board for the F*F switch, the Schmitt Trigger feature should beenabled in the FPGA design for the Flash*Freeze input to enhance noise immunity (Figure 4-8). TheSchmitt Trigger is an advanced I/O feature of the IGLOO PLUS FPGA family. If the IGLOO PLUS FPGAis swapped out with a device that does not have the advanced Schmitt Trigger I/O feature, the SchmittTrigger chip (U12) should be populated.

Some features on this board are included to demonstrate the Flash*Freeze variants of the IGLOO PLUSFPGA. I/Os can be individually configured to either hold their previous state or be tristated duringFlash*Freeze mode. Alternatively, they can be set to a certain state (high or low) using weak pull-up orpull-down I/O attribute configurations. These Flash*Freeze variants can be demonstrated by configuringthe I/Os in Designer and using switches as inputs to control the FET LEDs. Refer to the demo design,which provides additional details on demonstrating these Flash*Freeze variants ("IGLOO PLUS BoardDemo" on page 51).

Flash*Freeze Variant Dip SwitchTwo regular DIP switches are located on the board, next to the FET LEDs (Figure 4-9). The DIP switchescan be programmed to help debug or demonstrate the Flash*Freeze variants. Refer to the demo designthat demonstrates the Flash*Freeze variants with these switches.

Figure 4-8 • Flash*Freeze Schematic, Schmitt Triggered

V3P3

V3P3

IGLOO_FF [4]

Mfr P/N :AYZ0102AGRLMfr: ITT INDUSTRIES R61

10KR6110K

2

1

3

SW8

AYZ0102AGRL

SW8

AYZ0102AGRL+

C64

10uF

+

C64

10uF

C63

0.1

uF

C63

0.1

uF

R52

0

R52

0

C61

0.1

uF

C61

0.1

uF

NC1

A2

GND3

VCC5

Y4

U12

DNP

Mfg P/N = SN74AUP1G17DCKRManufacturer = TI

U12

DNP

Mfg P/N = SN74AUP1G17DCKRManufacturer = TI

+

C62

2.2

uF

+

C62

2.2

uF

Figure 4-9 • Two I/Os Controlled through DIP Switch Toggling High or Low

3V3_SWITCH2[4]

3V3_SWITCH1[4]

3V3_SWITCH1[4]

3V3_SWITCH2[4]R22 10KR22 10K

D1

1L

O T

67

K-L

1M

2-2

4-Z

_D

NL

D1

1L

O T

67

K-L

1M

2-2

4-Z

_D

NL

R21

DNL

R21

DNL

R20 10KR20 10K

R19

DNL

R19

DNL

1

2

3

4

SW5

76SB02ST

SW5

76SB02ST

D1

2L

O T

67

K-L

1M

2-2

4-Z

_D

NL

D1

2L

O T

67

K-L

1M

2-2

4-Z

_D

NL

Revision 1 35


Flash*Freeze Variant FET LEDsThese FET LEDs can be used for debugging, such as for viewing the state of I/Os in Flash*Freeze mode.These LEDs can be activated (ON) before entering Flash*Freeze mode, and have the ability to remainactivated (ON) in Flash*Freeze mode. In low-power or Flash*Freeze mode, the FET LEDs can continueto function normally. There is one N-Type FET LED and two P-Type FET LEDs on the board(Figure 4-10). Refer to "Demo 4 – Flash*Freeze Variant: Configuration Settings of Demo Design" onpage 52, which will help demonstrate the Flash*Freeze variants.

Figure 4-10 • FET LEDs for Debugging

V3P3

V3P3 V3P3

FET_N[4]

FET_P1 [4] FET_P2 [4]

P TYPE FET

N TYPE FET

D1

3L

O T

67

K-L

1M

2-2

4-Z

D1

3L

O T

67

K-L

1M

2-2

4-Z

1

2 3

G

S

D

Q6

MOSFET_PTYPEMfg P/N = FDV304PManufacturer = FairChild

G

S

D

Q6


R50

1.5K

R50

1.5K

D1

5L

O T

67

K-L

1M

2-2

4-Z

D1

5L

O T

67

K-L

1M

2-2

4-Z

R49

1.5K

R49

1.5K

1

2 3

G

S

D

Q4


G

S

D

Q4


1

2 3

GSD

Q5

MOSFET_NTYPEMfg P/N = FDV301NManufacturer = FairChild

GSD

Q5

MOSFET_NTYPEMfg P/N = FDV301NManufacturer = FairChild

R51

1.5K

R51

1.5K

D1

4L

O T

67

K-L

1M

2-2

4-Z

D1

4L

O T

67

K-L

1M

2-2

4-Z

36 Revision 1


Push-Button SwitchesFour active low push-button switches are provided on the board for debug purposes. You can remove thecorresponding jumpers to detach or isolate any of the four push-button test switches from the FPGA I/O.Schematics are shown in Figure 4-11 and Figure 4-12.

Figure 4-11 • Push-Button Switches Schematic

V3P3

SWITCH1 [4] SWITCH2 [4]

SWITCH1 [4]

SWITCH2 [4]

SWITCH3 [4] SWITCH4 [4]

SWITCH3 [4]

SWITCH4 [4]





R32 10KR32 10K

1 2

3 4

SW1

KSC403J

SW1

KSC403J

R33 10KR33 10K

1 2

3 4

SW4

KSC403J

SW4

KSC403J

1 2

3 4

SW3

KSC403J

SW3

KSC403J

1 2

3 4

SW2

KSC403J

SW2

KSC403J

R34 10KR34 10K

R23 10KR23 10K

Figure 4-12 • Jumper Header Schematic for Push-Button Switches

3V3_SWITCH1 [8]

SWITCH4 [6]

SWITCH3 [6]

SWITCH2 [6]

SWITCH1 [6]

1 2

J23HDR1X2

J23HDR1X2

1 2

J36HDR1X2

J36HDR1X2

1 2

J37HDR1X2

J37HDR1X2

1 2

J39HDR1X2

J39HDR1X2

1 2

J38HDR1X2

J38HDR1X2

Revision 1 37


.DIP SwitchesA DIP switch pack (8 switches) is provided on the board (Figure 4-13 and Figure 4-14). You can removethe corresponding jumpers to detach or isolate any of the eight DIP Switches from the FPGA I/Os..

Figure 4-13 • DIP Switches Schematic

V3P3

D_SWITCH1 [4]

D_SWITCH2 [4]

D_SWITCH3 [4]

D_SWITCH4 [4]

D_SWITCH5 [4]

D_SWITCH6 [4]

D_SWITCH7 [4]

D_SWITCH8 [4]

D_SWITCH1 [4]

D_SWITCH2 [4]

D_SWITCH3 [4]

D_SWITCH4 [4]

D_SWITCH5 [4]

D_SWITCH6 [4]

D_SWITCH7 [4]

D_SWITCH8 [4]

R54 4.7KR54 4.7K

R56 4.7KR56 4.7K

R53 4.7KR53 4.7K

R57 4.7KR57 4.7K

R55 4.7KR55 4.7K

R60 4.7KR60 4.7K

R58 4.7KR58 4.7K

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DSW5

DIP_SWITCH

Manufacturer = GRAYHILL IncMfg P/N = 76SB08ST

DSW5

DIP_SWITCH

Manufacturer = GRAYHILL IncMfg P/N = 76SB08ST

R59 4.7KR59 4.7K

Figure 4-14 • Jumper Header Schematic for DIP Switches

D_SWITCH1 [6]

D_SWITCH8 [6]

D_SWITCH7 [6]

D_SWITCH6 [6]

D_SWITCH5 [6]

D_SWITCH4 [6]

D_SWITCH3 [6]

D_SWITCH2 [6]

12

J34HDR1X2

J34HDR1X2

12

J31HDR1X2

J31HDR1X2

12

J30HDR1X2

J30HDR1X2

12

J29HDR1X2

J29HDR1X2

12

J33HDR1X2

J33HDR1X2

12

J28HDR1X2

J28HDR1X2

12

J32HDR1X2

J32HDR1X2

12

J35HDR1X2

J35HDR1X2

38 Revision 1


User LEDsEight active low debug LEDs are provided on the board (Figure 4-15 and Figure 4-16). You can removethe corresponding jumpers from the 8 × 2 headers to detach or isolate any of the eight LEDs from theFPGA I/Os.

Figure 4-15 • User LEDs Schematic

V3P3

V3P3

LED1[4]

LED2[4]

LED3[4]

LED4[4]

LED8[4]

LED5[4]

LED6[4]

LED7[4]

Mfr P/N :LO T67K-L1M2-24-ZMfr: Osram Opto Semiconductors Inc

D8

LO T67K-L1M2-24-Z

D8

LO T67K-L1M2-24-Z

D5

LO T67K-L1M2-24-Z

D5

LO T67K-L1M2-24-Z

D4

LO T67K-L1M2-24-Z

D4

LO T67K-L1M2-24-Z

R29

1.5K

R29

1.5K

D7

LO T67K-L1M2-24-Z

D7

LO T67K-L1M2-24-Z

R31

1.5K

R31

1.5K

R30

1.5K

R30

1.5K

D6

LO T67K-L1M2-24-Z

D6

LO T67K-L1M2-24-Z

R27

1.5K

R27

1.5K

R28

1.5K

R28

1.5K

R25

1.5K

R25

1.5K

R24

1.5K

R24

1.5K

R26

1.5K

R26

1.5K

D1

LO T67K-L1M2-24-Z

D1

LO T67K-L1M2-24-Z

D3

LO T67K-L1M2-24-Z

D3

LO T67K-L1M2-24-Z

D2

LO T67K-L1M2-24-Z

D2

LO T67K-L1M2-24-Z

Figure 4-16 • Jumper Header Schematic for User LEDs

D_SWITCH1 [6]

D_SWITCH8 [6]

D_SWITCH7 [6]

D_SWITCH6 [6]

D_SWITCH5 [6]

D_SWITCH4 [6]

D_SWITCH3 [6]

D_SWITCH2 [6]

12

J34HDR1X2

J34HDR1X2

12

J31HDR1X2

J31HDR1X2

12

J30HDR1X2

J30HDR1X2

12

J29HDR1X2

J29HDR1X2

12

J33HDR1X2

J33HDR1X2

12

J28HDR1X2

J28HDR1X2

12

J32HDR1X2

J32HDR1X2

12

J35HDR1X2

J35HDR1X2

Revision 1 39


I/O Test PinsAll IGLOO PLUS FPGA I/Os are available on headers located on the top and bottom of the device(Figure 4-17 and Figure 4-18). These test pins are multiples of 100 mils apart, so developers can easilyattach headers and place an extension card on top with an off-the-shelf breadboard for a low-costsolution for integration. In order to use I/Os assigned to the LEDs, DIP Switches, and push-buttonswitches, the 2-pin jumper on their path must be removed first to disconnect the assignment.

Figure 4-17 • I/O Test Pins

GND

GND

IGLOO PLUS

IO_B0

IO_B1

IO_B2

IO_B3

100 mils × N(N = 1, 2, 3, 4, ...)

Figure 4-18 • I/O Test Pins Schematic

TP272TP

TP272TP

TP57TP

TP57TP

TP263TP

TP263TP

TP194TP

TP194TP

TP306TP

TP306TP

TP313TP

TP313TP

TP51TP

TP51TP

TP257TP

TP257TP

TP324TP

TP324TP

TP188TP

TP188TP

TP300TP

TP300TP

TP283TP

TP283TP

TP318TP

TP318TP

TP294TP

TP294TP

TP277TP

TP277TP

TP62TP

TP62TP

TP268TP

TP268TP

TP327TP

TP327TP

TP251TP

TP251TP

TP199TP

TP199TP

TP291TP

TP291TP

TP328TP

TP328TP

TP271TP

TP271TP

TP56TP

TP56TP

TP262TP

TP262TP

TP250TP

TP250TP

TP193TP

TP193TP

TP305TP

TP305TP

TP312TP

TP312TP

TP67TP

TP67TP

TP256TP

TP256TP

TP323TP

TP323TP

TP187TP

TP187TP

TP299TP

TP299TP

TP282TP

TP282TP

TP198TP

TP198TP

TP317TP

TP317TP

TP293TP

TP293TP

TP276TP

TP276TP

TP61TP

TP61TP

TP267TP

TP267TPTP304

TPTP304

TP

TP311TP

TP311TP

TP270TP

TP270TP

TP55TP

TP55TP

TP261TP

TP261TP

TP280TP

TP280TP

TP192TP

TP192TP

TP281TP

TP281TP

TP66TP

TP66TP

TP63TP

TP63TP

TP255TP

TP255TP

TP322TP

TP322TP

TP186TP

TP186TP

TP298TP

TP298TP

TP197TP

TP197TP

TP316TP

TP316TP

TP292TP

TP292TP

TP275TP

TP275TP

TP60TP

TP60TP

TP266TP

TP266TP

TP191TP

TP191TP

TP303TP

TP303TP

TP310TP

TP310TP

TP286TP

TP286TP

TP54TP

TP54TP

TP260TP

TP260TP

TP279TP

TP279TP

TP297TP

TP297TP

TP65TP

TP65TP

TP254TP

TP254TP

TP321TP

TP321TP

TP307TP

TP307TP

TP185TP

TP185TP

TP59TP

TP59TP

TP265TP

TP265TP

TP196TP

TP196TP

TP315TP

TP315TP

TP274TP

TP274TP

TP326TP

TP326TP

TP190TP

TP190TP

TP302TP

TP302TP

TP309TP

TP309TP

TP285TP

TP285TP

TP53TP

TP53TP

TP259TP

TP259TP

TP184TP

TP184TP

TP296TP

TP296TP

TP64TP

TP64TP

TP202TP

TP202TP

TP253TP

TP253TP

TP320TP

TP320TP

TP165TP

TP165TP

TP273TP

TP273TP

TP58TP

TP58TP

TP264TP

TP264TP

TP195TP

TP195TP

TP314TP

TP314TP

TP258TP

TP258TP

TP325TP

TP325TP

TP189TP

TP189TP

TP301TP

TP301TP

TP290TP

TP290TP

TP308TP

TP308TP

TP284TP

TP284TP

TP52TP

TP52TP

TP295TP

TP295TP

TP278TP

TP278TP

TP200TP

TP200TP

TP269TP

TP269TP

TP201TP

TP201TP

TP252TP

TP252TP

TP319TP

TP319TP

V3P3

2V51V5_1V2

TP13TP

TP13TP

TP1TP

TP1TP

TP12TP

TP12TP

TP3TP

TP3TP

TP11TP

TP11TP

TP8TP

TP8TP

TP5TP

TP5TP

TP6TP

TP6TP

TP9TP

TP9TP

40 Revision 1


OLEDA 96 × 16 pixel low-power blue organic light emitting diode (OLED) is available on the board above theIGLOO PLUS FPGA (Figure 4-19). The OLED features a serial I2C interface, and is capable ofdisplaying sharp images or text. The demo design included in this kit contains a roulette game that usesthe OLED for display and the push-button switch for game control.

Additional OLED info is available at the IGLOO PLUS Starter Kit website page:www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.

Figure 4-19 • OLED Display Schematic

VP_10V

V3P3

V3P3

PACER_D0 [4]

PACER_RES# [4]

PACER_D2 [4]

SCL

SDA

Mfr P/N :PMO13701Mfr: PACER

VCC30

VCOMH29

IREF28

VDD11

BS112

BS213

NC11

NC28

NC39

NC410

NC514

NC631

VSS2

D727

D626

D525

D424

D323

D222

D121

D020

TEST53

TEST44

TEST35

TEST26

TEST17

RD#19

WR#18

D/C#17

RES#16

CS#15

U3

PMO13701

U3

PMO13701

C200.01uFC200.01uF

R3610KR3610K

+C21

4.7uF 16V

+C21

4.7uF 16VR372MR372M

C19

1uF

C19

1uF

R35

10K

R35

10K

Revision 1 41



Interface ConnectorA standard interface connector on the board can be used to connect additional daughter cards, some ofwhich are developed by partners and third party vendors (Figure 4-20). The interface possibilities arenumerous, such as flash and SRAM memory interfaces, keyboard interfaces for embedded applications,LCD interfaces, and motor control interfaces. GPIOA_1, GPIOA_2, GPIOA_4, and GPIOA_31 pins canbe used for critical signals, such as clock and reset, because proper series termination has beenprovided on these signal lines.

USB-to-UART InterfaceIncluded on the starter kit board is a USB-to-UART interface with ESD protection. This interface includesan integrated USB-to-UART bridge controller to provide a standard UART connection with the IGLOOPLUS FPGA. Any standard UART controller can be implemented in the IGLOO PLUS FPGA to allowaccess with this interface. In addition, the Microsemi IP catalog includes various UART controllers,specifically CoreUART, which can be instantiated in the FPGA design with an embedded processor.CoreUART controller supports both asynchronous and synchronous modes with configurableparameters for various applications.

One application of the USB-to-UART interface is to allow for Hyper-terminal on a PC to communicatewith the IGLOO PLUS FPGA. HyperTerminal is a serial communications application program that can beinstalled in the Windows® operating system. A basic HyperTerminal program is usually distributed withWindows. With an USB driver properly installed, and correct COM port and communication settingsselected, you can use the HyperTerminal program to communicate with a design running in the IGLOOPLUS FPGA device.

Information on the USB-to-UART bridge datasheet and device drivers are available at the IGLOO PLUSStarter Kit website page:www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.

Figure 4-20 • Interface Connector Schematic

VUSB V3P3

GPIOA_29{3}

GPIOA_33{3}GPIOA_31{3}

GPIOA_35{3}GPIOA_34 {3}GPIOA_36 {3}

GPIOA_26 {3}GPIOA_28 {3}GPIOA_30 {3}GPIOA_32 {3}

GPIOA_10 {3}GPIOA_8 {3}GPIOA_6 {3}

GPIOA_12 {3}

GPIOA_16 {3}GPIOA_18 {3}GPIOA_20 {3}

GPIOA_24 {3}GPIOA_22 {3}

GPIOA_2 {3}GPIOA_4 {3}

GPIOA_9{3}

GPIOA_13{3}GPIOA_15{3}GPIOA_17{3}GPIOA_19{3}GPIOA_21{3}GPIOA_23{3}




20x2 Edge Fingers

Pin No:15 & 16 Should be NC For Matting Connector Polarised Pins

Matting Conn P/N: MEC1-120-02-F-S-EM2Mfr : Samtec

2468101214

1820

2422

262830323436384039

3735333129272523211917

1311

97531

J48

HDR_20x2

J48

HDR_20x2

42 Revision 1



The USB-to-UART schematic is shown in Figure 4-21.

SPI FlashOne 2 Mbyte SPI flash is available on the board and can be used by CoreABC-type applications foraccess of additional memory. The flash interface, serial peripheral interface bus (SPI), is a synchronousserial data link standard that is used to access the flash memory. Some advantages of the SPI interfaceare full duplex communication and higher throughput than I2C. In the schematics shown in Figure 4-22,either the Winbond or Atmel 2 Mbyte SPI flash will be populated on-board.

Winbond and Atmel SPI flash datasheets are available at the IGLOO PLUS Starter Kit website page:www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx.

Note: Either the Winbond or Atmel SPI flash will be populated on the board.

Figure 4-21 • USB-to-UART Interface Schematic

V3P3

5V_USBVUSB

AGL_UART_RXD [4]AGL_UART_TXD [4]

Mfr P/N :UX60-MB-5STMfr: Hirose

Mfr P/N :USBLC6-2SC6Mfr: ST Micro.

Mfr P/N :CP2102-GMMfr: Silicon Labs

Mfr P/N :MICROSMD050F-2Mfr:Tyco

Mfr P/N :BLM31PG500SN1LMfr: Murata

R67

0

R67

0

C1

0.1uF

C1

0.1uF

R110KR110K

FB1

FERRITE BEAD

FB1

FERRITE BEAD

C2

1uF

C2

1uF

VBUS8

REGIN7

VDD6

NC110

NC213

NC314

NC415

NC516

NC617

D-5

D+4

GN

D3

GN

DN

W3

0

GN

DC

NT

R2

9

RST9

NSUSPEND11

SUSPEND12

NC718

NC819

NC920

NC1021

NC1122

DTR28

RTS24

CTS23

DSR27

RI2

TXD26

RXD25

DCD1

U2

CP2102

U2

CP2102

R2147R2147

PTC1

FUSE

PTC1

FUSE

C180.1uFC180.1uF

D9

LED_GREEN

D9

LED_GREEN

12

JP1

CON2

JP1

CON2

IO1A1

G2

IO2A3

IO2B4

V5

IO1B6

U1

USBLC6-2

U1

USBLC6-2

VBUS1

D-2

D+3

NC4

GND5

GND16

GND27

GND38

GND49

J5

USB_MINI_RECEP

J5

USB_MINI_RECEP

Figure 4-22 • SPI Flash Schematics

V3P3

V3P3

SPI_DIO[4]SPI_DO[4]SPI_CLK[4]SPI_CS_N[4]SPI_WP_N[4]SPI_HOLD_N[4]

SPI_DIO[4]SPI_DO[4]SPI_CLK[4]SPI_CS_N[4]SPI_WP_N[4]SPI_HOLD_N[4]

2 MByte

Mfr P/N : W25X16-VSSIGMfr: Winbond

C67

0.1uF 10V

C67

0.1uF 10V

HOLD7

Vcc8

CS1

DIO5

WP3

GND4

DO2

CLK6

SPI FLASH

16M bit

U11

W25X16

SPI FLASH

U11

W25X16

SI1

SO8

SCK2

CS4

WP5

RESET3

VCC6

GND7

SPI FLASH16M BIT

U23

Manufacturer = AtmelMANUFACTURER P/N = AT45BD161D-SU

SPI FLASH16M BIT

U23

AT45DB161D-SU

Manufacturer = AtmelMANUFACTURER P/N = AT45BD161D-SU

R474.87K

R474.87K

C50

0.1uF 10V

C50

0.1uF 10V

Revision 1 43



Low-Cost Programming Stick (LCPS)

InterfaceThe development board can be programmed by the low-cost programming stick (LCPS) or via a 10-pinFP3 header (Figure 4-24). Regardless of the programming dongle used, IGLOO PLUS is programmedthe same way as IGLOO nano, ProASIC3, and Fusion FPGA devices.The LCPS is a special version forthe FlashPro3 programming circuitry that is compatible with FlashPro3 and the generic FlashProprogramming software. The LCPS, like the IGLOO PLUS board, is RoHS-compliant and is completelylead (Pb) free. To use the LCPS with the FlashPro software, all you need to do is to select the FlashPro3from the list of programmer types. The LCPS behaves exactly as if it were a regular encased FlashPro3programmer, except regarding VPUMP. The LCPS does not supply VPUMP; it must be supplied by theIGLOO PLUS board. The 12-pin female connector socket is designed to interface to the 12-pin right-angle male header on the IGLOO PLUS kit. One of the pins is a special VJTAGENB signal that goes highwhen programming is taking place and returns to a low level when programming has completed. Thissignal is connected to the FET on the 1.5 V regulator circuit. The IGLOO PLUS board uses this signal toeffect a change in the value of VCC from 1.2 V to 1.5 V, which is required for programming all IGLOOPLUS devices.

You do not need to have the LCPS connected to the IGLOO PLUS board to operate it, after the FPGAhas been programmed. The LCPS must be connected to the IGLOO PLUS board only whenprogramming the AGLP125-CSG289.

Note:

1. The LCPS supplied with this kit is intended for use with the IGLOO PLUS Starter Kit. An LCPSsupplied for other kits, although electrically and functionally equivalent, may not connectseamlessly with the IGLOO PLUS Starter Kit board.

2. The LCPS is not designed to supply VPUMP on its own as does the FlashPro3/4 programmer, sothe IGLOO PLUS board must supply VPUMP. Use a 5 V brick or USB port to power-up the board.If you disconnect the VPUMP jumper, the LCPS will not work.

Figure 4-23 • Low-Cost Programming Stick (LCPS)

44 Revision 1


Figure 4-24 • FPGA Programming Headers Schematic

VJTAGENB[3] TCK [5]

VPUMP [5]

TRST [5]

TDI [5]

TMS[5]

VJTAG[5]

TDO[5]

Programmer

Mfr P/N :TSW-106-08-T-D-RAMfr: SAMTEC

6X2 Right Angled Header

TCK2

GND34

TDI6

TRSTB8

VPUMP10

VJTAGENB1

TMS3

GND25

VJTAG7

TDO9

GND411

GND512

J3

HEADER 6x2/SM

J3

HEADER 6x2/SM

Revision 1 45


LCPS StackupThe LCPS is built on a four-layer PCB with the layers arranged in the following stackup:

1. Top signal layer (Figure 4-25)

2. Ground plane

3. Power plane

1. Bottom signal layer (Figure 4-26 on page 47)

Figure 4-25 • Low-Cost Programming Stick – Top Silkscreen

46 Revision 1


Figure 4-26 • Low-Cost Programming Stick – Bottom Silkscreen

Revision 1 47

5 – Programming

Program a Design into the IGLOO PLUS Evaluation Board1. To program a design into the IGLOO PLUS evaluation board, attach the LCPS board to the

IGLOO PLUS evaluation board.

2. Attach a USB cable to the LCPS. This allows a programming data file, in programming databaseformat (*.pdb) or STAPL format (*.stp), to be downloaded via the FlashPro software to the IGLOOPLUS device fitted to the board.

3. A separate USB connection is required for the IGLOO PLUS Board if no other power source(power brick) is attached to the IGLOO PLUS board.

4. When using the FlashPro software, the programmer to select is the FlashPro3. The LCPS isfunctionally equivalent to a FlashPro programmer but designed specifically for use with theIGLOO PLUS Starter Kit.

5. Alternatively, an option (10-pin FP3 header) is provided to program the FPGA with a FlashPro3instead (Figure 5-1).

Figure 5-1 • Schematic of JTAG header for Programming Directly with a FlashPro3

VJTAG [5]VPUMP[5]

TMS[5]

TDI[5]TRST [5]

TCK[5]TDO[5]

TCK[5] TRST [5]

Mfr P/N :15-91-2100Mfr: Molex

R381KR381K

1357 8

642

9 10

J4

HDR_5x2_DNLDNL

J4

HDR_5x2_DNLDNL

R391KR391K

R66

0

R66

0

Revision 1 49

6 – IGLOO PLUS Board Demo

The IGLOO PLUS FPGA is pre-programmed with a simple demo to quickly get you started. This demodesign will provide a quick overview as well as a quick check of this board.

Demos Included in the Starter KitThere are a few demos included in this starter kit, such as a binary counter to light up the 8 user LEDs.These 8 LEDs retain their count value in Flash*Freeze mode and restart counting from that value afterexiting Flash*Freeze mode. During Flash*Freeze mode, the active LEDs will be weakly ON, since theyare driven by the weak hold state resistors. Flash*Freeze variants can be demonstrated using the F*Fswitches and FET LEDs.

The IGLOO PLUS demo design RTL and design files are available at the IGLOO PLUS Starter Kitwebsite page: www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. Referto the Quick Start Guide available on the website to run the demo.

Powering Up the Board1. Before running the demos, refer to Table 1-1 on page 11 to check the default jumper and board

settings.

2. The board is powered from the USB connection and no external power supply is required.

– A 5 V wall-jack connector could be used when USB cable is not available.

– The board does not switch seamlessly between the power brick and USB, so the powersource 4-pin header and jumper must be used to select the desired power source.

3. Once the USB cable is attached securely, verify the green LED next to the USB jack is ON.

Getting Started with the IGLOO PLUS Starter Kit Demo Design

Demo 1 – IGLOO PLUS Counter1. Before starting Demo 1, check the jumper settings and set all switches to the OFF or CLOSE

position. Ensure the F*F switch is in the OFF position.

2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in thestarter kit.

3. Press and release System Reset to reset the IGLOO PLUS FPGA.

4. Observe that LED D1 is ON during Reset.

5. The LEDs D[3:8] represent a binary counter which counts up from 000000 to 111111 and loopsback. After reset, LEDs D[3:8] should restart counting from zero.

Table 6-1 • LED[8:1]

LED Description

LED D1 On during reset

LED D2 On when any push-button is pressed or DIP switch is in the open position

LED D3 Binary Counter[5]



Revision 1 51


IGLOO PLUS Board Demo

Demo 2 – OLED Interface DemonstrationThis demo includes a simple Roulette game provided by Avnet Memec that demonstrates control andoperation of the OLED display.

1. Press SW1 to begin a bet and press SW1 again to stop at the number you want to bet on.

2. Once you have selected your number, press SW2 to spin. Your results will display in the OLED.

3. Continue with steps 1 and 2 to bet and play again.

Demo 3 – Simple Flash*Freeze DemonstrationThis demo demonstrates the IGLOO PLUS FPGA’s ability to save power while holding internal logic stateduring Flash*Freeze mode.

1. Enter Flash*Freeze mode by switching the F*F switch to ON.

– In Flash*Freeze mode, observe the LEDs D[1:8] retain the last state they were driven to whenFlash*Freeze mode was asserted. They may be weakly ON, since they are driven by theweak hold state resistors.

– The OLED will remain on, since it is self-powered.

– See Demo 4 below for the settings and states of LEDs D[13:15] during Flash*Freeze mode.

2. Exit Flash*Freeze mode by switching the F*F switch to OFF.

– After exiting Flash*Freeze mode, LEDs D[3:8] resume counting from the count value prior toentering Flash*Freeze mode.

3. To measure power of the FPGA core during and after Flash*Freeze mode, simply remove jumperJ12 and use a multimeter capable of reading µA current across J12.

Demo 4 – Flash*Freeze Variant: Configuration Settings of Demo DesignOne feature of the IGLOO PLUS FPGA family is the ability to hold input and output states duringFlash*Freeze mode. This demonstration will showcase this feature by displaying the result of variousinput and output hold configurations.

In this portion of the design, two inputs named FET Switch 1 and FET Switch 2 are used to drive differentlogic values into the FPGA. FET Switch 1 directly drives FET LED D13 and FET Switch 2 directly drivesFET LED D14 and FET LED D15. FET switches are used on this board to provide the required current todrive the LEDs when the FPGA is in Flash*Freeze mode. FETs are not required to enter Flash*Freezemode or to take advantage of the I/O hold state feature. The FPGA configurations of the inputs andoutputs of this circuit are described in Table 6-2 and Table 6-3 on page 53.




Table 6-1 • LED[8:1] (continued)

LED Description

Table 6-2 • FET Input Configuration in Demo Design

Name I/O Hold Internal Weak Resister Pull Description

FET Switch 1 Enabled Down Drives FET LED D13 directly

FET Switch 2 Disabled Down Drives FET LED D14 and D15 directly

52 Revision 1


When HOLD is disabled at the output buffer, the output will depend on the resister pull-up or pull-downdirection in Flash*Freeze mode. If HOLD is enabled at the output buffer, then the output will depend onthe state right before entering Flash*Freeze mode.

1. Similar to Demo 1, before starting Demo 4, check the jumper settings and set all switches to theOFF or CLOSED position. Ensure the F*F switch is in the OFF position.

2. Power-on the IGLOO PLUS Starter Kit board using the power supply or USB cable included in thestarter kit.

3. Press and release the System Reset button (SW7) to reset the IGLOO PLUS FPGA.

– Observe that LED D1 is ON during Reset.

4. Example A: Set both FET Switches [2:1] to the CLOSE position.

– Based on the logic in this demo design, both P-Type FET LEDs D13 and D14 should be ONand N-Type FET LED D15 should be OFF. Refer to the board schematic for reference on theFET LED connections.

– Enable Flash*Freeze mode by setting the F*F Switch to ON.

After entering Flash*Freeze mode, observe that P-Type FET LED D13 stays ON because theHOLD state for this output configuration was enabled.

Also observe that P-Type FET LED D14 is ON due to the pull-down resister configuration.

N-Type FET LED D15 turns ON due to the pull-up resister configuration.

Toggle the FET Switches back and forth.

Observe that the LEDs are unaffected, because the device is in Flash*Freeze mode. Theinputs are not able to pass data into the device.

Return the FET Switches [2:1] back to the CLOSE position

– Disable Flash*Freeze mode by setting the F*F Switch to OFF.

After exiting the Flash*Freeze mode, observe that N-Type FET LED D15 turns OFF.

5. Example B: Set both FET Switches [2:1] to the OPEN position

– Based on the logic in this demo design, both P-type FET LEDs D13 and D14 should be OFFand N-type FET LED D15 should be ON.

– Enable Flash*Freeze mode by setting the F*F Switch to ON.

After entering Flash*Freeze mode, observe that P-Type FET LED D13 remains OFF becausethe HOLD state for this output configuration was enabled.

Also observe that P-Type FET LED D14 turns ON due to the pull-down resister configuration.

N-Type FET LED D15 is ON due to the pull-up resister configuration.

– Disable Flash*Freeze mode by setting the F*F to OFF.

After exiting the Flash*Freeze mode, observe that P-Type FET LED D14 turns OFF.

Table 6-3 • FET Output Configuration in Demo Design

FET LED I/O HoldInternal Weak Resister

Pull Description

FET LED D13 Enabled Down P-Type

FET LED D14 Disabled Down P-Type

FET LED D15 Disabled Up N-Type

Revision 1 53

IGLOO PLUS Board Demo

The FET Truth Table (Table 6-4) shows the Flash*Freeze variants based on the FET I/O HOLD andresister pull configured for this demo design. For the output FET LEDs, NORMAL represents the LEDstate before entering and after exiting Flash*Freeze mode, while F*F Mode represents the LED stateduring Flash*Freeze mode.

Table 6-4 • FET Truth Table

Input Output

FET Switch 1

FET Switch 2

P-Type FET LED D13 (active low): HOLD

P-Type FET LED D14 (active low): Pull-down

N-Type FET LED D15 (active high): Pull-up

NORMAL F*F Mode Normal F*F Mode Normal F*F Mode

CLOSE (0) CLOSE (0) ON (0) ON (0) ON (0) ON (0) OFF (0) ON (1)

CLOSE (0) OPEN (1) ON (0) ON (0) OFF (1) ON (0) ON (1) ON (1)

OPEN (1) CLOSE (0) OFF (1) OFF (1) ON (0) ON (0) OFF (0) ON (1)

OPEN (1) OPEN (1) OFF (1) OFF (1) OFF (1) ON (0) ON (1) ON (1)

54 Revision 1

A – Resources

IGLOO PLUS Starter Kit

www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx

IGLOO PLUS Overview

www.microsemi.com/soc/products/iglooplus/default.aspx

IGLOO PLUS Datasheet

www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf

IGLOO PLUS FPGA Fabric User’s Guide

www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf

Libero IDE Design Software

www.microsemi.com/soc/products/software/libero/default.aspx

Revision 1 55

http://www.actel.com/products/iglooplus/default.aspx



http://www.actel.com/products/software/libero/default.aspx

http://www.actel.com/products/iglooplus/default.aspx



http://www.actel.com/products/software/libero/default.aspx



B – List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Date Changes Page

Revision 1(February, 2013)

Added note in "Low-Cost Programming Stick (LCPS)" section. (SAR 22976) 44

Note: *The part number is located on the last page of the document. The digits following the slash indicate the month and year of publication.

Revision 1 57

C – Product Support

Microsemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.

Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.

From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913

Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.

Technical SupportVisit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website.

WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc.

Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.

EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.

The technical support email address is [email protected].

Revision 1 59

http://www.microsemi.com/soc/support/search/default.aspx

http://www.microsemi.com/soc

mailto:[email protected]

Product Support

My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases.

Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email([email protected]) or contact a local sales office. Sales office listings can be found atwww.microsemi.com/soc/company/contact/default.aspx.

ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.

60 Revision 1

http://www.microsemi.com/soc/mycases/



http://www.microsemi.com/soc/company/contact/default.aspx

http://www.microsemi.com/soc/company/contact/default.aspx

http://www.microsemi.com/soc/company/contact/default.aspx#itartechsupport



http://www.microsemi.com/soc/ITAR/

Revis ion 1 61

BBank 0 I/O Signals for AGLP125-CSG289 17, 18, 19,

20, 21board

description 7stackup 8

board stackup 57

Ccontacting Microsemi SoC Products Group

customer service 59email 59web-based technical support 59

contents 5current measurement 26customer service 59

Ddemo

Flash*Freeze variantconfiguration settings of demo design 52

IGLOO PLUS counter 51OLED interface 52simple Flash*Freeze demonstration 52

DIP switches 38

FFlash*Freeze mode

control 30switch 35

Hhardware

components 7

II/O test pins 40Introduction 5

Jjumper settings 11jumpers

settings 11

LLCPS 44

stackup 46LEDs 39low-cost programming stick (LCPS) 44

MMicrosemi SoC Products Group

email 59web-based technical support 59website 59

Pproduct support 59–??

customer service 59email 59My Cases 60outside the U.S. 60technical support 59website 59

push-button switches 37

Rresources 55

Sswitches

DIP 38push-button 37settings 11

Ttech support

ITAR 60My Cases 60outside the U.S. 60

technical support 59

UUSB-to-UART

interface 42User LEDs 39

Wweb-based technical support 59

Index

50200152-1/2.13

© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks ofMicrosemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductorsolutions for: aerospace, defense and security; enterprise and communications; and industrialand alternative energy markets. Products include high-performance, high-reliability analogand RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, andcomplete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more atwww.microsemi.com.

Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996

http://www.microsemi.com

Documents

IGLOO PLUS Starter Kit User’s Guide