ALTERNATIVE SOLDERS FOR FLIP CHIP APPLICATIONS IN THE AUTOMOTIVE ENVIRONMENT

Erik Jung, Katrin Heinricht, Joachim Kloeser, Rolf Aschenbrenner and Herbert Reichl"

Fraunhofer Institute FhGnZM-Berlin Gustav-Meyer-Allee 25; 13355 Berlin

Phone: +49 30 464 03 230; Fax: +49 30 464 03 161; E-Mail: erju@izm.fhn.de

*Technical University of Berlin

Berlin, Germany

Abstract: Lead is one of the main components of almost all solders used in the electronics assembly industry. Growing concern over the long term toxicity of lead in connection with the disposal of electronic devices in landfill sites provides a driving force for the investigation of lead free substitutes for eutectic SnPb solders in mainstream electronic applications. In addition to the toxicity of lead there are other problems concerning Sn/Pb solders. In automotive and other harsh conditions applications (avionics, aerospace) where the solder joints are subjected to many thermal cycles, severe vibrations, and sustained temperatures of up to 150°C and peak temperatures of 180°C the critical failure mode of eutectic S o b solder in assemblies is bump fatigue, Especially for flip chip technology the induced thermal stresses and strains in the solder joints are very hazardous. Therefore, there is a real need to find high performance solder alloys with improved mechanical properties and microstructural stability.

This paper presents a flip chip technique based on electroless NYAu bumping and stencil printing of solder paste on wafers. These processes has been developed by IZM/TUB. Due to the fact that the variety of solder pastes is still growing chemical Nickel plating in combination with solder printing is a very flexible and cost effective bumping method.

For this technology in the first part of this paper the motivation, the basic process steps and key aspects are described in detail.The experimental results of an ultra fine pitch printing technique on wafers are shown and the reflowed solder bumps are characterized conceming uniformity and streneigh. In comparison to eutectic Sn/Pb solder different alloys SnlBilCu, SdAg, SdCu, AdSn are selected and investigated in this paper.

In the second part of this paper a comparison of the properties of different solder alloys conceming the usability for flip chip technology, microstructure evaluation and phase compositions are presented. The microstructure coarsening and phase growing after thermal aging are investigated as well. In order to investigate the influence of the CTE-value of the substrate material on reliability the flip chip assembly was performed on LTTC and FR-4 substrates. The quality of the flip chip joints were investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling with and without underfil on both types of substrate materials are presented.

INTRODUCTION As the electronic industry continues to expand into new areas, as well to improve existing products, original equipment manufacturers (OEMs) are looking for new ways to make their products smaller, lighter and less expensive. Here the flip chip and CSP technology provides excellent capabilities to fulfil the needs of today's and tomorrows requirements. These technologies has already obtained an increased level of acceptance for many different applications. Over the next few years flip chip technology is expected to become widespread reality in automotive,

consumer and telecommunication applications /I/. A breakthrough, however, will only be reached once the use of flip chip promises cost reduction, increased package density and reliability improvement.

Soldering operations are important manufacturing steps in the interconnection and packaging of nearly all modem electronic products. Lead tin alloys are the most often used solder materials because of their low cost and unique combination of material properties.

0-78034520-7/98 510.00 01998 IEEE 82 1998 IEEElCPMT Berlin IMI Electronics Manufacturing Technology Symposium

Environmental and long term toxicity concerns related to the use of lead have initiated the search of acceptable, alternative joining materials for electronic assembly /2/. In connection with the disposal of electronics in landfill sites where there is a danger of contamination of ground water. Economic sanctions, taxes or bans restricting the use of Pb in electronic products could lead to escalated costs of use and disposal solder paste /3/. Despite some claims, there has not yet been a completely viable alternative to the lead- based solder alloy that can be used as a direct replacement, utilizing existing manufacturing process.

Besides the ecological aspects for flip chip applications the need is to develop new solders that have similar processing characteristics and usage cost to Pb/Sn solders, but are lead free and have improved mechanical properties and microstructural stability. Current lead-tin solders lack shear strength resistance to creep and resistance to thermal mechanical fatigue. A solder which exhibits enhancements of these properties is crucial in automotive and other high- reliability products and high-temperature assemblies. Nevertheless, one of the important goals for the development of lead free solders for flip chip technology is to increase the reliability of the flip chip joints in order to renounce the underfil process step. In this context flip chip assembly using different solder alloys was performed on substrates with different CTE values. For reliability testing thermal cycling was performed between -55OC and +125"C. The first screening of the lead free solders for flip chip applications are focused to select potential and promising candidates for further more detailed studies.

SELECTION OF SOLDER ALLOYS Temperature Ranges and Applications The global drive to replace the use of toxic lead metal and alloys in industrial applications has focused, in part, on the development of new Pb-free solder alloys. The eutectic S o b alloy is by far the most commonly used solder in industry and a simple drop-in replacement alloy with substantially the same melting temperature is in great demand /4/. On the other hand for instance it is common practice in electronic packaging to solder the various levels of the package with different solders of different melting points so that the soldering of each successive level or step does not remelt the previously soldered joints. The U.S. National Center for Manufacturing Sciences has selected 3 operating temperature ranges for replacement of lead tin solders in electronics industry / 5 / :

0 -55OC to +IOO"C consumer & telecommunications

0 -55OC to 125OC military

0 -55OC to 180°C aerospace & automotive

83

Because the reflow temperature should be universally acceptable in manufacturing the limit of 225OC - 23OOC on the melting poing of the alloys was considered. The targeted applications for the solder alloys are:

0 Low cost consumer electronics (typ. max. temp. 80°C) Thermoplastic substrates (3D-MID)

0 Conventional electronic products (typ. max. temp. l0O0C)

FR-4 PCB and ceramic substrates SMT, wave and hand soldering techniques

High reliability products (typical m a . temp. 150°C) Automotive, aerospace and advanced Communication electronics

0 High temperatures assemblies (typ. max. temp. 1 SOOC) Automotive under the hood assemblies Power semiconductor die bonding

Important Properties of the Applied Sn/Pb and Pb-Free Solder Alloys In theory many solders could replace or complement the eutectic solder in assembly technology. Several authors have already published results of alternative solders 16, 7, 8 9, lo/. The investigations in this paper are focused to solders suitable for flip chip technology. The following criteria were established for the development and selection of ideal lead-free solders specifically designed for electronic assembly use:

0 Physical properties Melting temperature and range Surface tension Electrical conductivity Thermal conductivity

0 Microstructure Grain coarsening Phase stability Intermetallic growth

0 Solder substrate interactions Phase formations Substrate dissolution Wetting behavior

0 Mechanical properties Tensile strength Shear strength Elongation Creep resistance Thermal fatique

0 Compatibility with existing flux systems

1998 IEEVCPMT Bedin Inrl Electronics Manufacturing Technology Symposium

Availability

costs

Capable to form solder pastes (printability)

Solder Alloy

SnJPb -6337

SnnlBiiCu -90!9.5/0.5

Based of the sums of weighted propee data for various promising alloys we selected the alloys for experimenral study and evaluation shown in table 1. Conceming the reflow temperature the Sn!Bi;%u paste is a promising alternative to SnPb alloys because of its similar melting point and excellent mechanical properties. For high temperature applications eutectic Sn/Ag-, Sn!Cu- and Au'Sn pastes are used. Except the eutectic AdSn solder alloy all solder pastes can be integrated in a SMT reflow process flow. For the AdSn solder paste the reflow temperature of the furnace must be increased. The advantages of these paste are excellent fatigue behavior and the possibility of fluxless soldering which becomes very important for medical and applications and optoelectronics.

Melting Point Reflow (Peak) Properties Temperature 220 - 230 "C

230 - 245 "C

183 "C (eutectic)

198 "C

Standard solder reference sample

Potential drop in, high wettabiliw, fine

Table 1 includes the possible substrate for use with flip chip devices. For this low temperature cofired ceramic substrates (LTCC) and rigid or flexible laminates have the most

SnlCu - 97i3

Au!Sn - 80/20

promising potential. In the automotive under-the-hood applications for example LTCC substrates are used ai the moment but for further cost reduction organic laminates are under development as well , ' l l ' . The development of underfil materials which compensate the mismatch in the coefficient of thermal expansion (CTE) between the chip and the subsnare plays a key role for the applicability of flip chip technology especially on Ion cost FR-4 boards /12/, /13. It could be also demonstrated that encapsulation on ceramic substrates leads to a significant improvemenr in the life time of these devices 14 - 16 .

I

227 "C (eutectic)

280 'C (eutectic)

250 - 265 3C

3 10 - 530 "C

High melting. lower costs

High melting point. fluxless soldering Excellent farigue resistant Medical applications, optoelectronics

The main tarzet for the selection of a non lead containing solder for use in flip chip technology was to improve the overall reliability of the flip chip joints. Therefore an enhancement of the mechanical properties of the alternative paste is an important issue. Furthermore, the selection of the solder pastes was limited by the availabilily of the paste for fine pitch stencil printing. Hence, the printing experiments were performed for a moderate pitch of 300 um.

- 260 "C I Excellent wetting. high shear strain

Table. 1: Applied solder pastes for stencil printing

EXPENMENTAL SET UP In the following the basic process steps required for the development of a cost effective and flexible flip chip technology are described in detail. Figure 1 shows the elements of an in-line flip chip assembly process capable of high volume production.

Figure 1: Basic processes and materials for low cost flip chip assembly technology.

Applied Substrate Material

FR-4, FR-5, BT- Epoxy, Ceramics FR-4, FR-5, BT- Epoxy, Ceramics FR4, FR-5, BT- Epoxy, Ceramics

EDOXV. Ceramics FR-4, FR-S, BT-

Ceramics

Process Flow Figure 2 shows the process flow for flip chip assembly b> solder paste printing on wafers. Based on electroless Kickel bumping solder paste was printed on wafers. In contrarq to evaporating or electroplating techniques electroless NiiAu deposition in combination with stencil printing offers a IOU- cost bumping approach with high flexibility. In the following the single processing steps for this technology will be described in detail.

Flip Chip Bumping 6: Assembly Process

Flip Chip Bumping

Flip Chip Assembly

Figure 2: Flip chip assembIy process flow compatible to SMT.

Electroless NiiAu Bumping A key issue for flip chip technology will be the implementation of low cost bumping processes. Chemical bumping processes based on electroless nickel plating have been presented from several authors /I7 - 22.’ as a low-cost altemative. The bumping process is wet-chemical and maskless Ni bumps (figure 3) fi~lfil the following function. They protect the A1 and act as adhesion layer and a diffusion barrier and guarantee a stable and reliable contact to the A1 bond pads, Furthermore Ni’Au bumps offer a surface with very good suitability for flip chip soldering.

Figure 4 shows chemically plated nickel bumps on a 6‘- CMOS wafer. A height of 5 pm is recommended for FC soldering as it meets the requirements of reliability and fast processing. In 2 2 , 2 4 the process flo? and the wafer

design rules of the NUAu bumping process were described in detail.

passivation Ni

AI bondpad

Si wafer /

Figure 3: Structure of a NVAu bump.

Figure 4: NUAu bumps on a CMOS wafer.

Solder Printing For flip chip soldering a selective solder deposition on the wafer or subsaate is essential. The highest potentia1 for low! cost flip chip assembly has the stencil printing of solder paste. The printing technology is widely used, e.g. in SMT assembly. The challenge is to develop this technique toward a flip chip suitable pitch of 200 pm and below for mass volume production. To achieve reproducible and homogeneous solder deposits the process techniques for fine pitch printing require an improvement of the physical properties of solder paste, of the stencil materials and stencil processing technologies as well as the printing equipment n5i . Using solder printing for ultra fine pitch applications solder pastes with very small particle sizes. a nitrogen atmosphere and well controlled temperature profile of the reflow furnace is required

Stencil Printing On Wafers Depending on the application stencil printing of solder pastes can be performed on substrates and whoie wafers. The volume and the height of the deposited solder depends on the thickness, the size of the openings of the applied stencil and the squeegee material. In this paper the studies are focused to processes for stencil printing solder paste on wafers. For fine pitch printing in the past few years toois

85 1939 IEEE CPMT krlr It? I Electronics Manuia~unng Techwlq) Sy?nposiurr

and processes have been improved. Efforts have been focused on the development of soldering materials, especially solder pastes. For flip chip applications the particle size of the solder paste is one of the most important factors. Therefore some suppliers developed pastes with homogenous distribution of particles and sizes smaller than 25 pm.

UBM Solder material

Experimental Results The printing was performed with a precision printer from Fuji Machines and we used a closed squeegee system. The snap-off distance was set up 0 mm. Stencils with apertures made by laser cutting from Systronic were used for the experiments. The stencil apertures were adapted to the specific application. The volume of the printed paste is determined by the aperture diameter and the stencil thickness. Since the aperture size is limited due to the pitch, the stencil should be as thick as possible. On the other hand a high thickness to opening ratio will increase the risk of paste sticking. Therefore the selection of the appropriate stencil geometry is essential for printing with high yield /26/. For the experiments printing was performed on 4" wafers according the process flow in figure 1. The Ni UBM has a thickness of 5 pn. Thicker Ni will not significantly increase total height of the solder. The final height of solder bumps depends mainly of the printed paste volume. The fi,pures 5-7 show the results of solder printing on wafers using a PbSn63 solder paste is with particle sizes from 15 pm - 25 pm. The thickness of the stencil was 80 pm and the stencil was produced by Systronic by laser cutting.

5 pmNiP 10%

PbfSn-63/37

Fig. 5: SEM pictures of solder bumping steps: (a) bond pad in initial state, (b) with NVAu UBM, (e) with printed solder paste and (d) after solder reflow.

~ ~~ ~

Melting temperature

Typical height

The solder paste is reflowed in a convection oven under nitrogen atmosphere. Flux residues are cleaned in a solvent adapted to the used solder paste. Fig. 5 shows SEM

I83 O C

75 pm - 150 pm (depending on pitch)

photographs of a bump site during processing. Typical height of reflowed solder bumps is 100 .um at pitches down to 200 pm (see fig. 6). Maximum possible solder bump height is determined by the smallest pitch and bond pad layout of the wafer. The achieved bump uniformity is i 5 pm on 4" wafers. The distribution of bump heights on a wafer is shown in fig. 7. Specifications of solder bumps are summarized in Table 1.

ELmp"

Fig. 7: Solder bump height distribution on a 4" wafer.

I Bump Characteristic Specification

Wafer sue Table 1: Solder bump specifications.

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FLIP CHIP ASSEMBLY The flip chip assembly was performed using a automaticallq placing machine (Fuji QP2) according the process flow in fisure 2. Solder paste printing only on wafers was performed. No additional paste was prinred on the substrate.

For the reflow process of fine pitch solder pastes a nitrogen atmosphere is recommended. The reflow. temperature depends on the applied pastes. After the reflow process and electrical testing an underfl uas applied (Hysol 451 1). For the experiments we used an Asyntec (M-FCOB) equipment for dispensing the underfil material.

Test dies with 2 . 5 2 . 5 , 5.Oxj.0, 75x75 and 10.Ox10.0 mm' size and a pitch of 300 um was used. Octagonal bond pads had 80 pm diameters. The pad configuration on the die was peripheral. The dies had daisy-chain structures for the measurement of transition resistance. In addition the three larger die types allowed four-point measurement of contact resistance. Ni/Au bumps with heights of 5 pm were chemically deposited on the wafers as UBM.

The FR-4 boards had 20pm Cu leads and a final metallization of 4 um Ni'Au. The thickness of the solder mask was approx. 18 um. The LTCC substrates had a thick film metallization of 8 um - 10 um PdAg and Au. The CTE value of the organic boards was appr. 17 in contrary to the CTE value of 7 of the ceramic substrate.

EXPERIMENTAL RESULTS AND RELIABILITY TESTS The mechanical properties of solder joints are strongly dependent of the solder microstructure and interface structure. Refowed eutectic Sn/Pb-63.'37 solder has a very fme structure composed of fine grains of practically pure tin an lead at room temperature. At higher temperatures the initial microstructure will coarsen with time to form energetically more favorable structure. As the solder is subjected to high temperatures and stresses, such as thermal cycling. the microstructural evolution will accelerated. Moreover, interfacial reactions between the solder and bump interconnect and substrate metallization will continue at high temperatures. The coarse microstructure of eutectic SnPb solder may be a problem where the stresses directed to the solder are large. as the case with Fsilicon chips mounted to FR4 boards. Due to the coarsening of the microstructure, here the failure mode under harsh testing conditions (-55OC - t.125"C: -65OC - LISO"C) is bump fatigue. The cracks are found to initiate in areas of microstructural coarsening. Therefore, for high temperature operating systems an improved fatigue resistance solder alloy is needed which keeps their initial fine and uniform microstructure.

Preparation Of Test Sampies Due to the different flux formulations of the various solder pastes, the metal content of the pastes differ. Especially, as except for the SnPb63/37 solder paste all other pastes were not specifically designed for flip chip applications. Thus, as they have non-optimized particle distribution, they may vary largely in their metal content by volume and in their printing characteristics (eg. rheological properties). This results in different bump heights after reflow when using, the same stencil geometry.

Fig. 8 shows an underfilled flip chip assembly on FR-4 boards. For this SnfPb paste was printed on a wafer and reflowed. Finally the bumped dies were assembled to the board by a second reflow.

Table 3 gives the respective bump heights obtained with the different solder pastes (mean of 30 measurements).

Table 3: Bump heights with the different solder pastes (stencil thickness: 80 ptm)

Figure 9: Cross section of flip chip joints on FR-4 boards.

This implies that the subsequent results must be carefull). analyzed. The microsmcturai appearance of the bumps was investigated using SEM. It was observed. that the SnPb- 63'37 solder shows much coarser gain structures than the SnlCu-97.'3 or Sni'Ag-96.5/3.5. AuSn-SO20 and SniBi/Cu- 90'930.5 show microstructures in between the fine ness of

87

the beforementioned alloys. Figures 9-1 1 show the respective SEM images.

Alloy

Fig 9: Flip Chip Bump Solder (500x) Pb/Sn-37/63

Joint height (pm) Initial contact over substrate resistance metallization (mR)

a) b) Fig 10: Flip Chip Bump Solder (5OOx) a) Sn/Cu-97/3 b) SdAg96.5f3.5

SnPb631'37 SnAg96.5'3.5

Fig 11: Flip Chip Bump Solder (5OOx) a) Sn/Bi/Cu-90/9.5/0.5 b) AulSn-80L20

117 7.9 100 5.5

According to this fine grained morpholog and according to the results of previous investigations. this should allow a greater shear resistance and an increased lifetime by greater fatigue resistance E'. Shear tests performed at different states of thermal exposure (125'C up to 1024hrs) revealed that for flip chip bumps this general nile does not hold, as not only the bump material is tested and stressed but also all associated interfaces. Fig. 12 shoHs the respective graph of shear forces for the different alloys. Xo major influence of thermal exposure to 125°C on the bump adhesion could be observed during this test.

< 7

The Au!Sn-80:'20, as a high temperature solder was exposed to 150°C Here a slight degradation of the shear force due to grain coarsening at the 150°C exposure temperature was observed. However, no adverse influence on the flip chip reliabiliq i s expected.

SnCu97 '3 12 1

I .

d .-

2c -/ Y , 0 500 1003 1500 2000

Time of Exposure to 125'C (15OT AulSn) [hn]

Figure 12: Shear force YS. time of exposure to 125OC (1SOOC with AuSn80120 solder)

SnBiCu90!9.5/0.5 AuSn8020

RESULTS The Au<Sn-80:20 metallurgy being a high temperature solder, could be used only on the LTCC ceramics. To allow a comparison to a reference sample, Sn/Pb-63/37 and SnfAg-96.513.5 solder was also used on the LTCC ceramics. After joining and underfilling, samples of the different alloys were cross sectioned and measured for the respective joint height. In all cases a nearly void free underfl could be observed as the underfil could easily penetrate the resulting gap between solder mask and chip. The joint heights reflect the different bump volumes achiesed by the printing the different pastes. Table 4 summarizes the results.

11s 5.1 71 8.5

Figures 13- I5 show some representative cross sections from flip chip assemblies.

Fig. 13: Flip chip contacts of FR-4 boards; SnlPb-63137 SnlBilCu-90/9.5/0.5

86

Fig. 14: Flip chip contacts of FR-4 boards a) SnlAg-9633.5 b) SnfCu-,97/3

a> Fig. 15: Flip chip contacts on ceramics a) SnlAg-96.513.5 b) AuISn-80120

Following the undefill cure, the samples were electrically tested for their initial contact resistance and integrity of the daisy chained contacts. Subsequently they were subjected to thermal shock testing (-553C/+1250C. 1 Omin dwell). Based on previous results, additional electrical tests were performed after 500. 1000,2000 and 4000 thermal shocks. For the reliability tests 10 mm x 10 mm dies with 120 peripheraI bumps were used. For the experiments 12 chips of every allo? were used.

In the case of the FR4 board, the metailurgl 1SnAg3.5 shows first failures prior 1000 cycles. SnPb6W'J showed first failures prior 2000 cycles (see figure 16 and figure 17).

Chip Sne 10 mm x 10 mm Board MetaUaahn CdNu'Au

Chip Metatlzahon N d h

Underfill Hysoi 4511

- E - 10

8

6

I 3 0 1000 2000 3000 4C100

Number of Thermal Cycies [ -55 'C I + 125'Cj

Figure 16: Contact resistance vs. number of cycles on FR 4 boards

89

Figure 17: Contact resistance vs. number of cycles on ceramics

Solder fatigue was identified for the SnPb solder as a reason for the electrical failure (see figure 18). the SnAg metallurgy failed because of underf3 delamination. The reason for this is attributed to a non perfect cleaning process, as the solder paste and the cleaning process did not fit perfectly together leaving minute contaminant layers on the die. This contaminant layer lowers the underfill adhesion and promotes the early failure. Future experiments will focus on this aspect.

Figure 18: Solder fatigue; failed contact after 2000 thermal cycles (SnPb-63/37)

In the case of ceramics, none of the used metallurgies show a significant rise in contact resistance (see figure 17). (The increase observed with the smallest die of the SnPb63G7 solder sample is expected to be due to an underf3 void as only one contact contributes to this raise).

SUMMARY A chemical wafer bumping process based on electroless Ni plating was presented. A very good uniformity of bumps has been obtained and the results of reliability investigations were excellent. Cost for chemical Ni bumping are significantly lower compared to other conventional techniques. In the case of using Ni/Au bumps for flip chip assembly wafers, chips or substrates must be prepared by deposition of solder in a separate process. Therefore at the IZM different promising methods exist. The resulting flip chip assembly techniques are very flexible and cost effective. Different lead free solder paste have been stencil printed on wafers, ceramics and FR-4 substrates. Different types of test dies with chemically plated Ni/Au bumps were soldered in a reflow furnace to the substrate. After underfilling the chips their reliability has been tested. The results show that the combination of chemical bumping and solder paste printing for flip chip assembly is very flexible and a reliable low cost technique. Further investigation on the lead free solder pastes is necessary to find out the optimal metallurgy for industrial application. A main issue to be solved by the paste suppliers is to improve the printability of these promising alloys for flip chip applications. In order to demonstrate the low cost approach of the flip chip technique presented in this paper a fully automatic flip chip line was established at IZM-Berlin. For industrial partners this center will serve as a source for production of demonstrators and prototypes as well as small and medium series.

ACKNOWLEDGMENTS The authors want to acknowledge Mrs. B. Otto for electrical measurements, Mr. E. Busse for metallographic preparations and Mr. Vogelsang and Mr. Wojakowski for their help. Special thanks goes to Mrs. Liane Lauter from TU-Berlin and Dr. Dietz from Degussa for his support and helpful discussions.

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