IEEE TRANSACTIONS ON SEMICONDUCTOR · PDF filetest-structure to analyze the magnitude of spatial correlation of ... Many steps within the manufacturing ... of characterization of the

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009 245

Lack of Spatial Correlation in MOSFET ThresholdVoltage Variation and Implications for Voltage

ScalingNigel Drego, Student Member, IEEE, Anantha Chandrakasan, Fellow, IEEE, and Duane Boning, Fellow, IEEE

Abstract—Due to increased variation in modern process tech-nology nodes, the spatial correlation of variation is a key issuefor both modeling and design. We have created a large arraytest-structure to analyze the magnitude of spatial correlation ofthreshold voltage in a 180 nm CMOS process. The datafrom over 50 k measured devices per die indicates that there is nosignificant within-die spatial correlation in . Furthermore, theacross-chip variation patterns between different die also do notcorrelate. This indicates that Random Dopant Fluctuation (RDF)is the primary mechanism responsible for variation and thatrelatively simple Monte Carlo-type analysis can capture the effectsof such variation. While high performance digital logic circuits, athigh , can be strongly affected by spatially correlated channellength variation, we note that subthreshold logic will be primarilyaffected by random uncorrelated variation.

Index Terms—Spatial correlation, threshold voltage, variation.

I. INTRODUCTION

S CALING has resulted in poor control of parametric varia-tions, increasing focus on such variations as an important

design consideration [1]. Many steps within the manufacturingprocess introduce layout/pattern-dependent or spatial variation,including 1) subwavelength lithography, 2) plasma etch, 3)ion implantation and annealing, and 4) chemical-mechanicalpolishing [2], [3]. In particular, the physics of the fabricationprocess, or spatially varying characteristics of the layout (suchas pattern density), can act to create deviations in device orinterconnect geometry or material properties that have repeat-able spatial patterns. In some cases, the matching betweendevices or structures has a strong dependence on the separationdistance between those devices; i.e., there exists significantspatial correlation in the variation.

Much of the existing literature focuses on approaches to ef-ficient modeling of spatial correlations of process parametersand their impact on timing in circuits [4]–[6]. Methods for ro-bust extraction of spatial correlations from noisy measurements

Manuscript received July 23, 2008; revised January 08, 2009. Current versionpublished May 06, 2009. This work was supported by the Focus Center for Cir-cuit & System Solutions (C2S2), one of five research centers funded under theFocus Center Research Program, a Semiconductor Research Corporation Pro-gram.

The authors are with the Microsystems Technology Laboratories, Depart-ment of Electrical Engineering and Computer Science, Massachusetts Insti-tute of Technology, Cambridge, MA 02139 USA (e-mail: [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TSM.2009.2017645

have also been reported [7], [8]. Most, if not all, of this literaturelacks data to substantiate the models and methods developed. Asa result, the assumptions and functional forms of these modelingapproaches to spatial correlation remain largely unvalidated.

Recently, the modeling community has had particular interestin the spatial correlation of parametric variations in the hope ofdeveloping algorithms and tools that allow designers to take ad-vantage of, or counter, known correlations. While this modelingcapability aids in robust design, it also has the potential to pro-vide even more advantage when developing adaptive systemsthat can detect and respond to parameteric variation. However,the substantial data necessary to compute accurate spatial cor-relations is often difficult to acquire, leaving the modeling com-munity guessing as to the functional forms of the spatial corre-lations present (if any).

To date, most spatial correlation data analysis has consideredchannel length variation [9]. However, there has been in-creasing attention to the measurement and characterization of

variation in large device arrays with the work of Agarwalet al., Rao et al. and Mukhopadhyay et al. at IBM [10]–[13],Fischer et al. [14] and Wang et al. [15]. Only a subset of thesepresent data regarding spatial correlation analysis of the mea-sured results. Agarwal et al. present spatial correlation analysisof SRAM-sized devices in a 65-nm SOI process, concludingthat little spatial correlation in within each die exists at 65nm. Fischer et al. also provide variation data and autocor-relation analysis of 1-M SRAM cells at both the 90 nm and65-nm nodes, with the results again showing no spatial correla-tion. Furthermore, both the aforementioned works make little tono effort to isolate threshold voltage variation from variation inchannel length or other variation sources. Sabade et al. [16] usewafer-level spatial information on chip-level leakage currents topredict neighboring chip leakage currents and screen faulty die[16].

In [17], we described the analytic basis and a custom test-cir-cuit to gather intrinsic variation data, which isolatesfrom other parameters by measuring subthreshold currents ofMOSFETS, similar in approach to [10]. Here we contribute thethreshold voltage variation data, focusing on the analysisand implications of this data. We present extended variationanalyses, beyond those in [10], including examination of poten-tial correlations in the variation patterns between pairs of die.A surprising result is that, once variations in channel length areproperly isolated, no significant spatial correlations are found in

, even in the 180 nm technology used here. Given this lackof within-die spatial correlation, we examine the effects on dy-

0894-6507/$25.00 © 2009 IEEE

Authorized licensed use limited to: MIT Libraries. Downloaded on December 29, 2009 at 11:06 from IEEE Xplore. Restrictions apply.

246 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009

namic voltage scaling (DVS) systems. We find that while cir-cuit performance deviations between nearby circuits might behighly correlated at nominal operating voltages due to high cor-relation in channel length, this performance correlation quicklyfalls off as random, uncorrelated variation begins to domi-nate at lower voltages.

In Section II, we describe the analytic basis in using sub-threshold leakage currents to extract threshold voltages. Here,we also detail the test structure used to measure the sub-threshold currents from a large number of MOSFETs in a

array, and provide simulation results detailinghow well the structure is able to isolate variation from othertypes of variation. This is followed by a detailed analysis ofthe extracted threshold voltages of these devices in Section III.We then describe the modeling and circuit implications of theobserved variations, paying close attention to how correlation(or lack of correlation) in parameter variation affects DVSsystems in Section IV. Conclusions are presented in Section V.

II. THEORY AND ENABLING CIRCUITS

In this section, we describe the device operation fundamen-tals and analytic basis used to extract variation from leakagecurrent measurements, as well as the overall test chip architec-ture and circuits.

A. Extraction of

The intrinsic or ideal threshold voltage, , of a MOSFETis defined by (1), where is the flat-band voltage, is theFermi potential of the substrate, is the body-factor and isthe source to body bias. Thus, is fundamentally dependentonly on substrate doping, , and the oxide thickness, ,through :

(1)

However, due to short-channel effects, notably drain-inducedbarrier lowering (DIBL), in the deep submicron regime, the ac-tual threshold voltage, , becomes a function of not onlyand , but also channel length, , and source/drain junctiondepth, [18]. To quantify this dependence, is now definedas a summation of the ideal threshold voltage and a shift

due to short channel effects, as in [19].The appropriate modeling of variability requires modeling

variability in each of the fundamental parameters. However,measuring variability in many fundamental parameters (e.g.,

) is often extremely difficult. As such, many modeling andsimulation programs, such as Hspice, allow modeling of vari-ability in parameters critical to circuit designers: andthrough the use of the parameter and direct manipula-tion of in the netlist [20]. This work seeks to characterize thevariation and, in particular, spatial variation of to enablesuch modeling and simulation. This requires isolation offrom other common sources of variation such as , and canbe achieved to a large degree in the subthreshold regime of tran-sistor operation1.

1From this point forward, we will use and interchangeably indicativeof characterization of the ideal MOSFET threshold voltage.

In this regime, the current through the transistor is given by(2), where is the drain current at , is the body-effect coefficient, is the DIBL coefficient, is the subthresholdslope ideality parameter, defined by (3), and is the thermalvoltage:

(2)

(3)

The term in (2) is easily eliminated with

, and can be eliminated by shortingthe body and source of each device. Minimization of the DIBLcomponent is achieved by reducing to a few hundredmillivolts—large enough to eliminate the term, butstill small enough to minimize the effect of DIBL. Assumingthat , , , and are identical for two arbitrary devices,taking the natural logarithm of the ratio of the currents of thosetwo devices will result in a simple, analytic equation for the

of those devices2, as shown in the following derivation:

(4)

(5)

(6)

It is known that the subthreshold slope between devices canvary, and thus the assumption that is identical for the devicesbeing compared is not valid in general. Taking this into account,the above equations can be reworked and shown to provide therelationship in (7) between the drain currents, threshold voltagesand :

(7)

Since (7) provides no simple, closed-form solution for ,the values of , , and at least one device must beknown to compute the other and thus a delta between the two.Equation (3) shows that can easily be computed using twomeasurements of at differing values of . We also notethat by using a small value for we can minimize the contri-bution of the second term in (7) in two ways: a smaller re-sults in 1) a smaller multiplicand, and 2) as can be seen in Fig. 2,the instantaneous value of tends to converge at extremely low

despite variation in , allowing use of (6) rather than (7).Ascertaining the value of one of the device threshold voltages

is more difficult, but possible by finding the value of wherethe subthreshold current deviates from the ideal log-linear form.This known can then be used to compute the for every

2This denotes the difference in ideal threshold voltage between twodevices and is distinct from in [19] which describes the shift in a singledevice’s threshold voltage due to short channel effects.


DREGO et al.: LACK OF SPATIAL CORRELATION IN MOSFET THRESHOLD VOLTAGE VARIATION AND IMPLICATIONS FOR VOLTAGE SCALING 247

Fig. 1. Simplified variation architecture and circuits.

Fig. 2. Convergence of at low despite variation.

other DUT. By using (7), along with two additional measure-ments for each DUT (to compute ), a complete map of alltest devices across the chip can be ascertained.

A more practical method is to compute an average value,, where each can be computed from

subthreshold leakage current measurements, and then usein (6). This has the added benefit that post-processing of thecurrent measurements to extract remains computationallyefficient. Furthermore, the error associated with using this av-erage value is small if .

B. Test-Structure Architecture and Circuits

Fig. 1 is a simplified schematic showing the architectureand circuit blocks to measure variation. A dual-slope, inte-grating analog-to-digital Converter (ADC) is used to measuresubthreshold leakage currents due to its suitability to accuratelymeasure small currents. By externally setting , the oper-ational amplifier enforces a virtual ground at the input nodes,ensuring that each device connected is biased at the same .Amplifier gain and mismatch errors will introduce error into thevalue of seen by the DUTs, but each DUT is affected in the

same manner. Large input devices and a high-gain dBensure that this error is small nevertheless.

To measure currents of many devices efficiently, we use asingle ADC that is multiplexed among all devices. Apart fromthe area efficiency achieved by using a single ADC, this ensuresthat any non-idealities in the ADC are common to all DUTsand therefore do not affect the results. We have chosen to use ahierarchical access scheme analagous to a memory, with rows,columns and sections. Each bank contains 128 PMOS and 128NMOS DUTs organized in columns, and each section contains90 rows of banks. Bank enable pass gates steer only the cur-rent of the selected device to the measurement circuitry. Thetest-chip contains 540 banks organized into 6 sections for a totalof banks columns DUTs of each type in a

mm mm array. All device lengths are minimum length forthis technology m . The lower portion of this array con-tains banks with random designed device width ranging from

m, the minimum allowable, to m, while in the upperhalf of the array, each row contains the same device width.

While the row and column access transistors introduce re-sistance and variation, HSpice simulations show that avariation in either or of the access transistors haseffect (Section II-C) on of the DUT being accessed. De-spite column access transistors being turned completely off forall other DUTs, a finite leakage current, , through the rowand column access transistors and the “off” DUTs adds to the

of the DUT being accessed. When of the accessed DUTis large, corresponding to a larger , is a negligible com-ponent and can safely be ignored. However, as described in Sec-tion II-A, it is desirable to set as low as possible to benefitfrom the convergence of at low . At gate biases below0.25 V, reduces to nanoamps or smaller, so that even smalldrain-source leakage currents and drain/source-body junctioncurrents accumulate over the “off” DUTs and their access tran-sistors.

Each of the bank enable pass gates are high- devices tominimize these parasitic leakage currents emanating from unac-cessed devices. However, even with very small parasitic leakagecurrents from each of these pass gates, the large number of gatescan result in these parasitic currents summing to a current large



Fig. 3. Test-chip die photo. The DUT array is shown at left, with the ADC anddigital control and calibtration blocks at right.

enough to interfere with the current being measured. An ac-tive current subtraction scheme was devised and implementedon-chip as shown in Fig. 1. Two (source and sink) 8-bit ther-mometer-code DACs [21] with digital control logic are added toactively add or subtract current equivalent to . The digitallogic implements a binary search algorithm that uses the outputof the ADC to converge upon the correct DAC input value andacts as an auto-zeroing mechanism. For example, when tryingto measure the first NMOS DUT in a bank, the auto-zeroing isfirst run when all DUTs in the bank are off. If the ADC outputis anything, but 0, after the first auto-zeroing measurement, thedigital logic will completely turn on one of the two DACs shownin Fig. 1 in response to the direction of . If is beingdrawn from the measurement circuitry to ground, the algorithmturns on the source DAC (top of Fig. 1) in order to “source”and remove its effect from the measurement. Analogously, thealgorithm will turn on the sink DAC (bottom of Fig. 1) to “sink”an flowing from to the measurement circuitry. Subse-quent measurements are used to refine the DAC control word ina logarithmic fashion. Auto-zeroing is performed once for eachbank being tested at a specific gate bias. Due to the discrete na-ture of a DAC as well as limited resolution, the auto-zeroingwill not be perfect, and residual is treated as an offset andsubtracted from DUT current measurements.

The test-chip was implemented on a National Semiconductorm bulk CMOS process. Fig. 3 is a die photo showing the

mm mm test-chip, of which mm mm is the denseDUT array.

C. Simulation Results of Isolation

We next present simulation results showing that the abovetheory and circuits are effective in isolating and extractingeven in the presence of other types of variation, particularlychannel length variation. Furthermore, simulations show thatthe multiplexing circuitry contributes a negligible error in themeasured current.

1) Isolation: Simulations were performed in which asingle DUT, with row and column access transistors, charges anintegrating capacitor. Since the operational amplifier forces avirtual ground at the inputs, remains constant as the capac-itor is being charged, and can then be found using

. Simulations were performed with DUT andchannel length being varied by and being variedacross the allowable range, determined by the output stage of theoperational amplifier. The range in this design is 0.3 V–1.5 V.

The plots in Fig. 4(a) show the simulation results. The topplot in the figure varies DUT and , while the bottomplot varies DUT channel length and . Both plots show therelative change in current from the nominal or at a givenvalue of . The plots clearly show that the arrangement de-tailed above is more sensitive to changes in as a result ofvariation rather than variation, especially at low . Theseresults are consistent with the theory outlined in Section II-A.

To quantify these results further, the sensitivity of to ei-ther or can be computed by taking the derivative withrespect to and , respectively. Taking the ratio of thesederivatives gives the relative sensitivity of the circuit toand . Since it is clear from Fig. 4(a) that the circuit is leastsensitive to at low values of , these derivatives are onlycalculated for the lowest value allowable, 0.3 V. Fig. 4(b)plots the ratio of to for ranging from0.35 V to 0.5 V. Lower values of are not plotted, as a trendin decreasing sensitivity to with larger values of isevident from the figure. However, Section II-A discussed em-ploying lower values of , where the value of convergesdespite variation. The results of sensitivity analysis imply thatsimply measuring the value of , as discussed in Section II-A,and using a near the nominal for the process providemore benefit in extracting than attempting measurementsat extremely low gate biases. Furthermore, low gate bias valuesincrease the resolution and dynamic range requirements of theADC, and even more attention must be paid to preventingcurrents from unselected DUTs.

For all values of plotted, the sensitivity ratio through themajority of the variation range is below 0.1, meaning the circuitis at least 10X more sensitive to variation than to vari-ation. This is particularly true for where allbut the endpoints remain . Furthermore, sensitivity tovariation peaks in the vicinity of the nominal values of and

. Since variation in these parameters are typically normallydistributed about the nominal value, the majority of variationmeasured will be in the high- -selectivity region of operation,giving high confidence that the measured variation is pri-marily a result of threshold voltage variation.

Simulations were performed where a transistor was subjectedto variation ( or or both) and the ADC outputs used to de-termine the amount of variation with both (6) and (7). All simu-lations were done with V and V andthe ADC resolution set to 10 bits. Simulations were also doneat V, the results of which are used in conjunc-tion with (3) to calculate . Table II-C1 contains the results ofthese simulations showing the ability of the circuit to measurethe known variations. It should be noted that the simulationswhere only is varied result in approximately a 10% error in



Fig. 4. Current sensitivity to variation in , . (a) Percent change in current from nominal value at a given when varying (top plot) and channel length,(bottom plot). (b) Circuit sensitivity ratio.

TABLE IEXTRACTED VARIATION VERSUS SUBJECTED VARIATION

TABLE IISIMULATED CURRENT DIFFERENCES DUE TO INCLUSION AND VARIATION

WITHIN ACCESS TRANSISTORS ( V AND V)

the extracted deltas, primarily a result of the inherent inaccu-racy in using (6) which does not account for varying simul-taneously. This alone would indicate that this test-structure canresolve deltas of approximately 1% of the nominal . How-ever, since the sensitivity of the circuit to variation is notinfinite, resolution is reduced to approximately 2% of nominal

.2) Access Transistor and Resistance Effects: In order to hi-

erarchically access a large number of DUTs within an array,each DUT requires row and column access transistors, and eachbank of DUTs requires a pass-gate. These devices introduceadditional resistance, potentially lowering the and corre-sponding of the DUT due to the finite of the devices.However, operation in the subthreshold regime produces smallcurrents which are not perturbed substantially by even fairlylarge resistances. Simulations were carried out to evaluate thisimpact. The test circuit was used in these simulations with and

without row, column and bank access transistors. Table II-C2shows that the impact of these transistors and variation withinthem is less than 0.5% of the simulated current without any ac-cess transistors.

Another possible source of inaccuracy in implementing alarge array is variation in the distance current must travel tothe measurement circuitry, resulting in different resistancesseen by each DUT to the ADC. However, simulations showthat even with a k difference in resistance, the relativecurrent difference is only 0.1%. Furthermore, the path fromeach DUT bank to the ADC is implemented as a dense metalgrid spanning multiple metal layers to provide the lowestpossible resistance. Process data and simulations indicate thata minimum width wire spanning 2 mm has a resistance ofapproximately . However, the grid is implemented withmany 3X minimum-width wires spanning four metal layers,decreasing the overall resistance substantially. Since the resis-tance difference between any two DUTs cannot be more thanthe resistance of a single minimum-width wire spanning theentire array, we conclude that resistance variations in the gridwill have negligible effect on measured currents.

III. DATA ANALYSIS

We next examine the measured currents from K deviceson each of 36 chips. We first consider the ADC performance inmeasuring currents, followed by extraction of from ourdata. We then analyze device size and separation distance de-pendencies, and other within- and between-die spatial depen-dencies.

A. ADC Performance

We first characterize the static performance of the ADC, asthis component is critical to our current measurements. Since theinput to the ADC is a DC current, dynamic ADC performanceis intentionally omitted as it has no effect on the measured cur-rents. To alleviate noise concerns, measurements are repeatedten times and the average over the ten runs is used, as we assumewhite noise. In light of the limited input to the ADC, the primarymetric we characterize is the integral nonlinearity (INL), as thisgives the effective resolution of the ADC. Fig. 5 is a plot of the



Fig. 5. INL plot for a single ADC.

INL versus ADC code for a single chip, when the ADC is con-figured for 10-bit resolution and 600-nA full-scale current. Atthe high-end of the ADC range, the INL begins to degrade dueto limited bandwidth of the operational amplifier. This limits themaximum full-scale current to nA. However, a redesignof the operational amplifier could remove this limitation in fu-ture designs. The INL for the ADC shown in Fig. 5 leads to aneffective linearity of

. Out of the 36 chips measured, the worst case effec-tive linearity is bits, resulting in an effective resolution of

nA nA. The minimum resolvable is thencomputed according to (6), where is the maximum currentmeasurable by the ADC, is the current one ADC step belowthe maximum current and is conservatively estimated to be1.5 for this process. This gives mV, or 0.14% ofthe nominal for this process—below the 2% limit detailedin Section II-C—giving high confidence that ADC nonlinearitycontributes negligible error to the extraction of .

Implementation limitations resulted in disabling of the auto-zeroing DACs intended to cancel the off-DUT leakage currents.However, each bank is still calibrated by first doing a currentmeasurement with that bank’s pass gate enabled but with no de-vice enabled. Subtracting this measurement from the measureddevice current gives the true subthreshold current of the enableddevice, but limits the dynamic range of the ADC.

B. Current Measurements and Extracted

Using the analysis in Section II-A and measured currentsfrom DUTs within the array, we compute for each devicewith respect to a reference device in the corner of the array. Thevalues of needed for the computation are extracted by mea-suring currents at different biases ( V

V in 5 mV increments) and computing a best-line fit ona semilog scale. The slope of this line relative to the ideal 60mV/decade gives . A spatial plot of for one die is shown inFig. 6(a). From this plot, it is evident that does vary, althoughthe magnitude is small, so using the average value of betweentwo devices in computing the introduces only small er-rors3. Furthermore, due to the limits placed on the full-scale

3The error is less than , as this is the error when no attempt is madeto account for varying as discussed in Section II-C1.

current by the degraded linearity at high current levels (Sec-tion III-A), extracting an absolute to use in (7) is impos-sible, limiting calculation of to the formulation given by(6). This limitation can also be overcome in future designs.

Once has been computed from the measured currents foreach device, we compute . Fig. 6(b) illustrates thefrom each device to the reference device in the bottom rightcorner of the array for an example chip. While it appears thatthere may be some correlation in the upper half of the array,this is only due to the systematic designed device width patternfrom row to row in this section of the array, resulting in a shiftin standard deviation but not correlation as will be shown in thefollowing spatial analyses.

C. Pelgrom Modeling

To understand the effect of device size on standard deviation,we first show a Pelgrom plot of standard deviation of versus

[22]. We note that , whereis with respect to our specified reference device. Based on Pel-grom’s theory, we expect to see a linear relationship between

and . Fig. 7(a) shows this linear relationship fora single chip, where has been normalized relative to that fora device having W/L of m. Ideally, the best-fitline should pass through 0, indicating that devices of infinitearea should have a standard deviation of 0. Deviation from thisideal in our data may be a result of ADC measurement resolu-tion. Specifically, the data for many of the smallest devices in thearray m is excluded as their extremely small cur-rents are smaller than the resolution of the implemented ADC.In such cases, data is either nonexistent (measured values being0 as the currents were below the resolution of the ADC), or whendata was present, gives unrealistic values of due to thelarge ratio of ADC step size versus absolute current being mea-sured at the bottom of the ADC range. Data is excluded by ex-amining the computed values of and excluding any deviceswith a computed or . The majority of the ex-cluded data is for small device sizes in the tails of the distribu-tion, artificially lowering the standard deviation for these devicesizes. As a result, the data points on the far right of Fig. 7(a) tendto be slightly below the linear fit, and may also cause the fit lineto no longer pass through 0. In all further plots and data analysis,the data for devices with m is excluded to ensure dataintegrity. We believe that all trends in the data remain applicableto the small device sizes in this technology.

The Pelgrom model includes two terms: 1) an area depen-dent term with proportionality and 2) a distance depen-dent term with proportionality , as shown in (8). Fig. 7(a)shows a clear dependence on device area, but Fig. 7(b) showsno significant distance dependency. In Fig. 7(b), all pairs of de-vices within a specific chip having the indicated separation dis-tance are considered, and the standard deviation, normalizedto a m m device, across all those pairs is plotted.Results show that placing devices nearer to each other does notdecrease the variance between them. This will be discussed fur-ther in Section IV:

(8)



Fig. 6. Spatial distributions of and for a single die.

Fig. 7. Pelgrom fits of . (a) versus . (b) versus Distance.

D. Intra-Die Spatial Correlation

Since depends on device size, separate spatial corre-lation analysis by individual device size is necessary. Intra-diespatial correlation analysis is performed by computing the cor-relation coefficient for all devices separated by some distance,

, where as shownin (9), where is the between a given device andthe reference device. These correlation coefficients are thenplotted versus separation distance in Fig. 8(a) for a device sizeof m m. The bounds to determine statisticalsignificance (as a function of the number of available pairshaving separation ) are also shown on the plot. No spatialcorrelation is seen, as all data points fall within the significancebounds. Though this plot shows the data from only one devicesize on one chip, similar plots (omitted due to space constraints)for other device sizes and chips reveal the same conclusion:

(9)

The lack of spatial correlation indicates that variation israndom, and we find it to be normally distributed. Fig. 9 indi-cates that over 99% of the data points in this data set are indeednormally distributed. As supported by the measurement resultsat more scaled nodes, such as in [10], [11], [14], this leads to

the conclusion that variation must be dominated by randomdopant fluctuation (RDF), even at the technology node.Although line-edge roughness (LER) should be considered asa possible cause of random variation, the technologynode is likely not affected by subresolution patterning affectsto the same degree as a 90- or 65-nm process. Furthermore,by measuring subthreshold currents and reducing , we re-duce the DIBL effect and minimize any current variations dueto channel length variation. Additionally, oxide thickness is rel-atively well controlled and variation in this parameter is likelyto be more spatially smooth. We note that smaller device sizes,including any excluded by our ADC resolution screening proce-dure, would be expected to be even more susceptible to RDF; aninteresting result here is that RDF is discernable and dominateseven for larger device sizes.

E. Die-to-Die Correlation

Given the lack of any significant intra-die spatial correlation,inter-die correlation is only expected if the standard deviation ofthe mean shift between each die is considerably larger than thewithin-die standard deviation (i.e., ).Computing this requires the absolute for the reference deviceon each chip, which necessitates current measurements to deter-mine where the versus curve breaks from a straight lineon a semilog plot. However, due to the limited dynamic range



Fig. 8. Intra-die correlation versus distance and die-to-die pattern correlation.

Fig. 9. distribution and normal probability plot for a single die.

of the on-chip ADC, we were unable to measure currents signif-icantly larger than 600 nA, making it impossible to determinean absolute for each reference device. Nevertheless, we arestill able to compute correlations in the spatial variation patternsbetween arbitrary pairs of die. Once again, we choose a singledevice size to analyze and compute the correlation coefficient,

, between pairs of die using (10), where andare the of identical devices located at on

die and die , respectively, and , , , are the meansand standard deviations of of all devices of the given sizeon dies and , respectively. Fig. 8(b) shows the correlation co-efficient as a function of all pairwise combinations.All data points fall within the significance bounds indicatingno significant variation pattern similarity between pairs of dies.Larger device sizes show the same results:

(10)

The previous two subsections have shown that variation isboth random and spatially uncorrelated, implying that knowingthe variation between two devices gives no further informationabout two similarly spaced devices on the same chip or even the

same two devices on a different chip. This has powerful impli-cations for both circuit designers and the modeling community.

IV. DESIGN AND MODELING IMPLICATIONS

In order to determine the importance of the lack of correlationin variation, we must determine the sensitivity of a given cir-cuit or design to variation. For example, it is well known thatsubthreshold circuit designs are highly susceptible to varia-tion, while channel length variation has minor impact in com-parison. In general, computing circuit sensitivity to individualprocess parameters is not easily done analytically. However, wecan consider a simple inverter where the power-supply to the in-verter is scaled from subthreshold to well above to illustratethe differing circuit sensitivities.

A. Circuit Modeling

For a simple inverter operating above-threshold, the propa-gation delay for a falling transition can be modeled as in (11).However, when the inverter is operating subthreshold, (11) ismodified to (12):

(11)

(12)



Fig. 10. Circuit performance correlation as a function of .

where for modern processes and is a constantdetermined by the process technology. Given the correlation co-efficients for channel lengths and threshold voltages

between the NMOS transistors in two arbitrary in-verters, it should be possible to compute the correlation coeffi-cient for their propagation delays. In general, this is a difficultproblem to solve analytically, but Monte Carlo simulations pro-vide insight. To setup these simulations, we use the pa-rameter in Hspice to apply completely random variation inand we modify gate lengths in the spice deck using correlatedrandom variation of . This was done in accordancewith our results showing lack of correlation in and the spa-tial correlation results in from [9] to highlight the differingimpacts of correlated versus uncorrelated variation in differentcircuit operating regimes.

We easily see in Fig. 10(a) that the overall correlation containssome interesting characteristics. When , the cor-relation asymptotically grows toward . However, around

, the correlation falls precipitously, indicating thatthe gate overdrive is no longer sufficient to mask out RDF-dom-inated variation. Since (11) becomes less applicable when

, the computed , but below itsettles to an extremely weak correlation, indicative of the dom-inant role of in determining subthreshold current.

For simple logic gates, assuming channel length andvariation are independent, one can safely assume that

when . In contrast, in thesubthreshold region it is safe to assume dueto the lack of correlation in variation.

This result demonstrates the importance of modeling corre-lations in each device parameter individually: the correlation ofthe particular circuit output metric is, in general, a nonlinearfunction of the correlations in each device parameter. Further-more, the overall circuit performance correlation is highly de-pendent on circuit operating region and the circuit’s sensitivityto individual device parameters within the operating region. Forregions of operation where correlation is low or insignificant,methods for modeling variation as uncorrelated IID statistics areappropriate, using Monte Carlo or distribution propagation ap-proaches.

B. Circuit Design

Designers face many decisions in today’s complex circuits.Increased variation means that designers must now considerhow best to ensure robust circuit operation. One approach isto design the circuit to operate correctly given the range andcharacteristics of known or estimated device variations. A moreaggressive approach is to consider active variation sensing andcompensation strategies. The results of the previous sectionimply that the designer must carefully consider the operatingregion of the circuit when evaluating either robust design oractive compensation strategies to counteract variation.

In the above-threshold region where channel length variationdominates circuit performance variation, assuming that channellength variation is spatially correlated, variation sensors can beused to detect variation. Active compensation, such as back-bi-asing circuits, can then be used to counteract the detected vari-ation. Given high spatial correlation within a givenradius, only one such variation sensor and compensation circuitis required within this radius.

In contrast, subthreshold operation results in no significantspatial correlation due to or L variations. Additionally, Sec-tion III-C showed that the variance was not significantly relatedto distance. Consequently, a designer can only make use of thefact that the variance decreases with increasing device area, asincreasing the size of a device effectively averages out variationdue to Random Dopant Fluctuation. However, doing so resultsin negative power scaling due to increased total capacitance,and so there exists a trade-off between yield and power. In [23],the authors analyze the effect of increasing device width on theminimum energy point of subthreshold operation, showing thatup-sizing for a constant yield has a negative effect on the min-imum energy point. Another method of averaging out variationis to increase logic depth as in [24]. By increasing the numberof devices in a logic path, the variance of the propagation delayof the entire path decreases. This technique can prove useful indesigns where operating frequency is not the primary metric.

In ultra-dynamic voltage frequency scaling (UDVFS) sys-tems, such as those in low-power systems like mobile devicesor sensor networks, both subthreshold and above-threshold op-eration are used [25], [26]. Such systems often utilize replica



critical paths or variation sensors to determine the appropriatefrequency to operate at for a given power-supply voltage. Todetermine how correlated these replicas are to the actual paththey are monitoring while scaling , we performed MonteCarlo simulations with correlated channel length variation of aseven-stage ring-oscillator (RO) and a critical path of a 64-bitKogge–Stone (KS) adder. Fig. 10(b) shows the results of a 1000-point Monte Carlo simulation with 65-nm predictive technologymodels [27], where , ,

mV m, and .The overall correlation in delay between the two paths is

for V V. The reason this is greaterthan is that the load capacitance of the following stageis also correlated as a result of correlated variation in channellength, thereby increasing the overall correlation. In the regionof V V, the overall correlation between mon-itor and circuit decreases quickly, indicating that performance ofthe monitor/replica is no longer indicative of the performance ofthe critical path and should not be used to determine correct op-erating frequency unless a large guard-band is applied. Such aguard-band would undoubtedly subtract away from energy effi-ciencies achieved by moving to lower supply voltages. A morerobust method of controlling operating frequency in such sys-tems is to detect logic errors in potential critical paths and slowdown the frequency until timing errors are no longer detected[28], [29].

V. CONCLUSION

We have implemented a test-chip to analyze spatial correla-tion of variation. Analysis of the variation data from thistest-chip shows that there is neither intra-die spatial correlationnor inter-die correlation in the variation pattern between chips.Using the gathered statistics of variation, we have shown thatmodeling of correlation in digital static timing is highly depen-dent on the circuit’s region of operation, with timing correlationbeing approximately equal to channel length correlation when

and approximately zero in the subthreshold regime.To accurately model the derived correlation in timing character-istics for all regions of operation, it is necessary to model thecorrelation of both channel length and variation indepen-dently. We have also shown that the design techniques neces-sary to ensure circuit robustness are equally dependent on thecircuit’s region of operation.

ACKNOWLEDGMENT

The authors would also like to thank D. Lim, K. Balakrishnan,and N. Verma for their aid in chip testing and invaluable discus-sions regarding data analysis and implications and P. Hollowayand National Semiconductor for chip fabrication.

REFERENCES

[1] S. R. Nassif, “Design for varaibility in DSM technologies,” in Proc.Int. Symp. Quality Electronic Design (ISQED), 2000, pp. 451–454.

[2] X.-W. Lin, “Design and process variability—the sources and mecha-nisms,” DAC Tutotrial—Practical Aspects of Coping with Variability:An Electrical View, 2006.

[3] M. Orshansky, S. Nassif, and D. Boning, Design for Manufactura-bility and Statistical Design: A Constructive Approach. New York:Springer, 2008.

[4] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K.Gala, and R. Panda, “Statistical delay computation considering spatialcorrelations,” Asia Pacific - Design Automation Conf., pp. 271–276,Jan. 2003.

[5] H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spa-tial correlations,” IEEE Tran. Computer-Aided Design Integrated Cir-cuits Syst., vol. 24, no. 9, pp. 1467–1482, Sep. 2005.

[6] A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysisfor intra-die process variations with spatial correlations,” in Proc. Int.Conf. Computer-Aided Design, Nov. 2003, pp. 200–207.

[7] Q. Fu, W.-S. Luk, J. Tao, C. Yan, and X. Zeng, “Characterizingintra-die spatial correlation using spectral density method,” in Proc.Int. Symp. Quality Electronic Design (ISQED), Mar. 2008, pp.718–723.

[8] J. Xiong, V. Zolotov, and L. He, “Robust extraction of spatial cor-relation,” IEEE Trans. Computer-Aided Design, vol. 26, no. 4, pp.619–631, Apr. 2007.

[9] P. Freidberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos,“Modeling within-die spatial correlation effects for process-designco-optimization,” in Proc. Int. Symp. Quality Electronic Design(ISQED), Mar. 2005, pp. 516–521.

[10] K. Agarwal, F. Liu, C. McDowell, S. Nassif, K. Nowka, M. Palmer, D.Acharyya, and J. Plusquellic, “A test structure for characterizing localdevice mismatches,” in Symp. VLSI Circuits, 2006, pp. 67–68.

[11] K. Agarwal, J. Hayes, and S. Nassif, “Fast characterization of thresholdvoltage fluctuation in MOS devices,” IEEE Trans. Semicond. Manuf.,vol. 21, no. 4, pp. 526–533, Nov. 2008.

[12] R. Rao, K. Jenkins, and J.-J. Kim, “A completely digital on-chip cir-cuit for local-random-variability measurement,” in Proc. of the Inter-national Solid-State Circuits Conf., Feb. 2008, pp. 412–623.

[13] S. Mukhopadhyay, K. Kim, K. Jenkins, C.-T. Chuang, and K. Roy,“Statistical characterization and on-chip measurement methods forlocal random variability of a process using sense-amplifier-based teststructure,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 400–611.

[14] T. Fischer, E. Amirante, P. Huber, T. Nirschl, A. Olbrich, M. Oster-mayr, and D. Schmitt-Landsiedel, “Analysis of read current and writetrip voltage variability from a 1-MB SRAM test structure,” IEEE Tran.Semicond. Manuf., vol. 21, no. 4, pp. 534–541, Nov. 2008.

[15] V. Wang and K. Shepard, “On-chip transistor characterisation arraysfor variability analysis,” Electron. Lett., vol. 43, no. 15, pp. 806–807,Jul. 2007.

[16] S. Sabade and D. Walker, “Estimation of fault-free leakage currentusing wafer-level spatial information,” IEEE Trans. Very Large ScaleIntegrat. (VLSI) Syst., vol. 14, no. 1, pp. 91–94, Jan. 2006.

[17] N. Drego, A. Chandrakasan, and D. Boning, “A test-structure to effi-ciently study threshold-voltage variation in large MOSFET arrays,” inProc. Int. Symp. Quality Electronic Design (ISQED), Mar. 2007, pp.281–286.

[18] J. A. del, Integrated Microelectronic Devices. Englewood Cliffs, NJ:Prentice Hall, 2007.

[19] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. Ko, andY. Cheng, “Threshold voltage model for deep-submicrometer MOS-FETs,” IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86–95, Jan.1993.

[20] HSPICE Simulation and Analysis User Guide, Synopsis, 2007.[21] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New

York: Wiley, 1997.[22] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers,

“Matching properties of MOS transistors,” IEEE J. Solid-State Cir-cuits, vol. 24, no. 5, pp. 1433–1440, Oct. 1989.

[23] J. Kwong and A. Chandrakasan, “Variation-driven device sizing forminimum energy subthreshold circuits,” in Proc. International Sympo-sium on Low Power Electronics and Design (ISLPED), 2006, pp. 8–13.

[24] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “Analysis and mit-igation of variability in subthreshold design,” in Proc. InternationalSymposium on Low Power Electronics and Design (ISLPED), 2005,pp. 20–25.

[25] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, “The limit of dy-namic voltage scaling and insomniac dynamic voltage scaling,” IEEETrans. Very Large Scale Integrat. (VLSI) Syst., vol. 13, no. 11, pp.1239–1252, Nov. 2005.

[26] B. Calhoun and A. Chandraksan, “Ultra-dynamic voltage scaling(UDVS) using sub-threshold operation and local voltage dithering,”IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238–245, Jan. 2006.

[27] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New para-digm of predictive MOSFET and interconnect modeling for early cir-cuit design,” in Custom Integrated Circuits Conf., 2000, pp. 201–204.



[28] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner,and T. Mudge, “Self-tuning DVS processor using delay-error detec-tion and correction,” IEEE J.Solid-State Circuits, vol. 41, no. 4, pp.792–804, Apr. 2006.

[29] D. Blaauw, S. Kalaiselvan, K. Lai, W.-H. Ma, S. Pant, C. Tokunaga, S.Das, and D. Bull, “Razor II: In situ error detection and correction forPVT and SER tolerance,” in Proc. Int. Solid-State Circuits Conf., Feb.2008, pp. 400–401.

Nigel Drego (S’03) received the M.S. degree fromthe Massachusetts Institute of Technology (MIT),Cambridge, in 2003. He is currently working towardthe Ph.D. degree in the Electrical Engineering andComputer Science Department at MIT.

From 2003 to 2005, he was a Design Engineer atIntel Corporation, Santa Clara, CA, where he was in-volved in the design of a high-performance micropro-cessor. His current research interests are mitigatingthe impact of semiconductor process variation in dig-ital circuits and systems.

Anantha Chandrakasan (M’95–SM’01–F’04)received the B.S, M.S., and Ph.D. degrees in elec-trical engineering and computer sciences from theUniversity of California, Berkeley, in 1989, 1990,and 1994, respectively.

Since September 1994, he has been with theMassachusetts Institute of Technology, Cambridge,where he is currently the Joseph F. and Nancy P.Keithley Professor of Electrical Engineering. He isthe Director of the MIT Microsystems TechnologyLaboratories. He is a co-author of Low Power

Digital CMOS Design (Kluwer, 1995), Digital Integrated Circuits (PearsonPrentice-Hall, 2003, 2nd ed.), and Sub-Threshold Design for Ultra-Low PowerSystems (Springer, 2006). He is also a co-editor of Low Power CMOS Design(IEEE Press, 1998), Design of High-Performance Microprocessor Circuits

(IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer,2005). His research interests include low-power digital integrated circuit de-sign, wireless microsensors, ultra-wideband radios, and emerging technologies.

Dr. Chandrakasan has been a co-recipient of several awards, including the1993 IEEE Communications Society’s Best Tutorial Paper Award, the IEEEElectron Devices Society’s 1997 Paul Rappaport Award for the Best Paper inan EDS publication during 1997, the 1999 DAC Design Contest Award, the2004 DAC/ISSCC Student Design Contest Award, and the ISSCC 2007 Beat-rice Winner Award for Editorial Excellence. He has served as a technical pro-gram co-chair for the 1997 International Symposium on Low Power Electronicsand Design (ISLPED), VLSI Design ’98, and the 1998 IEEE Workshop onSignal Processing Systems. He was the Signal Processing Sub-committee Chairfor ISSCC 1999–2001, the Program Vice-Chair for ISSCC 2002, the ProgramChair for ISSCC 2003, and the Technology Directions Sub-committee Chairfor ISSCC 2004–2007. He was an Associate Editor for the IEEE JOURNAL OFSOLID-STATE CIRCUITS from 1998 to 2001. He served on the SSCS AdCom from2000 to 2007 and he was the meetings committee chair from 2004 to 2007. Heis the Technology Directions Chair for ISSCC 2008.

Duane Boning (S’90–M’91–SM’00–F’05) receivedthe B.S., M.S., and Ph.D. degrees from the Massa-chusetts Institute of Technology (MIT), Cambridge.

Currently, he is a Professor of electrical engi-neering and computer science and Associate Headfor Electrical Engineering in the Electrical Engi-neering and Computer Science Department, MIT.His research focus is variation modeling, control, andenvironmental issues in semiconductor and MEMSmanufacturing with emphasis on chemical–mechan-ical polishing and plasma etch, and CAD tools for

statistical process, device, and circuit design. He has written over 120 papersand conference presentations in these areas of research. From 1991 to 1993,he was a Member of the Technical Staff at Texas Instruments, Dallas, TX.He served as the Associate Director for the MIT Microsystems TechnologyLaboratories from 1998 to 2004.

Dr. Boning is the Editor-in-Chief of the IEEE TRANSACTIONS ONSEMICONDUCTOR MANUFACTURING.


Documents

IEEE TRANSACTIONS ON SEMICONDUCTOR · PDF filetest-structure to analyze the magnitude of spatial correlation of ... Many steps within the manufacturing ... of characterization of the