IEEE TRANSACTIONS ON MICROWAVE THEORY AND …ntur.lib.ntu.edu.tw/bitstream/246246/148460/1/13.pdf · IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 10, OCTOBER

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 10, OCTOBER 2007 2075

35–65-GHz CMOS Broadband Modulator andDemodulator With Sub-Harmonic Pumping

for MMW Wireless Gigabit ApplicationsJeng-Han Tsai, Student Member, IEEE, and Tian-Wei Huang, Senior Member, IEEE

Abstract—Sub-harmonic modulator and demodulator are pre-sented in this paper using 0.13- m standard CMOS technologyfor millimeter-wave (MMW) wireless gigabit direct-conversionsystems. To overcome the main problem of local oscillator (LO)leakage in direct-conversion systems, the sub-harmonicallypumped scheme is selected in this mixer design. An embeddedfour-way quadrature divider is utilized in the sub-harmonicGilbert-cell design to generate quadrature-phases LO signalsat MMW frequency. For broadband applications, a broadbandmatching design formula is provided in this paper to extend theoperational frequency range from 35 to 65 GHz. To improve theflatness of conversion loss at high frequency, high-impedance com-pensation lines are incorporated between the transconductancestage and LO switching quad of the Gilbert-cell mixer to com-pensate the parasitic capacitance. The sub-harmonic modulatorand demodulator exhibit 6 1.5 dB and 7.5 1.5 dB measuredconversion loss, respectively, from 35 to 65 GHz. For MMWwireless gigabit applications, the gigabit modulation signal test issuccessfully performed through the direct-conversion system inthis paper. To our knowledge, this is the first demonstration of theMMW CMOS sub-harmonic modulator and demodulator thatfeature broadband and gigabit applications.

Index Terms—CMOS, demodulator, direct conversion, mil-limeter wave (MMW), modulator, sub-harmonically pumped.

I. INTRODUCTION

RECENTLY, the Federal Communications Commission(FCC) announced 7 GHz of unlicensed band in mil-

limeter-wave (MMW) frequency bands from 57 to 64 GHz [1].The FCC allocation provides the possibility of the wirelessgigabit communication services, such as wireless personalarea networks (WPANs) [2], wireless gigabit Ethernet [3], andpoint-to-multipoint MMW fiber-radio communication systems[4]. Furthermore, these 60-GHz short-range links provideextra benefits of security, spatial isolation, and frequencyreuse, which results from the significant oxygen absorptionat kilometer range [2]. To meet the MMW market demands,many researchers have developed highly integrated MMWmonolithic integrated circuits. In the past, this research wasdominated by III–V semiconductors. Due to the possibility

Manuscript received February 24, 2007; revised May 29, 2007. This workwas supported by the National Science Council of Taiwan under Grant NSC96-2219-E-002-021, Grant NSC 95-2219-E-002-011, Grant NSC 95-2221-E-002-084-MY2, and Grant NSC 93-2752-E-002-003-PAE.

The authors are with the Department of Electrical Engineering and GraduateInstitute of Communication Engineering, National Taiwan University, Taipei,106 Taiwan, R.O.C. (e-mail: [email protected]).

Digital Object Identifier 10.1109/TMTT.2007.905497

of low-cost silicon and back-end integration, modern CMOStechnology with downscaling of transistor dimensions is aninteresting alternative for MMW applications. Today 0.13- mbulk CMOS technology is capable of high-gain amplificationsin the 60 GHz [5].

Direct-conversion architecture with advantages of minimalhardware, no image frequency, and wider bandwidths [6] is at-tractive for broadband MMW applications. Therefore, passivede-modulator and modulator have been reported in various pro-cesses [7]–[10] for MMW direct-conversion systems, even gi-gabit data rate. However, the main problem of local oscillator(LO) leakage must be considered carefully when designing di-rect conversion transceivers [6]. To minimize the problem, thesub-harmonic pumping technique whose LO frequency is one-half of the desired RF frequency is considered as a potentialsolution [11]–[15]. In addition, using relatively low LO fre-quency can decrease the design challenge of a high-power andlow phase-noise LO in MMW frequencies [12].

The mixer is a critical component in the demodulator andmodulator designs that translates the RF signals to and frombaseband signals. Traditionally, mixers using passive topologiesin the MMW regime have high conversion loss and large chipsize due to the quarter-wave length matching stubs and baluns[16]. Now the high-performance CMOS devices make it pos-sible to consider the fundamental Gilbert-cell mixer for low con-version loss and compact die size in MMW [17]. However, theCMOS sub-harmonic Gilbert-cell mixer has not been demon-strated in MMW for the following reasons.

1) The switching quad of the sub-harmonic Gilbert-cellmixer consists of four parallel connected transistors intro-duce a larger parasitic capacitance than the fundamentalGilbert-cell mixer, which limits the operation frequenciesand bandwidth in the MMW regime.

2) The lack of accurate quadrature-phase LO signals gen-erator in the MMW limits the operation frequencies ofsub-harmonic Gilbert-cell mixers.

Furthermore, the MMW CMOS Gilbert-cell-based demodula-tors and modulators with gigabit direct-conversion capabilitieshave not been demonstrated.

This paper presents an MMW broadband sub-harmonic mod-ulator and demodulator using 0.13- m standard CMOS tech-nology for MMW direct-conversion systems. The sub-harmon-ically pumped technique is selected to minimize the LO leakageproblem. For broadband applications, a broadband matching de-sign formula is provided to extend the operational frequencyrange. To compensate the parasitic capacitance of the CMOS

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2076 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 10, OCTOBER 2007

Fig. 1. Block diagrams of the CMOS broadband sub-harmonically pumpedmodulator and demodulator.

transistor, a high-impedance compensation line is incorporatedbetween the transconductance stage and switching quad to forma third-order Butterworth LC ladder network. In addition, anMMW four-way quadrature divider using a 90 coupler and180 balun have been implemented in the CMOS process to pro-vide equal amplitude and quadrature-phases LO signals for thesub-harmonically pumped modulator and demodulator. Finally,the experimental results show the MMW CMOS sub-harmonicmodulator and demodulator MMICs feature good direct-conver-sion quality up to the gigabit data rate.

II. OPERATION PRINCIPLE

The direct-conversion architecture is a promising approachfor single-chip transceivers for the following reasons. First, theelimination of the IF circuitry reduces design complexity andminimal hardware. Second, with zero IF, there is no image fre-quency. Third, the radio channels have wide bandwidths, whichmake it more suitable for high data-rate systems. However, awell-known problem is the LO leakage because of poor reverseisolation through the mixer. As an upconverter, the LO leakageshould be minimized since an unwanted carrier signal at the RFoutput can degrade the modulation quality. As a downconverter,the LO leakage from the receiver into the antenna becomes anin-band interferer to other nearby receivers tuned to the sameband. In addition, LO leakage self-mixing to dc through themixer cause a more serious dc offset problem in receiver. Tominimize these problems, the sub-harmonically pumped tech-nique is considered as a potential solution. With sub-harmonicpumping, the fundamental LO frequency is one-half of the de-sired RF frequency, therefore, the fundamental component ofLO leakage does not appear in the concerned signal frequencybands [13]–[15]. In fact, the LO leakage does not completelyeliminate due to the imperfections in the circuit mismatch. How-ever, the sub-harmonically pumped technique is beneficial to re-duce LO leakage in the modulator and dc offset in the demodu-lator.

A block diagram of the sub-harmonic modulator and demod-ulator are shown in Fig. 1. The sub-harmonic modulator consistsof a 90 broadside coupler, a Wilkinson power divider, and twosub-harmonically pumped mixers. The Wilkinson power divideris used to provide good isolation between the input ports of twomixers. The broadside coupler provides a 90 phase shifter at the

RF port. The mixers can perform the modulation of the LO withthe baseband in-phase ( ) and quadrature ( ) modulating sig-nals. Both mixed signals are combined at the output to providea composite modulated signal. All signals are fully differential,except for the RF and LO input signals. Using the following no-tation for the LO, in-phase ( ) and quadrature ( ) signals:

(1a)

(1b)

(1c)

the mixed signals and are

(2a)

(2b)

after the mixed signals and pass through the broadsidecoupler, the modulated signal is given by

(3)

However, due to the amplitude and phase imbalance of practicalcircuit implementation, complete suppression does not occur[6].

The block diagram of the modulator shown in Fig. 1 can alsobe operated as a demodulator with the replacement of downcon-version mixers. Modulated signals entering the 90 phase shifterfrom the RF port are separated into two equal amplitude com-ponents with 90 phase shift and mix with the sub-harmonic LOby the sub-harmonic mixer to produce baseband signals.

III. CIRCUIT DESIGN

The mixer is a critical component in the demodulator andmodulator designs that translates the RF signals to and frombaseband signals. Circuit design of the broadband sub-har-monic direct up/downconversion mixer is described here. Thequality factors of the matching networks [18] are designed tohave a low value for broadband impedance matching. Althougha higher quality factor of the matching networks has betterconversion loss, the circuits become more narrowband and sen-sitive to process variations. The sub-harmonic modulator anddemodulator are fabricated in a 0.13- m 1P8M bulk CMOSprocess. This process provides a single poly layer for thegates of the MOS and eight metal layers for inter-connection.Using optimized CMOS topology and deep n-well (DNW),this topology provides an of 85 GHz and of 90 GHz atmaximum-transconductance bias. The transmission lines wereimplemented using thin-film microstrip (TFMS) lines [5]. TheTFMS consists of metal 1 (bottom layer) in the 1P8M CMOSprocess as the ground plane and metal 8 (top layer) as themicrostrip signal line with the thick SiO layer as the substrate.The TFMS can be meandered in a very compact area to reducethe circuit size without suffering the coupling effect. In this0.13- m CMOS process, the TFMS linewidth of 50- charac-teristic impedance is approximately 10 m. The circuits weresimulated with Agilent’s Advanced Design System (ADS).


TSAI AND HUANG: 35–65-GHz CMOS BROADBAND MODULATOR AND DEMODULATOR WITH SUB-HARMONIC PUMPING 2077

Fig. 2. Schematic of the 35–65-GHz CMOS sub-harmonic direct upconversionGilbert-cell mixer.

The passive components include the discontinuities of theTFMS lines, inductors, and capacitors and were simulated bya full-wave electromagnetic (EM) simulator (Sonnet software)[19].

A. Broadband Sub-Harmonic Direct Upconversion Mixer

The sub-harmonically pumped mixing in a direct upcon-version mixer is selected in this design. Since the LO leakageof the sub-harmonic mixer does not appear in the RF bandand the 2 LO leakage of the sub-harmonic mixer is muchsmaller than the LO leakage of the fundamental mixer, thesignal distortion due to large LO leakage to the RF port can besignificantly reduced [13]–[15]. The schematic of the broad-band sub-harmonic direct upconversion Gilbert-cell mixer isshowed in Fig. 2. The mixer consists of the several passive andactive components. The Gilbert-cell configuration is selectedfor its double-balanced implementation, which offers high spursuppression in a very compact die size. The main transcon-ductor, which converts the baseband input signal to outputcurrent, is composed of nMOS and (144 m/0.13

m, which is a 72-finger device with 2 m unit finger length).The sub-harmonic LO switching quad consists of four parallelconnected nMOS pairs, shown as – (36 m/0.13 m).Each transistors of the LO switching quad turn on and offalternatively during one period of the applied LO signal, thus,the RF signal can be switched on every quarter cycle of the LOsignal, which creates an effective 2 LO signal. In order to min-imize the noise of the active mixer, the bias current of the LOswitching quad should be small enough to lower the magnitudeof noise pulses. Therefore, a current bleeding circuit, which iscomposed of (400 ) and (400 ) is incorporated tobleed the drain current flowing into main transconductors andreduce the bias current of the LO switching quad [20]. The biascurrent of the transconductor stage is determined by a currentmirror source, which is composed of (72 m/0.13 m),

Fig. 3. Equivalent circuit of output matching network of the sub-harmonic di-rect upconversion Gilbert-cell mixer.

(12 m/0.13 m), and (2000 ). A single mixer drawstotal 11.5-mA dc current from a 3.3-V supply voltage. There is4-mA dc current bled through and , respectively, from a3.3-V supply voltage.

To achieve broadband frequency response at the RF outputport, the quality factor of the output impedance matching net-work is kept low to cover the 35–65-GHz band. The outputmatching networks consist of a shunt inductor ( or )and a series dc blocking capacitor ( or ). One terminalof the inductor is connected to with a bypass capac-itor . For low quality factor output impedance matching anal-ysis, each output side equivalent circuit of the double-balancedsub-harmonic mixer is shown in Fig. 3. and are resis-tance and capacitance looking into a drain of LO switching quadtransistors. The dc-blocking capacitor (2 pF) is ac short. Theload impedance is 50 . The inductor at each outputside along with its equivalent series resistance (ESR) aretransformed to a parallel combination of and

[18] for parallel RLC resonant circuit analysis,where the quality factor of the drain inductor is given by

(4)

The quality factor of the parallel RLC resonant circuitshown in Fig. 3 at the resonant frequency ( ) is given by

(5)

To match the impedance at the output port,should be equal to of 50 . From the definition of thequality factor [18], the quality factor of outputmatching network was determined to be 1.5 in thisstudy to cover the 35–65-GHz bandwidth. The inductorneeds to be 0.055 nH along with its ESR of 1.3 . Finally,the simulation helps in choosing the device size of the LOswitching quad transistors.

B. Broadband Sub-Harmonic Direct Downconversion Mixer

Most direct conversion receivers suffer degradation ofsignal-to-noise ratio (SNR) performance due to the problems ofLO self-mixing. To mitigates the LO self-mixing problem, thesub-harmonically pumped mixing scheme is selected to sepa-rate the fundamental LO and RF frequency band. The schematic



Fig. 4. Schematic of the 35–65-GHz CMOS sub-harmonic direct downconver-sion Gilbert-cell mixer.

Fig. 5. Equivalent circuit of input matching network of the sub-harmonic directdownconversion Gilbert-cell mixer.

of the sub-harmonic double-balanced direct downconversionGilbert-cell mixer is shown in Fig. 4. The main transcon-ductor, which converts RF input signal to output current, iscomposed of nMOS and (32 m/0.13 m). The biascurrent of the transconductor stage is determined by a currentmirror source, which is composed of (72 m/0.13 m),

(12 m/0.13 m), and (2400 ). The sub-harmonicLO switching quad consists of four parallel connected nMOSpairs, shown as – (12 m/0.13 m). A current bleedingcircuit, which is composed of (400 ) and (400 ),are incorporated to bleed the drain current flowing into maintransconductors. With this current bleeding circuit, the draincurrent of the input transistors and can be partiallysupplied through it, which reduces the drain current of theswitching quad transistors and the voltage drop of load resistors( and ). Therefore, the value of these load resistors,and (1000 ), can be increased, thus the voltage conversiongain is raised. A source–follower buffer for baseband activematching is used. By selecting the transistor size of(72 m/0.13 m) and (72 m/0.13 m), the basebandmodulation bandwidth of the downconversion mixer can bewidened up to 1 GHz for gigabit applications.

For broadband RF input impedance matching, the qualityfactor of the input matching network is also kept low to coverthe 35–65-GHz band. As shown in Figs. 4 and 5, gate inductors

( or ) and source inductors ( or ) are usedto transfer the input impedance to of 50 . The ESR of the

Fig. 6. (a) Small-signal model of the transconductor stage with the loadingeffect of the LO switching quad. (b) High-impedance compensation line is in-corporated as inductances between transconductance stage and switching quad.

inductors and are and , respectively. The effect ofparasitic shunt capacitances of the inductors are too small tobe reflected in calculation of input impedance. An expression ofthe impedance looking into the gate of transistor pairsor through the inductor can be written as follow [21]:

(6)

where is the parasitic capacitor of the transistor or .The quality factor ( ) of the series RLC resonant circuitshown in Fig. 5 at the resonant frequency ( ) including thesource impedance is given by [18]

(7)

The quality factor of output matching network was alsodetermined to be 1.5 to cover 35–65 GHz. Once is set, thesize of transistor and (32 m/0.13 m) are determinedby (7). Finally, the simulation helps in choosing the values ofthe components. The selected size of transistor and is a16-finger device with a 2- m unit finger length. Both and

are minimum length devices (0.13 m). of the transistoror is 0.031 pF in this study. is 0.42 nH with of

8 and nH with of 1.2 .The parasitic capacitance of CMOS technology results in

degradation of the performance at a high operation frequency.To compensate the parasitic capacitance and improve theconversion loss at high frequency, a compensation line asinductance is incorporated between transconductance stage andswitching quad. Fig. 6(a) shows the small-signal model of thetransconductor stage with the loading effect of the followingLO switching quad stage. and are the parasitic resistanceand capacitance, respectively, of the transconductor stagetransistor, while and are the parasitics of the LOswitching quad. The gain-bandwidth product (GBW) of thistransconductor stage is given by

(8)

where . As can be observed, large parasitic capac-itances limit the GBW of the Gilbert-cell mixer. The switching



Fig. 7. Simulated conversion loss versus RF frequency of the sub-harmonicdownconversion Gilbert-cell mixer for different compensation-line lengths.

quad of the sub-harmonic Gilbert-cell mixer especially consistsof four parallel connected nMOS pairs, which introduce a largerparasitic capacitance than a fundamental Gilbert-cell mixer. Toovercome the problem, a high-impedance compensation line, asshown in Figs. 4 and 6(b), is incorporated as an inductance be-tween the transconductance stage and switching quad to com-pensate and . The parasitic capacitance of the transistoris combined with the inductance of the compensation line toform a third-order Butterworth LC ladder network in Fig. 6(b)[22]. The network absorbs the parasitic capacitance at reso-nant frequency. Therefore, the use of a series inductor betweenthe transconductor and the switching transistors can extend thebandwidth above the limit in (8). In general, it is complicated tocalculate the values of the high-impedance compensation linefor optimizing the LC ladder network directly. Instead, the simu-lation helps in optimizing choosing the values of the compensa-tion-line lengths. The simulated conversion loss of the completemixer is shown in Fig. 7 with various compensation-line lengthsfrom 0 to 400 m and width of 2.5 m. A significant improve-ment can be achieved for the flatness of conversion loss overfrequencies by a proper selection of compensation-line length.Without the compensation line, the conversion loss will slopedown from 6 to 11 dB when the RF and LO frequency sweepsfrom 35 to 65 GHz. For a flat conversion loss over frequency,the compensation-line length of 300 m is selected, the conver-sion loss will slope down from 5 to 6 dB when the RF frequencysweeps from 35 to 65 GHz.

C. MMW Quadrature-Phases LO Generation Schemein the CMOS Process

The phase-shifting network plays an important role in thegeneration of equal amplitude and quadrature-phases LO sig-nals for the sub-harmonically pumped Gilbert-cell mixer. How-ever, it is difficult to generate the accurate quadrature-phases LOby using an external balanced phase shifter or surface mountbalun, particularly in the MMW frequency. Furthermore, usinga conventional embedded RC poly-phase filter at the LO signalpath attenuates the LO power significantly in the MMW fre-quency. An additional differential LO buffer amplifiers should

Fig. 8. Proposed MMW LO four-way quadrature divider.

be added between the poly-phase filter and mixer in order tocompensate the losses [23].

For the MMW sub-harmonic Gilbert-cell mixer, an embeddedLO four-way quadrature divider using a 90 coupler and 180baluns in the CMOS technology is proposed. The structure andlayout of the LO four-way quadrature divider is shown in Fig. 8.A Marchand-type transformer is used as 180 baluns due to itsexcellent amplitude/phase match and broadband response [10],[24]. Two coupled lines in the Marchand balun are constructedof broadside coupled lines using metal layers 7 and 8 in this0.13- m CMOS process. These two coupled lines are woundinto two coils, shown in Fig. 8, with a width and gap both of3 m. Port 1 of the 180 balun was connected through two coilsto open circuit, and ports 2 and port 3 were connected fromground to coil. At the operation frequency, the signal of port1 will couple to the top side coils, and port 2 and port 3 will be180 out-of-phase.

For the 90 coupler of the four-way quadrature divider, abroadside coupler with a tight coupling factor of 3 dB is alsoimplemented using the TFMS structure [10]. It is constructedwith two strip lines using different metal layers, i.e., metal layer7 and 8. Since the gap between the edge coupler is too small tobe fabricated for the required coupling, metal layer 8 and 7 areused for the coupled lines of the broadside coupler due to thethick dielectric layer. To obtain the appropriate coupling, an ad-ditional offset distance of 2 m between metal 7 and 8 is added.The linewidth of the coupled line is 4 m. Its size can be reducedby using meander-like layout. The 90 coupler and 180 balunsare both calculated using the full-wave EM simulator (Sonnetsoftware) [19].

IV. EXPERIMENTAL RESULTS

The microphotographs of the modulator and demodulator areshown in Figs. 9 and 10. Overall die size of the modulator anddemodulator are 0.98 mm 0.8 mm and 1 mm 1 mm, respec-tively. The MMIC are tested via on-wafer probing. The mea-surement results are shown here.

A. Modulator Characteristics

The key performances of the modulator are suppression, con-version loss, and intermodulation. Fig. 11 shows the measured



Fig. 9. Chip photograph of the CMOS sub-harmonic modulator with chip sizeof 0.98 mm� 0.8 mm.

Fig. 10. Chip photograph of the CMOS sub-harmonic demodulator with chipsize of 1.0 mm� 1.0 mm.

output spectrum of the CMOS sub-harmonic IQ modulator withan RF frequency of 60 GHz, an LO frequency of 30 GHz, and abaseband frequency of 5 MHz, where the lower sideband (LSB)is the desired signal and the upper sideband (USB) is the imagesignal. The measured output power of the modulator signal is

19 dBm with the optimal LO drive power of 7 dBm and base-band input of 14 dBm. The measured USB suppression is

24 dBc, which indicates an amplitude error is within 0.6 dBand a phase error is within 6 [6], [10]. The measured 2 LOsuppression is 27 dBc, referring to the desired output power.The LO driver power is 7 dBm at 30 GHz and the 2 LOleakage power is 45.7 dBm, as shown in Fig. 11. Therefore,the 2 LO to RF port isolation (LO leakage) is 52.7 dB. Thethird-order intermodulation ( ) components are lessthan 31 dBc and the second-order intermodulation (

Fig. 11. Measured output spectrum of the sub-harmonic IQ modulator with an2 � LO frequency of 60 GHz and a baseband frequency of 5 MHz.

Fig. 12. Simulated and measured conversion loss and USB suppression versusthe RF frequency from 20 to 70 GHz for the sub-harmonic IQ modulator.

) components are less than 40 dBc referring to the de-sired output power.

The simulated and measured conversion loss and USBsuppression of the IQ modulator from 20 to 70 GHz is plottedin Fig. 12. The measured conversion-loss results agree wellwith the simulated results, which demonstrate the conversionloss of 6 1.5 dB from 35 to 65 GHz. The measured USBsuppression is better than 20 dBc from 39 to 70 GHz. Inaddition, the USB suppression has the best performance,i.e., 30 dBc, from 42 to 45 GHz due to the low-imbalance(amplitude imbalance 0.5 dB and phase imbalance 3 )characteristics of the RF 90 broadside coupler. The simulatedand measured 2 LO suppression of the modulator from 20 to70 GHz is plotted in Fig. 13. The measured 2 LO suppressionis better than 24 dBc from 30 to 65 GHz. The measuredintermodulation ( and ) of themodulator from 20 to 70 GHz is also plotted in Fig. 13. Ascan be observed, the third- and second-order intermodulationare better than 28 dBc and 40 dBc, respectively, from 35to 65 GHz. The measured output is 19 dBm and the



Fig. 13. Simulated and measured 2 �LO suppression and measured intermod-ulation versus the RF frequency from 20 to 70 GHz for the sub-harmonic IQmodulator.

Fig. 14. Block diagram of the MMW vector signal measurement system forthe MMW sub-harmonic modulator.

total dc power consumption of the sub-harmonic modulator is75.9 mW.

To verify the high data rates digital modulation quality ofthe sub-harmonic IQ modulator, the MMW vector signal mea-surement system has been set up. The block diagram of thevector signal measurement system is plotted in Fig. 14. Thebaseband IQ sources are generated using Agilent’s ADS soft-ware and downloaded into an arbitrary waveform generator (Ag-ilent E4438C). The baseband IQ signals are fed into our modu-lator MMIC. The LO source of the modulator is provided by thesignal generator (Agilent E8247C). The output spectrum can beobserved by using a spectrum analyzer (Agilent E4448A). Thespectrum analyzer is also used for high-quality downconversionof the output signal to an IF (70 MHz). This 70-MHz IF signal isfed into a vector signal analyzer (Agilent VSA 89601A) for theanalysis of the digital modulation quality. The baseband overallinput power, including I , I , Q , and Q , is 14 dBm. At a2 LO frequency of 60 GHz, the sub-harmonic IQ modulator isevaluated by a quadrature phase-shift keying (QPSK) modula-tion with a data rate of 20 Ms/s. The measured output spectrumof the IQ modulator is plotted in Fig. 15, which demonstrateda channel power of higher than 20 dBm with a channel band-width of 20 MHz and an adjacent channel power ratio (ACPR)of better than 25 dBc. The measured constellation diagram ofthe IQ modulator at 60 GHz is plotted in Fig. 16. The points

Fig. 15. Measured output spectrum of the sub-harmonic IQ modulator at60 GHz with a 20-Ms/s QPSK modulation; the channel power is approximately�20 dBm with a channel bandwidth of 20 MHz.

Fig. 16. Measured constellation diagram of the sub-harmonic IQ modulator at60 GHz with a 20-Ms/s QPSK modulation.

Fig. 17. Measured BPSK output spectrum of the sub-harmonic modulator at60 GHz with 0.2-, 0.5, and 1.0-Gb/s data rates in PRBS.

in the QPSK constellation can be spread out uniformly into a“square.” The measured error vector magnitude (EVM) of theQPSK modulation is within 6%. For wideband applications, thepseudorandom bit stream (PRBS) with 0.2-, 0.5-, and 1.0-Gb/sdata rates is fed in to the sub-harmonic modulator. The dif-ferential baseband signals are generated from a pattern gener-ator (Anritsu MP1763C), and the voltage swing of the base-band signal is 0.5 V. The measured binary phase-shift keying(BPSK) output spectrum at 60 GHz is plotted in Fig. 17 withgood LO suppression. The spectrum is spread out due to theunfiltered baseband signals, resulting in a sinc-like spectrum.



TABLE ICOMPARISON OF MODULATOR IN VARIOUS TECHNOLOGIES AND TOPOLOGIES

Fig. 18. Block diagram of the MMW measurement system for the MMW sub-harmonic demodulator.

Table I is the comparison of the previously reported modulatorin various technologies and topologies. Our CMOS modulatorformed by the sub-harmonic double-balanced Gilbert-cell mixerdemonstrates smallest conversion loss and best 2 LO to RF portisolation with a compact chip size.

B. Demodulator Characteristics

The common set of specifications for the direct downconver-sion demodulator are the conversion loss, intermodulation dis-tortion, 2 LO leakage to the input port, and rejection of theLO at the input port. Fig. 18 shows the block diagram of themeasurement system for the MMW sub-harmonic demodulatorin this study. The MMW continuous wave (CW) signals, pro-vided by signal generator (Agilent E8267C), are fed into ourdemodulator MMIC. The LO source of the demodulator is pro-vided by another signal generator (Agilent E8247C). The outputspectrum can be measured by using a spectrum analyzer (Agi-lent E4448A). An oscilloscope is used to observe the I , I ,Q , and Q time-domain waveforms. At an RF of 60 GHz andbaseband of 10 MHz, the conversion loss is measured as a func-tion of LO power. The optimal LO drive is 8 dBm. Fig. 19plots the simulated and measured conversion loss versus RF fre-quency corresponding to I , I , Q , and Q ports from 15 to70 GHz. As can be observed, the simulation and measurementresults have a good agreement. The measured conversion loss

Fig. 19. Simulated and measured conversion loss versus the RF frequency from15 to 70 GHz for the sub-harmonic demodulator.

is 7.5 dB (to 50- load) with the gain flatness of 1.5 dB andthe amplitude imbalance is within 1.5 dB from 35 to 65 GHz.The downconverted I , I , Q , and Q time-domain wave-forms are shown in Fig. 20, where the RF unmodulated car-rier signal is 60 GHz and the downconverted baseband signalis 10 MHz. Measured isolation between RF to LO port, LOto RF port, and 2 LO to RF port are shown in Fig. 21. TheLO to RF port and 2 LO to RF port isolation are better than45 and 50 dB, respectively, from 35 to 65 GHz. The measuredinput 1-dB compression point of the mixer is 0 and 5 dBmat an RF of 40 and 60 GHz, respectively. To investigate theintermodulation properties of the mixer, two-tone intermodula-tion measurements with the frequency offset of 500 kHz areshown in Fig. 22. The typical input third-order intermodulationproduct (IIP3) is 9 dBm for an RF two-tone of 44.0005 GHzand 43.9995 GHz with an LO input of 21.995 GHz. The typicalinput second-order intermodulation product (IIP2) is 34 dBm.Fig. 23 is the measured conversion loss versus the baseband fre-quency from 1 MHz to 3 GHz with an LO frequency of 30 GHz



Fig. 20. Measured baseband time-domain quadrature signals at 10 MHz for thesub-harmonic demodulator.

Fig. 21. Measured isolation between RF to LO port, LO to RF port, and 2�LOto RF port.

Fig. 22. Measured IIP3 and IIP2 for the sub-harmonic demodulator (IF =

RF � 2 � LO, RF = 44 GHz� 500 kHz, LO = 21:995 GHz).

for the demodulator. The demodulator features a demodulationbandwidth above 1 GHz. The measured double-sideband noisefigure of the demodulator is 14.5 dB at an IF of 100 MHz and

Fig. 23. Measured conversion loss versus the baseband frequency of the sub-harmonic demodulator.

Fig. 24. Measured eye diagram of the 0.5-Gb/s and 1-Gb/s PRBS for the sub-harmonic demodulator.

RF of 40 GHz. The total dc power consumption of the sub-har-monic demodulator is 90.8 mW.

To verify the high data rates’ digital demodulation quality,the sub-harmonic demodulator is evaluated with 1-Gb/s datarates in a PRBS. The block diagram of the gigabit measurementsystem for an MMW sub-harmonic demodulator is also plottedin Fig. 18. The baseband signals are generated from a patterngenerator (Anritsu MP1763C) with a data rate of 1-Gb/s. Thebaseband signals are upconvert to the MMW frequency band (inthis study, 44 GHz), by a custom design MMW upconverter. The44-GHz gigabit modulation signal is fed into the sub-harmonicdemodulator for a demodulation quality test. The measured eyediagram of the 0.5-Gb/s and 1-Gb/s PRBS demodulation signalare plotted in Fig. 24, while the 50- input of the oscilloscope



is used as the load. To be observed, the clear eye opening isachieved for the satisfactory recovery of the baseband signal.

V. CONCLUSION

The first demonstration of the broadband sub-harmonicCMOS modulator and demodulator using 0.13- m standardMS/RF CMOS technology for MMW wireless gigabit appli-cations has been presented in this paper. The key component,i.e., the four-way quadrature divider of the sub-harmonicallypumped mixer, has been embedded to generate the quadra-ture-phases LO signals in the MMW frequency. For broadbandapplications, a broadband matching design formula is providedin this paper to extend the operational frequency range from 35to 65 GHz. To improve the conversion loss at high frequency,high-impedance compensation is incorporated between thetransconductance stage and LO switching quad of the mixer tocompensate the parasitic capacitance. A significant improve-ment can be achieved for the flatness of conversion loss overfrequencies after adding the compensation line. The modulatorexhibits 6 1.5 dB measured conversion loss from 35 to 65 GHzwith good sideband and 2 LO suppression. The demodulatorexhibits 7.5 1.5 dB measured conversion loss with amplitudeimbalance within 1.5 dB from 35 to 65 GHz. Furthermore,for wireless gigabit applications, a digital modulation signaltest is performed for the sub-harmonic modulator and demod-ulator. The experimental results show that the modulator anddemodulator feature broadband and gigabit direct-conversioncapabilities.

ACKNOWLEDGMENT

The chips were fabricated by the TSMC Semiconductors Cor-poration, Hsinchu City, Taiwan, R.O.C., through the Chip Im-plementation Center (CIC), Hsinchu City, Taiwan, R.O.C. Theauthors would like to thank H.-Y. Chang, National Central Uni-versity, Jhongli City, Taiwan, R.O.C., and P.-S. Wu, NationalTaiwan University, Taipei, Taiwan, R.O.C., for discussions.

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Jeng-Han Tsai (S’04) was born in Tainan, Taiwan,R.O.C., on December 20, 1980. He received theB.S. degree in electric engineering from NationalCentral University, Chung-Li, Taiwan, R.O.C., in2002, and Ph.D. degree from the Graduate Instituteof Communication Engineering, National TaiwanUniversity, Taipei, Taiwan, R.O.C., in 2007.

He is currently a Post-Doctoral Research Fellowwith the Graduate Institute of Communication Engi-neering, National Taiwan University. His research in-terests include microwave and MMW circuit designs.



Tian-Wei Huang (S’91–M’98–SM’02) received theB.S. degree in electrical engineering from NationalCheng Kung University, Tainan, Taiwan, R.O.C., in1987, and the M.S. and Ph.D. degree in electrical en-gineering from the University of California at LosAngeles (UCLA), in 1990 and 1993, respectively.

In 1993, he joined the TRW RF Product Center,Redondo Beach, CA. From 1998 to 1999, he waswith Lucent Technologies, where he was involvedwith the local multipoint distribution system (LMDS)fixed wireless systems. From 1999 to 2002, he was

involved with RF/wireless system testing with Cisco Systems. In August 2002,he joined the faculty of the Department of Electrical Engineering, NationalTaiwan University. His current research interests are MMIC/RFIC design,packaging, and RF system-on-chip (SOC) integration. His research has focusedon the design and testing of monolithic microwave integrated circuits (MMICs)and RF integrated circuits (RFICs).


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