IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND ... · the effective thermal conductivity of glass samples with copper TPVs. A Quantum Focus Instruments Infrared (IR) microscope, with

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015 1075

Impact of Copper Through-Package Vias onThermal Performance of Glass Interposers

Sangbeom Cho, Venky Sundaram, Rao R. Tummala, Fellow, IEEE, and Yogendra K. Joshi, Fellow, IEEE

Abstract— In this paper, the thermal performance of glassinterposer substrate with copper through-package vias (TPVs)is investigated both experimentally and numerically. Copper viaarrays with different via pitches and diameters were fabricatedin 114.3 mm × 114.3 mm × 100 µm glass panels usinglow-cost laser drilling, electroless plating, and electroplating forcopper deposition. The thermal performance of such a structurewas quantified by measuring an effective thermal conductivitywhich combines the effect of copper and glass. The effectivethermal conductivity of fabricated samples was determined withinfrared microscopy and compared with finite-element analysison unit TPV cell. Using the effective thermal conductivity,further numerical analyses were performed on a 2.5-D interposer,which has two chips mounted side by side with a total heatgeneration of 3 W. Interconnects and TPV layers in the interposerwere modeled as homogeneous layers with an effective thermalconductivity. Using the developed model, the effect of copperTPVs on the thermal performance of silicon and glass interposerswas compared. To further characterize the thermal performanceof the 2.5-D glass interposer structure, the effects of pitch ofinterconnects and TPVs and the TPV diameter are presented.

Index Terms— 2.5-D interposer, thermal performance,through-package via (TPV).

I. INTRODUCTION

S ILICON and glass interposers have been proposed and arebeing developed as next-generation substrates to overcome

the limitations of organic substrates due to many advantages,including high I/O density. However, a silicon interposer islimited to 300-mm wafer sizes, leading to high fabrication costof each interposer and high electrical loss limiting its electricalperformance. To address these issues, the 3-D SystemsPackaging Research Center at Georgia Tech has beendeveloping glass interposers since 2010 [1].

Glass has the merits of panel-based processing, whichresults in low costs. Combined with the advantages of ultra-high electrical resistivity, low electrical losses make glass anexcellent interposer candidate over organic and silicon [2].However, glass has a 100-times lower thermal conductivitythan silicon, which can result in poor thermal transmission.

Manuscript received December 24, 2014; revised May 3, 2015; acceptedJune 15, 2015. Date of publication July 23, 2015; date of current versionAugust 12, 2015. This work was supported by the Silicon and Glass Inter-posers Consortium through the Packaging Research Center, Georgia Instituteof Technology, Atlanta, GA, USA. Recommended for publication by AssociateEditor A. Jain upon evaluation of reviewers’ comments.

S. Cho and Y. K. Joshi are with the G. W. Woodruff School of MechanicalEngineering, Georgia Institute of Technology, Atlanta, GA 30332 USA(e-mail: [email protected]; [email protected]).

V. Sundaram and R. R. Tummala are with the 3D Systems PackagingResearch Center, Georgia Institute of Technology, Atlanta, GA 30332 USA(e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2015.2450731

This paper addresses this problem by experimentally andnumerically investigating the effect of copper through-packagevias (TPVs), which serve as a major thermal path within theinterposer.

The idea of using metal vias for thermal managementwas first adopted in the design of interconnects betweenthe chip and printed circuit boards (PCBs). Lee et al. [3]developed analytical closed form expressions for the thermalresistance network of vias between multichip modules, whichshowed good agreement with experimental data. Li [4] studiedthe relationship between the thermal resistance and the viadesign parameters. This paper shows that adding metal viascan improve the thermal performance across the PCB byover 10 times.

A number of studies have explored the advantages of2.5-D and 3-D package integration technologies (Fig. 1)over 2-D integration. The main advantage of 3-D technol-ogy is to enhance interconnect density using through-siliconvias (TSVs) in logic and memory chips, which provides animproved bandwidth due to reduced interconnect length [5].However, the power densities in these stacked 3-D integratedcircuits (ICs) dramatically increase as the number of stackedchips increases, while the area of the chips decreases. This mayresult in thermomechanical reliability failures, in addition tolower electrical performance due to high junction temperature.Incorporating thermal vias in ICs can be a promising way tosolve this problem. However, it poses area penalty for routingspace and reduces the number of electrical I/Os, resulting in atradeoff between thermal and electrical performances. Recentstudies with thermal vias were focused on the development ofalgorithms for an efficient placement of thermal vias in 3-DICs, minimizing the perturbations on routing [6], [7]. Goplenand Sapatnekar [6] developed an algorithm to determine theoptimized number of thermal vias in 3-D ICs for variousthermal objectives, including minimizing maximum temper-ature and thermal gradients. Lee and Lim [7] presented a co-optimization study for interconnects in 3-D ICs, consideringsignal, power, and thermal aspects.

Numerical simulations have also been carried out to studythe temperature distribution within 3-D ICs with TSVs.Ma et al. [8] proposed a simplified thermal model for TSVsin interposer using effective thermal properties. The accuracyand the application limits of the model were presented alongwith the volume ratio of copper and silicon. Lau and Yue [9]studied the thermal performance of 3-D IC integrationsystem-in-package with TSVs through modeling. The studypresented the effect of various parameters, including TSV fillermaterial, diameter, pitch, and aspect ratios, on the thermal

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1076 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 8, AUGUST 2015

Fig. 1. Schematic of (a) 2.5-D interposer packaging with logic and memory and (b) 3-D IC integration technology with TSVs.

resistance of the interposers. The thermal performance ofTSVs in 3-D chip stack was also evaluated experimentally.Zhang et al. [10] examined the thermal characteristics of TSVarrays by measuring the electrical resistance, which has alinear relationship with temperature. Matsumoto et al. [11]measured the temperature distribution of 3-D stacked test chipsand calculated the equivalent thermal conductivity of theinterconnection. Oprins et al. [12] presented a methodologyfor the detailed thermal analysis of stacked die packages,including the complete back-end-of-line structures. In thestudy, a two-die stacked structure in a ball grid array packageconfiguration was studied and the results were experimentallyvalidated.

Kim et al. [13] and Zhang et al. [14] have studiedthe application of advanced cooling schemes in 3-D ICs.Kim et al. [13] investigated single-phase and phase-changeconvection, and discussed the effect of different refrigerants onthermal performance of 3-D ICs. Zhang et al. [14] presented2.5-D and 3-D integration approaches with an embeddedmicrofluidic cooling, which utilized fluidic microbumps andfluidic vias. While a number of works have been reported onthe thermal characterization of silicon-based 2.5-D and 3-Dintegration technologies, thermal studies of glass-basedintegration technologies are currently lacking bothexperimental and numerical characterizations [15], [16].

This paper is organized into three sections. Section IIdescribes the fabrication process of glass interposer testsamples. Fabricated samples with via structures and test setupdesigned for the thermal performance measurements are alsopresented. Section III compares the test results with finite-element (FE) analysis. Section IV provides simulation resultsto study the effect of TPVs on the thermal performanceof 2.5-D glass interposers. The results from parametric studiesof the effect of via pitch and diameter are also presented.

II. THERMAL CONDUCTIVITY MEASUREMENT OF

GLASS INTERPOSER WITH COPPER VIAS

To measure the effect of copper TPVs on the thermalperformance of glass interposer, TPV via arrays werefabricated on a 114 mm × 114 mm × 100 μm borosil-icate glass panel. Prior to via drilling, both surfaces ofthe panel were cleaned with acetone and isopropyl alcohol.Then both sides were laminated with 22.5-μm-thick dielectricpolymer layers. A hot press machine was used during thelamination process with optimized temperature and timesettings. The laminated polymer layer serves as a buildup layer

Fig. 2. Process flow for glass interposer fabrication.

for wiring and also as a buffer layer which reduces the impactof laser on glass during the ablation process [2]. The laminatedglass sample was then subjected to UV laser ablation forvia formation. The UV laser drilling resulted in tapered viaprofiles.

Fig. 2 summarizes the process flow used for the testsample fabrication. It also shows the optical images of glasssamples’ via entrance and exit formed by UV laser ablation.To achieve good metal adhesion to the glass panel, the surfaceof polymer was roughened through microetch processes.A 1-μm copper seed layer was formed on the roughenedsurface through electroless copper deposition, followed byelectrolytic copper plating processes which resulted in a finalcopper layer thickness of 10 μm. After having the via sidewalls plated, via pads were patterned using photolithography.Via pad diameter was designed to be 40 μm larger thaneach via diameter. Table I summarizes the via dimensions offabricated via arrays including entrance and exit via diameters,pitches, plating thickness, pad size, and the number of vias.After patterning the via pads, the panel was diced into10 pieces of 2.54 mm × 2.54 mm-size glass samples withTPV arrays having different via parameters.

A. Test Setup for Effective ThermalConductivity Measurement

To measure thermal conductivity of via samples, a heaterassembly was fabricated, which consisted of a heater

CHO et al.: IMPACT OF COPPER TPVs ON THERMAL PERFORMANCE OF GLASS INTERPOSERS 1077

TABLE I

TPV GEOMETRY AND DIMENSIONS

and a PCB. The size of the heater was 2.54 mm × 2.54 mm,which corresponded to the sample size with a 100-μm thick-ness. The heater was comprised of two resistors, each able todissipate a maximum power of 6 W and was wire bonded tothe PCB for power supply connection. Two diodes placed atthe center and the edge of the heater were utilized for surfacetemperature measurements. The heat-generating surface of theheater was exposed to ambient, and its other sides weresurrounded by epoxy with wire bonds. The epoxy protected theheater and wirebonds from mechanical and electrical impactand also minimized heat loss from the surfaces of heater. Afterthe epoxy was cured, the heater diodes were calibrated byputting the assembly in a large oven. A via-patterned glasssample of the size of 2.54 mm × 2.54 mm was attachedto the heater using a thermal adhesive pad. After the samplewas attached to the heater, the assembly was covered with aninsulation material to reduce heat losses through convectionand radiation to the ambient.

Fig. 3 shows the schematic of the test setup used to measurethe effective thermal conductivity of glass samples withcopper TPVs. A Quantum Focus Instruments Infrared (IR)microscope, with a spatial resolution of 2.8 μm and a pixel sizeof 1.6 μm, was used to measure the surface temperature of thesample. The heater assembly was mounted and tightly fixedon the thermal stage of IR microscope using Teflon blocks.Two source meters were connected to the heater assembly tosupply power to the heater and to provide constant currentsource (1 mA) to diodes.

Six additional thermocouples were attached to the PCBand the epoxy area to estimate the amount of heat dissipatedthrough conduction. Prior to the measurements, the surface ofthe sample was coated with a black carbon spray to reducethe uncertainty in the measurement.

Fig. 3. Schematic of test setup to measure effective thermal conductivity ofglass samples with copper vias.

The IR microscope measures radiance at a defined referencetemperature. This allows the acquisition of the referenceemissivity at each pixel area of the sample. This calibratedemissivity map of the sample was used in subsequentmeasurements to accurately measure temperature. Thereference temperature was selected such that it was in proxim-ity to the temperature of the area of interest during the tests.

Heat loss through epoxy was estimated using thermalresistance analysis, including spreading resistance, andcalculated to be ∼14% of total power input of the heater.Heat loss through convection Qc was estimated using (1) andits heat transfer coefficient hc was calculated using (2) forsmall devices in a natural convection condition [17]

Qc = hc A�T (1)

hc = 0.83 f (�T/Lch)n (2)

where �T is temperature difference between the surface andthe ambient, Lch is the characteristic length, f = 1 andn = 0.33 for horizontal plate facing upward.

Heat loss through radiation QR was estimated using theexpression for a small surface in large surroundings

QR = εσ A(T 4

surf − T 4sur

)(3)

where Tsurf is the sample’s surface temperature (∼343 K)at targeted heater power level, Tsur is the temperature ofthe surroundings, ε (∼0.8) is emissivity measured by theIR microscope system, and σ is the Stefan–Boltzman constant(5.67×10−8 W/m2 · K4). Total heat losses through convectionand radiation were found to be ∼5% of the total heater power.

Fig. 4 shows the thermal resistance network of the viasample stack-up on heater. Heater resistance Rh and thermalpad resistance Rp were measured separately prior to eachstack-up to determine T 3. The average surface temperature ofthe sample T 4 was measured by the IR microscope. Finally,the effective thermal conductivity of the glass sample wascalculated using

k = Q′′ �y

�T(4)


Fig. 4. Thermal resistance network of sample stack-up on heater.

where Q′′ is the heat flux calculated using the power inputof the heater minus the estimated heat losses, �y thesample thickness, and �T the temperature difference betweenT 4 and T 3.

B. Effective Thermal Conductivity Calculation

Due to the large number of via interconnects, the develop-ment of the thermal model of interposer is computationallyintensive. To resolve this problem, an equivalent model witheffective thermal conductivity has been used [9], [18]. Sinceinterconnect vias are populated in the interposer with repeatedgeometric patterns, they can be simplified by converting asingle cell of interconnect/TPV pattern into a block with arepresentative thermal conductivity. Both in-plane andout-of-plane thermal conductivity should be calculated becausethe thermal path offered by the copper structure is dependenton the direction of heat flow. To determine in-plane andout-of-plane effective thermal conductivity of a interconnect/TPV cell, the inward heat flux boundary condition was appliedto the left/top surface, the outward heat flux condition wasapplied to the right/bottom surface, and the adiabatic conditionwas applied to the other side walls of the model. Effectivethermal conductivity was calculated with (4) using the averagetemperature of left/top and right/bottom surfaces. Models forthree different samples listed in Table I were developed andthe effective thermal conductivities were calculated.

C. Test and Simulation Results

Fig. 5 shows steady-state IR images of the glass sampleswith different via patterns heated from the back. In each image,copper pads show the highest temperature due to high thermalconductivity compared with polymer-laminated glass aroundthem. However, the temperature profile along the copper padwas not symmetric, a trend observed for all samples.

From the cross-sectional and top view images shownin Fig. 6, it was observed that copper was not evenly platedat the heater side of each TPV, which caused poor thermalcontact between the heater and the sample. A likely causewas the misalignment of the TPV mask with glass panel duringphotolithography. This additional interfacial thermal resistancebetween the sample and the heater is thought to be the majorreason for the nonuniform temperature profile along the edgeof the TPV in IR images.

Fig. 5. Surface temperature profile of (a) Sample 1, (b) Sample 2,(c) Sample 3, and (d) Sample 4 measured with IR microscopy. D: diametersof vias. P: pitches of vias. N : numbers of vias.

Fig. 6. Cross-sectional view (top) and top view (bottom) of Sample 3.

The resolution uncertainty of the test system was calculatedusing equation

uG =√(

∂G

∂x1u1

)2

+(

∂G

∂x2u2

)2

+ · · · +(

∂G

∂xnun

)2

(5)

where uG is the uncertainty of variable G and u1–un are theuncertainties of variable x1–xn.

The uncertainties of the test results were calculated afterperforming five sets of measurements for each sample,


TABLE II

COMPARISON OF THE MEASURED OUT-OF-PLANE EFFECTIVE THERMAL

CONDUCTIVITIES OF THE GLASS SAMPLES WITH SIMULATION

Fig. 7. Copper plating condition of vias in (a) original and (b) correctedmodels.

and expressed as

uk = B ± σ (6)

where uk is the uncertainty of the measured effectiveout-of-plane thermal conductivity, B is the average value,and σ is the standard deviation of five measurements. Beforetaking each measurement, the sample was cooled downto ambient temperature, and heated up again to referencetemperature for new emissivity mapping.

Table II compares the effective out-of-plane thermal conduc-tivity of four samples. Results for Samples 2–4 are comparedwith the simulation results from single via analysis introducedin the previous section, while Sample 1 simulation is comparedwith the measurement in [15]. Samples 2 and 3 show largedifferences (∼36% and ∼39%), while Sample 4 shows theleast (∼5%). Several factors, including additional heat loss,quality of thermal contact between each layer in the samples,and copper plating quality, can contribute to the discrepancy.

From the test and simulation results, shown in Table II, theimplementation of 144 copper vias with a diameter of 100 μmat a pitch of 200 μm in a 2.54 mm × 2.54 mm area increasesthe out-of-plane thermal conductivity of the glass substrateby ∼20 times compared with its original property (1 W/m · K).

One of the sources of the discrepancy between the test andsimulation for Samples 2 and 3 was copper plating quality.Based on the copper plating quality condition acquired fromthe cross-sectional top and bottom images of the samples,new via models were developed. Fig. 7 shows two different

TABLE III

PERCENTAGE ERROR BETWEEN CALCULATED EFFECTIVE OUT-OF-PLANE

THERMAL CONDUCTIVITY FROM MODELS AND

MEASUREMENTS FOR SAMPLES 2 AND 3

via models with different copper plating conditions of vias inthe original model and the corrected model. Another sourceof error can be the contact resistance between the thermaladhesive and the sample, which was neglected in the model.To evaluate the effect of the contact resistance on the discrep-ancy between modeling and test results, the contact resistanceof the same adhesive material (room temperature vulcanizationsilicone) from [19] was used, assuming that the contactconditions between the sample and the adhesive are similar.

Table III shows the error (in %) calculated aftercomparing the effective out-of-plane thermal conductivityfrom the original copper plating condition corrected and thecontact resistance-applied model with test results.

The errors (in %) for Samples 2 and 3 decrease as themodels get corrected, which shows that these two factors canbe the major causes of the discrepancy. To get more accuratetest results, the contact resistance of each sample needs to bemeasured.

III. SIMULATION WITH 2.5-D INTERPOSER APPLICATION

Prior studies have shown that the thermal conductivityof the substrate does not significantly affect the thermalperformance of the interposer as most of the heat generatedfrom chips is dissipated through the back of the chip to thelid or heat sink [16]. Interposer structures without heat sinkwere considered for low-power application (3 W) to showthe effect of interposer components on thermal performance.Using an equivalent interposer model with effective thermalconductivities for copper TPVs, a 2.5-D glass interposerwas developed. The interposer model consisted of five majorcomponents: chips, microbumps, interposer, bumps, and PCB.Several assumptions were made in the modeling of eachcomponent as geometric details and arrangements of TPVsare dependent on the floorplanning of the dies and signalassignment. General assumptions made for current simulationstudies are as follows.

1) Both chips on the interposer have identical size(10 mm × 10 mm) and heat generation.

2) Chips are modeled as two blocks which have uniformvolumetric heat generations and the distance betweenthe two chips is fixed at 100 μm.

3) Microbumps under the periphery area of the chips havesmaller pitch than those in the center area and areassigned for signal delivery between dies.


Fig. 8. Schematic of 2.5-D interposer and geometric dimensions of microbumps, TPVs, and bumps used for modeling.

4) Microbumps under the center area of the chips(9 mm × 9 mm area) are directly connected to copperTPVs. TPVs are also connected to bumps directly forground connection to PCB.

5) 20% of TPVs are assigned as ground TPVs. The groundTPVs are connected to copper vias in PCB, which aredirectly connected to a ground plane.

6) One ground plane is embedded in PCB. It has the samesize as PCB (50 mm × 50 mm) and a thickness of 0.5 oz(∼18 μm). A power layer in PCB is not considered inthe model.

7) As the number of interconnects increases or decreases,the number of TPVs also increases or decreases forincreased-decreased signal delivery. To control intercon-nects and TPVs together, four microbumps are assumedto be connected with one TPV, and two TPVs areconnected with one bump. For ground via connection,each bump is mapped one-to-one to copper vias in PCB.Ground TPVs are assumed to be placed under the centerof the chip area.

8) All heat generated from chip (3 W) is assumed to beconducted through components and dissipated at thebottom of PCB, which has its bottom plane temperaturefixed at 300 K.

Based on the above assumptions, a parametric design studyof silicon and glass interposers was performed to characterizethe effect of copper TPVs and copper ground plane.

A. Effect of Copper TPVs and Ground Planeon Glass and Silicon Interposers

The purpose of the first simulation was to compare theeffect of copper TPVs on the thermal performance of silicon

TABLE IV

GEOMETRIC DIMENSIONS OF INTERPOSER COMPONENTS

and glass interposers. The model did not include the effectof copper traces within re-distribution layer in the interposeror PCB and focused only on the effect of copper vias andsingle copper ground plane on the thermal performance of theinterposer.

The geometric details are summarized in Fig. 8. Thedimensions of chips, interposer, and PCB, and the number ofinterconnects/vias are tabulated in Table IV. Table V summa-rizes material thermal conductivities. As a baseline, silicon andglass interposer structures without copper TPVs and groundplane were considered and the maximum temperature of eachstructure was compared with each interposer structure havingvias and ground plane implemented. TPV shape, diameter, andtotal substrate thickness were kept the same for silicon andglass interposers as shown in Figs. 8 and 9. The thickness ofthe polymer layers in the glass interposer was 22.5 μm, whichcorresponded to the thickness of the polymer laminated onthe sample. The SiO2 layer thickness in the Si interposer wasmodeled as 1 μm, which corresponded to the typical dielectriclayer thickness on a silicon interposer.


TABLE V

MATERIAL PROPERTIES AND CALCULATED EFFECTIVE THERMAL

CONDUCTIVITIES OF INTERCONNECTS AND TPVs

Fig. 9. Geometric dimension of TPV in silicon interposer.

Fig. 10 compares the surface temperature profile and themaximum temperature of the two interposers for two differentcases, when each chip generates 1.5 W. Due to symmetry,only a quarter of the geometry was considered and is shownin Fig. 10. Without copper TPVs and ground layers, the glassinterposer showed a 32% higher maximum temperature thanthe silicon interposer.

The glass substrate showed a similar temperature withPCB, as glass impedes the heat being conducted throughthe substrate. The silicon interposer, however, decreased thechip temperature, resulting in a substrate temperature higherthan that of the glass interposer. The difference in maximumtemperature between glass and silicon interposers decreasedafter TPVs and ground layer were implemented in bothinterposers as shown in Fig. 10(b) and (d). The glass interposershowed a 17% higher maximum temperature than the siliconinterposer. The results indicate that the copper TPVs in theglass interposer perform more effectively than those in thesilicon interposer.

Fig. 11 compares junction-to-board thermal resistance � j b

improvement of glass and silicon interposers, where

� j b = Tj − Tb

Q(7)

where Tj is the junction temperature, Tb is the board bottomtemperature, and Q is the total heat generated from the chips.The addition of TPVs and ground layer decreased the thermalresistance of both interposers, but the resistance of glass

Fig. 10. Surface temperature profile of (a) and (b) glass interposer and(c) and (d) silicon interposer with different via and layer condition.

Fig. 11. Normalized junction-to-board thermal resistances of glass and siliconinterposers with different via and ground layer conditions.

interposer showed higher comparative decrease than silicon,and confirmed the better thermal effectiveness of copper TPVsin the glass interposer than those in silicon.

B. Effect of TPV Pitch on Thermal Performanceof Glass Interposer

To characterize the effect of interconnects and TPVs onthe glass interposer, further analyses of the effect of pitchwere performed based on Assumption 7. Three cases withdifferent numbers of interconnects and TPVs were consideredfor the glass interposer structure. Table VI lists the numbersand the pitches used for three different cases. Other geometricfeatures and dimensions remained the same as shown in Fig. 8.During the simulation, only the pitch of microbumps in the


TABLE VI

PITCH/COUNT AND NORMALIZED � jb OF MICROBUMPS, TPVs, AND

BUMPS FOR THREE CASES. EACH THERMAL RESISTANCE IS

NORMALIZED BY THE RESISTANCE VALUE FROM CASE 1

Fig. 12. Normalized junction-to-board thermal resistance with differenteffective out-of-plane thermal conductivities of three components(microbumps, TPVs, and bumps). Each component’s resistance is normalizedby its maximum value.

center area was varied, and the outside of it was kept constantas 80 μm. The total number of microbumps in the peripheryarea was 1900. Table VI compares the � j b in three cases bynormalizing them by maximum value from Case 1. As thenumber of interconnects and TPVs increased, the thermalperformance of the glass interposer also increased, but itseffect was not significant. Case 3 showed a 9% better thermalperformance than Case 1 by having a ∼3.5 times highernumber of interconnects and TPVs.

Fig. 12 shows the thermal performance improvement ofthe glass interposer by changing the effective out-of-planethermal conductivity of the microbumps, TPVs, and bumps.Interconnect and TPV counts in Case 1 of Table VI wereconsidered for the fixed components. The variation of thermalconductivity ranged from that of glass (1 W/m · K) to copper(400 W/m · K). The effect of interconnect/TPV on in-planethermal conductivities was not considered because negligiblevariation in it was observed compared with out-of-planethermal conductivity. A consistent dependence trend for allthe three components was demonstrated with a relatively largedrop between 1 and ∼50 W/m · K. Increasing the thermalconductivity of interconnect/TPV layers beyond 100 W/m · Kdid not enhance the performance much. The thermalconductivity change in bump layer affected the thermalperformance of the interposer the most, while the microbumpaffected the least.

Fig. 13. Junction-to-board thermal resistances of glass interposer withdifferent D1 (laser entrance diameter) and D2 (laser exit diameter).

For interconnects, an effective thermal conductivity in therange 50–100 W/m · K is hard to achieve, as the solder hasa lower thermal conductivity (∼50 W/m · K) than copper.However, TPV only consists of copper and thus can have awider range of effective thermal conductivity values, depend-ing on the amount of copper used for filling vias. Fig. 13 showsthe change in � j b for different TPV diameters at fixed pitch(300 μm) and height of the interposer (145 μm). As thediameters (D1 and D2) increase, the effective out-of-planethermal conductivity of the TPV layer also increases due tothe increased copper volume fraction. This result indicatesthat increasing out-of-plane thermal conductivity to that ofcopper gave insignificant enhancement, compared with theimplementation of TPVs with diameters of 160 and 130 μm.This implies that the thermal resistance of other compo-nents becomes more dominant than that of the interposersubstrate after TPV implementation. The change in effec-tive in-plane thermal conductivity of TPV was negligible(∼1–∼3 W/m · K) compared with the change in effectiveout-of-plane thermal conductivity (∼1–∼220 W/m · K) duringthe analysis.

IV. CONCLUSION

This paper investigates the effect of copper TPVs in glassinterposers through FE modeling and measurements. CopperTPVs were fabricated in a glass interposer and their effec-tive thermal conductivity was measured by IR microscopy.The measured values were compared with the results fromthe FE model which used an equivalent TPV layer witheffective thermal conductivity. Using the equivalent modelingtechnique, a 2.5-D interposer model was developed for para-metric design study. Detailed interconnects and TPV geometrydimensions were incorporated in the modeling to develop amore realistic model. Major results from the parametric designstudy are as follows.

1) The implementation of copper TPVs in glass interposersand copper ground layers in PCBs enhanced the thermalperformance of interposers. Interconnects and TPVsperform as thermal as well as electrical paths.


2) The TPVs in glass interposer performed more effec-tively than in the silicon interposer. Glass isolated heatwithin the chip due to its low thermal conductivity.The silicon interposer substrate, however, played a roleas a heat spreader which efficiently lowered the chiptemperature.

3) Increasing the number of interconnects and TPVs bydecreasing their pitch improved the thermal performanceof the glass interposers due to the increased effectiveout-of-plane thermal conductivity of interconnect andTPV layers. It was shown that the glass interposer’sout-of-plane thermal resistance became no longersignificant for effective thermal conductivities higherthan 100 W/m · K.

ACKNOWLEDGMENT

The authors would like to thank the member companiesof the low-cost glass interposers and packages consortium atthe Georgia Institute of Technology 3-D Systems PackagingResearch Center for supporting this study.

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[11] K. Matsumoto, S. Ibaraki, K. Sakuma, and F. Yamada, “Thermalresistance measurements of interconnections for a three-dimensional(3D) chip stack,” in Proc. IEEE Int. Conf. 3D Syst. Integr., Sep. 2009,pp. 1–5.

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[19] P. Teertstra, “Thermal conductivity and contact resistancemeasurements for adhesives,” in Proc. ASME InterPACK, Jul. 2007,pp. 381–388.

Sangbeom Cho received the B.S. degree fromHanyang University, Seoul, Korea, and theM.S. degree in mechanical engineering fromthe Korea Advanced Institute of Science andTechnology, Daejeon, Korea. He is currentlypursuing the Ph.D. degree in mechanical engineeringwith the Georgia Institute of Technology, Atlanta,GA, USA.

He is with the 3-D Systems Packaging ResearchCenter, Georgia Institute of Technology. His currentresearch interests include thermal management of

microelectronics.

Venky Sundaram received the B.S. degree fromIIT Mumbai, Mumbai, India, and the M.S. andPh.D. degrees in materials science and engineeringfrom the Georgia Institute of Technology, Atlanta,GA, USA.

He is currently the Director of Research andIndustry Relations with the 3-D Systems PackagingResearch Center, Georgia Institute of Technology.He is the Program Director of the Low-Cost GlassInterposer and Packages Industry Consortium withmore than 25 active global industry members. He is

a globally recognized expert in packaging technology and a Co-Founderof Jacket Micro Devices, Livonia, MI, USA and an RF/wireless startupacquired by AVX Corporation, Fountain Inn, SC, USA. He has authoredover 15 patents and 100 publications. His current research interests includesystem-on-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research.

Dr. Sundaram has received several best paper awards. He is the Co-Chairmanof the IEEE CPMT Technical Committee on High-Density Substrates andthe Director of Education Programs with the Executive Council of theInternational Microelectronics and Packaging Society.


Rao R. Tummala (F’93) received theB.S. degree from the Indian Institute ofScience (IIS), Bangalore, India, and the Ph.D.degree from the University of Illinois at Urbana–Champaign, Champaign, IL, USA.

He was an IBM Fellow, pioneering the first plasmadisplay and multichip electronics for mainframesand servers. He is currently a Distinguishedand Endowed Chair Professor and the FoundingDirector of the National Science Foundation’sEngineering Research Center with the Georgia

Institute of Technology, Atlanta, GA, USA, pioneering Moore’s Law forsystem integration. He has authored over 500 technical papers, holds74 patents and inventions, and has authored the first modern book entitledMicroelectronics Packaging Handbook, the first undergrad textbook entitledFundamentals of Microsystems Packaging, and the first book introducing thesystem-on-package technology.

Prof. Tummala is a member of the National Academy of Engineering.He has received many industry, academic, and professional society awards,including the Industry Week’s Award for improving the U.S. competitiveness,the IEEE David Sarnoff Award, the International Microelectronics andPackaging Society Dan Hughes Award, the Engineering Materials Awardfrom ASM, and the Total Excellence in Manufacturing from SME.He received the Distinguished Alumni Awards from the University of Illinoisat Urbana–Champaign, IIS, and the Georgia Institute of Technology. He wasa recipient of the Technovisionary Award from the Indian SemiconductorAssociation and the IEEE Field Award for his contributions to electronicssystems integration and cross-disciplinary education in 2011. He wasthe President of the IEEE Components, Packaging, and ManufacturingTechnology Society and the IEEE International Microelectronics andPackaging Society.

Yogendra K. Joshi (F’12) received the B.Tech.degree in mechanical engineering from IIT Kanpur,Kanpur, India, in 1979, the M.Sc. degree inmechanical engineering from the State Universityof New York, Buffalo, NY, USA, in 1981,and the D.Phil. degree in mechanical engineeringand applied mechanics from the University ofPennsylvania, Philadelphia, PA, USA, in 1984.

He is currently a Professor and John M. McKenneyand Warren D. Shiver Distinguished Chair with theG. W. Woodruff School of Mechanical Engineering,

Georgia Institute of Technology, Atlanta, GA, USA. He has authored orco-authored over 260 archival journal and conference publications. His currentresearch interests include multiscale thermal management.

Prof. Joshi is a fellow of the American Society of MechanicalEngineers (ASME) and the American Association for the Advancement ofScience. He was a co-recipient of the ASME Curriculum Innovation Awardin 1999, the Inventor Recognition Award from the Semiconductor ResearchCorporation in 2001, the ASME Electronic and Photonic Packaging DivisionOutstanding Contribution Award in Thermal Management in 2006, the ASMEJournal of Electronics Packaging Best Paper of the Year Award in 2008, theIBM Faculty Award in 2008, the IEEE Semitherm Significant ContributorAward in 2009, the IIT Kanpur Distinguished Alumnus Award in 2011,the ASME InterPack Achievement Award in 2011, the ITherm AchievementAward in 2012, and the ASME Heat Transfer Memorial Award in 2013.

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