4
Optimal Schematic Design of Low-Q IP Blocks Sergey G. Krutchinsky, Fellow IEEE Department of automatic control systems Taganrog Institute of Technology Southern Federal University, scientific center «MicAn» Taganrog, Russian Federation E-mail: [email protected] Mikhail S. Tsybin, graduate student Department of automatic control systems Taganrog Institute of Technology Southern Federal University, scientific center «MicAn» Taganrog, Russian Federation E-mail: [email protected] Abstract Universal procedure of schematic design of compensating feedback loops is offered. The syn- thesis schemes algorithm with cancellation is for- mulated. Examples of high-stable circuit with can- cellation design are considered and appropriate- ness of use and development of multidefferential OA as new type of IP blocks of active components is shown. 1. Introduction Creating mixed-signal systems on chip (SoC) order to design of analog and discrete -analog IP blocks, which provide signals converting high pre- cision with low power consumption. For this reason traditional schematic decisions application at de- sign of analog nodes and device forming these blocks results in inconsistent requirements - high precision (low parametric sensitivity) offers to ac- tive components using (example, OA) with high current consumption. The modern production tech- nology of mixed-signal SoC provides high identity of active element parameters. So, in operational amplifiers (ОУ) relative changes of static gain (μ) and gain bandwidth (f 1 ) in a temperature range to 100ºС are made of 10 1 %, and their difference for separate ОУ 10 times less. This technological fea- ture to the full isn't used in circuitry of difficult high-sensitivity devices and IP blocks, but as shown in [1], has good possibilities of increasing of mixed-signal SoC quality factors. 2. Problem statement Generally parameter P is appropriateness to use a pole or zero of transfer function Ф(p) or complex transfer coefficient Ф(jω). Typical parameters of such approach is frequency of a pole (ω p ) and its Q factor (Q=1/d p ). For the general problem decision it is necessary to create schematic circuits in which parametrical minimization of these parameters sen- sitivity is possible. As shown in [1] decision of a task in assigned task is reduced to minimization of the sums min, min, 1 1 1 N j P f N j P j j S S (1) provided that N j const S const S P f P j j , 1 , mod , mod 1 (2) doesn't increase (keeps the numerical value). Figure 1. Structural feature of compensating feedback loop. Selected minimization demands application of additional compensating feedback loops (fig. 1), action of which directed as to partial parametrical sensitivity minimization and its sign changing, as to an increment changing of idealized transfer func- tion Фи(p) the designed device, influence-caused by jth OA transfer function К(р) p F p F p K p H p H p F p K p p jj jj j j j j j u 1 1 1 . (3) Here local transfer functions H j (p), F j (p) and F jj (p) are defined for the idealized scheme from follow- ing experiences. At an input signal source connection to the basic input scheme transfer function F j (p) on jth OA out- put is defined, and at carrying over signal source to not inverting jth OA input similar transfer functions on scheme output H j (p) and on jth OA output F jj (p) are defined. Feedback loop circuit W(p) connection between a differential input considered OA and an additional the scheme input (In. c) allows to gener- ate local transfer functions p H j and p F jj in- crements, reducing jth OA influence. From a ratio (3) follows that under concrete par- ametrical conditions for multiterminal network W(p) a sign change becoming under the influence of jth OA parameters idealized transfer function final increment of all designed device is possible. This variant provide cancellation of separate OA dominating parameters influence on scheme pa- rameter P and, therefore, exclude relative changes and 1 1 f f influence, active elements defined by identity. Fulfillment of condition (2) allows not increasing influence of real deviations from "identi- ty". In this case 978-1-4577-1958-5/11/$26.00 ©2011 IEEE

[IEEE Test Symposium (EWDTS) - Sevastopol, Ukraine (2011.09.9-2011.09.12)] 2011 9th East-West Design & Test Symposium (EWDTS) - Optimal schematic design of low-Q IP blocks

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Page 1: [IEEE Test Symposium (EWDTS) - Sevastopol, Ukraine (2011.09.9-2011.09.12)] 2011 9th East-West Design & Test Symposium (EWDTS) - Optimal schematic design of low-Q IP blocks

Optimal Schematic Design of Low-Q IP Blocks

Sergey G. Krutchinsky, Fellow IEEE Department of automatic control systems

Taganrog Institute of Technology Southern Federal University, scientific center «MicAn»

Taganrog, Russian Federation E-mail: [email protected]

Mikhail S. Tsybin, graduate student Department of automatic control systems

Taganrog Institute of Technology Southern Federal University, scientific center «MicAn»

Taganrog, Russian Federation E-mail: [email protected]

Abstract Universal procedure of schematic design of

compensating feedback loops is offered. The syn-thesis schemes algorithm with cancellation is for-mulated. Examples of high-stable circuit with can-cellation design are considered and appropriate-ness of use and development of multidefferential OA as new type of IP blocks of active components is shown.

1. Introduction Creating mixed-signal systems on chip (SoC)

order to design of analog and discrete -analog IP blocks, which provide signals converting high pre-cision with low power consumption. For this reason traditional schematic decisions application at de-sign of analog nodes and device forming these blocks results in inconsistent requirements - high precision (low parametric sensitivity) offers to ac-tive components using (example, OA) with high current consumption. The modern production tech-nology of mixed-signal SoC provides high identity of active element parameters. So, in operational amplifiers (ОУ) relative changes of static gain (μ) and gain bandwidth (f1) in a temperature range to 100ºС are made of 101%, and their difference for separate ОУ 10 times less. This technological fea-ture to the full isn't used in circuitry of difficult high-sensitivity devices and IP blocks, but as shown in [1], has good possibilities of increasing of mixed-signal SoC quality factors.

2. Problem statement Generally parameter P is appropriateness to use

a pole or zero of transfer function Ф(p) or complex transfer coefficient Ф(jω). Typical parameters of such approach is frequency of a pole (ωp) and its Q factor (Q=1/dp). For the general problem decision it is necessary to create schematic circuits in which parametrical minimization of these parameters sen-sitivity is possible.

As shown in [1] decision of a task in assigned task is reduced to minimization of the sums

min,min,11

1

N

j

Pf

N

j

Pjj

SS (1)

provided that

NjconstSconstS Pf

Pjj

,1,mod,mod1

(2)

doesn't increase (keeps the numerical value).

Figure 1. Structural feature of compensating feedback loop.

Selected minimization demands application of additional compensating feedback loops (fig. 1), action of which directed as to partial parametrical sensitivity minimization and its sign changing, as to an increment changing of idealized transfer func-tion Фи(p) the designed device, influence-caused by jth OA transfer function К(р)

pFpFpK

pHpHpFpK

ppjjjj

j

jjj

ju

11

1 . (3)

Here local transfer functions Hj(p), Fj (p) and Fjj(p) are defined for the idealized scheme from follow-ing experiences.

At an input signal source connection to the basic input scheme transfer function Fj(p) on jth OA out-put is defined, and at carrying over signal source to not inverting jth OA input similar transfer functions on scheme output Hj(p) and on jth OA output Fjj(p) are defined. Feedback loop circuit W(p) connection between a differential input considered OA and an additional the scheme input (In. c) allows to gener-ate local transfer functions pH j and pF jj in-crements, reducing jth OA influence.

From a ratio (3) follows that under concrete par-ametrical conditions for multiterminal network W(p) a sign change becoming under the influence of jth OA parameters idealized transfer function final increment of all designed device is possible. This variant provide cancellation of separate OA dominating parameters influence on scheme pa-rameter P and, therefore, exclude relative changes

and 11 ff influence, active elements defined by identity. Fulfillment of condition (2) allows not increasing influence of real deviations from "identi-ty".

In this case

978-1-4577-1958-5/11/$26.00 ©2011 IEEE

Page 2: [IEEE Test Symposium (EWDTS) - Sevastopol, Ukraine (2011.09.9-2011.09.12)] 2011 9th East-West Design & Test Symposium (EWDTS) - Optimal schematic design of low-Q IP blocks

,1

2

1

211

N

j

Pff

N

j

Pjj

SSPP

(4)

where j :

;)(,

)(,)()(max

1

1

1

1)( 1

jj

jjf f

ff

f

(5)

parameter P stability increases repeatedly and de-fined as by deviations and

1f , and also root-mean-square value of parametrical sensitivity. In [1] is shown that the present condition is not only sufficient, but also the unique for the general prob-lem decision. However there is opened a question of a choice of jth OA, an additional input and struc-ture of compensating multiterminal network W(p).

The decision of this problem has a line of fea-tures and is connected with the frequency selection devices synthesis general theory.

3. Symmetric multidifferential OA Statement of a base algorithm of schematic cir-

cuit structures synthesis with cancellation of OA gain bandwidth influence on filter unevenness (characteristics) in a pass-band we will accompany with the additional remark. Structural principle evolution of self-compensation and cancellation shows that for minimization of active elements total number used ОA should be characterized by additional input resistance. It was a stimulus for working out of whole OA class with multidifferen-tial inputs [2], [3]. As for the assigned task decision the basic interest represent multidifferential ОA with a symmetric input. The structure and symbol of such amplifier are shown on Fig. 2.

Figure 2. The structure (a) and symbol (b) of symmetric multi-

differential.

Here along with the basic differential stage (DS0) the set of auxiliary differential stages (DSi) with current output is used. The current output and potential output of the separating stage (SS) pro-vide effective gain signal and its coordination with the OA output stage (OS). Use of the general feed-back leads to the following idealized transfer func-tion on an additional input

0

1( ) ii

Kp

K (6)

where 0K , iK – transfer coefficients of main (0) and additional (i) differential stages. – feedback transfer coefficient, connecting output to inverting input of the main differential stage.

For the decision of the general problem of 0K and OA influence cancellation on characteristics

and parameters of the filter the major in the ratio (6) is the relation 0iK K . The existing differential stages circuitry allows realizing this ratio with the relation accuracy of two resistive elements of the general scheme [3]. The given property, as it will be shown below, is the core for creation of sche-matic circuit with cancellation.

4. Synthesis algorithm of the high or-der schemes with cancellation

For increase of loops cancellation efficiency it is necessary to provide additional f1 compensation at the cost of other scheme active elements. Such statement of a problem is possible because of their identity. Its decision, according to Fig. 1, is con-nected with search of an additional scheme input at which the local transfer functions increment enter-ing into a ratio (3), provides material transfer com-ponent kw . For maintenance of f1j influence cancel-lation this input should possess following proper-ties: to realize transfer function on an any ОA input:

)p(FK1)p(F

N

1jjjkj

(7)

where K – coefficient, defined by condition of par-ametrical optimization of total sensitivity (1). to be characterized by an input impedance, ad-missible for connection of a used active element.

The second property of an input isn't described strictly according to set of the factors that influence on decision-making. Additional inputs k generally can be created by connection of a set of passive elements. Their completeness is important substan-tial part of preparatory stage of synthesis. Here we examine only the difference of the second synthesis stage which connected with high order of transfer function and low Q factor of poles.

In this case electronic circuit transfer function will be shown as:

)р(В)р(В

)р(А)р(Ф

, (8)

at what, the increment of a denominator polynomial is caused by influence of general parameters of active elements:

)(2

)(1)()(

1 11pF

)πf(ppF

рВрВ

jj

N

j jjj

N

j j

(9)

and local transfer function )p(F jj is determined by ratio (3).

Conditions of cancellation have the following appearance:

min)(2

)()()(

1

kjk

j j

k

kjk

j j

k pF)πf(

pKpFKрВрВ

(10)

where kK - scale coefficient ( ( )kw p ), connect differential input of jth ОA to additional kth system input; )p(F jk - transfer function on output of jth ОA at use of kth input.

Page 3: [IEEE Test Symposium (EWDTS) - Sevastopol, Ukraine (2011.09.9-2011.09.12)] 2011 9th East-West Design & Test Symposium (EWDTS) - Optimal schematic design of low-Q IP blocks

From ratios (9) and (10) it follows that the suc-cess of parametrical optimization by factors kK ( k ) is defined by structural "affinity" of numera-tor polynomials of local functions )( pF jj and

)p(F jk ( k ). The necessary number of k addi-tional inputs depends on this "affinity". Thus, the task (11) generally resolves by search of alternative variants and is connected with procedure of synthe-sis of a set )p(F jk that is difficult enough, even under condition of aprioristic certainty of func-tion )p(F jj . To formalize the present design proce-dure it is possible within the limits of enough sim-ple algorithms reproduced by modern circuit CAD with accessible macromodels of active elements and, specifically, ОA.

The schematic party of modeling stages directed on the search of additional and preferable scheme inputs (k), calculation of real and imaginary com-ponents (9), search of optimum coefficient kK is shown on Fig. 3.

Figure 3. Object of schematic modeling.

Easy to show that: )(sin)(1)(cos)()()( 11 jMMjÂj (11) )(sin)(jM1)(cos)(M)j(FK 22jkk (12)

where

âxjkâxjk

pupu

eueuMuuuuM

argarg)(,mod)(

argarg)(,mod)(

2

1

(13)

The specified ratios are adequate to an optimiza-tion problem provided that in the scheme 1 are used idealized ОA (models of the first level), in the scheme 2 are applied real ОA (models of the third level with wished and f1), and in the scheme 3 only one model of the third level in chosen (jth) ОA is used. As to a source of input signal вxe in the scheme 3 it is connected with additional (kth) input of the scheme. Pointed functions in ratios (13) and (14) are amplitude-frequency and phase-frequency characteristics of experiences or on the basic outputs of schemes 1 and 2, or on an output of scale amplifier.

The measurements that are done on specified ratios allow to generate target functions of paramet-rical optimization:

min)(cos)(M1)(cos)(M 21 (14) min)(sin)(M)(sin)(M 21 (15)

when select 0K0 is provided by operating frequency range ( ) minimization of real (14) and imaginary (15) function component (10).

The offered procedure can be used repeatedly, applying in the scheme 2 most effective compen-sating feedback. Ranging of preferable inputs k and jth ОA can be carried out by increase in volumes (the scheme 3) at schematic modeling, and a choice of a preferable variant – on a minimum of estima-tions (14) and (15).

5. Synthesis example of low-pass filter with cancellation

Let's consider application of the present algo-rithm for schematic circuit synthesis of third order the low-pass filter (LF) with normal D-elements (supercapacities). Such variant of realization pro-vides low parametrical sensitivity of the filter to passive elements instability in a pass-band. Be-sides, realization of supercapacity on the basis of two ОA allows to minimize zero drift at the mini-mum sensitivity of parameters (Fig. 4a).

Figure 4. Third order LF: a) with low zero drift; b) drift-

stabilized. Let's notice that Q factor of complex conjugate

pole in this filter makes 1,41 and, hence, at ARC-realization the dominating parameters defining in-fluence of active elements on accuracy of realiza-tion are absent [4].

So, at set approximating function of amplitude-frequency characteristic (AFC) unevenness in a pass-band (160 kHz) 0.1dB, influence of ОA1 and ОA2 gain bandwidth ( 1f =5MHz) leads to increase this error to 0.6 dB (Table I).

Use preliminary accentuation (change C by 6%) doesn't provide the decision of a problem under that even synchronous change 1f on 20% leads to ad-ditional AFC error on 0.2 dB (Table. I). Let's notice that to achieve demanded amplitude-frequency characteristic unevenness (σ) at ideal preliminary adjustment of the filter it is possible only increase

1f to 50MHz that finally and leads to increase in a consumption current practically on an order.

For the decision of the general problem of the filter scheme synthesis with cancellation of ОA gain bandwidth influence on unevenness in a pass-

Page 4: [IEEE Test Symposium (EWDTS) - Sevastopol, Ukraine (2011.09.9-2011.09.12)] 2011 9th East-West Design & Test Symposium (EWDTS) - Optimal schematic design of low-Q IP blocks

band it is necessary with use in structure of D-elements multidifferential ОA to organize loops of self-compensation and cancellation of the "high-order" coefficients influence on filter AFC in a pass-band and to calculate possible variants of co-efficients К1 and К2 realization (ratio (10)). Appar-ently from a ratio (10) increase of self-compensation level of influence f1 and f2 is possible performance of condition К1=К2=1, thus in the third order LF the stability margin is provided with influence R5, C3. Performance of the specified equality assumes application in structure of D-element МОA1 (К1=1) and МОA2 (К2=1) (Fig. 4b). The relative error increasing of LF boundary frequency (δfb) speaks by reduction unevenness (σ) its AFC in a pass-band.

Modeling results of the scheme (Fig. 4b) show that the basic error of the filter is caused by reduc-tion of the filter boundary frequency (fb) by 25%, allows to receive filter subject to influence of real destabilizing factors (f1=4…6MHz) precisely matched with the ideal filter unevenness (Table. I). And input of additional accentuation provides also the coordination of the filter boundary frequency.

The received results for staircase LF allows to draw following conclusions. First, in cancellation loop of gain bandwidth influence of general ОA it is expedient to use МОA, providing preservation of numerical values of passive elements and removing additional restrictions in the form of inequalities on their face values. However, boundary common-mode voltage and a frequencies range for attenua-tion coefficient of this voltage should surpass LF pass-band. Secondly, use of additional amplifiers practically doesn't change the scheme zero drift.

At last, and this most important thing, efficiency of cancellation loops is defined by numerical value of the maximum Q factor of the filter transfer func-tion poles. If this parameter is close to one that the total effect of cancellation loops can appear insig-nificant that testifies to expediency of revision of filter AFC approximation principle.

6. Conclusion The results received in this work allow to make

a line of methodical and practical conclusions.

First, the concretization of the founded functional and topological principles of purposeful compen-sating feedback loops input can lead to simple rules of schematic design with cancellation for a certain practical problems class. The analysis of target (re-alized) transfer functions, change character of their values and base parameters P structure is necessary for this purpose.

Resulted in work the examples, showing a schemes synthesis technique with cancellation, open the substantial party of design procedures and show possible directions of functional properties perfection of used active elements. As it is shown on Fig. 4b, in circuitry of such devices expediently use multidifferential OA, leaving line additional parametrical limits and essentially changing the general approach to designing of high-sensitivity blocks. Besides, low values of common-mode re-jection ratio in operating frequency range can es-sentially affect on compensating feedback loops working efficiency. From these positions it is nec-essary or developing of OA differential stages and MOA input stages, or application of not differential working initial OA, i.e. go to schemes with "virtu-al" zero.

7. References [1] S. Krutchinsky. Optimization of Sensitivity Domi-

nating Parameters OA in Selective IP Blocks. Pro-ceedings International IEEE EAST-WEST Design & Test Symposium 2010, St. Petersburg, Russia, September 17-20, 2010, p.p. 246-249

[2] S. Krutchinsky, E. Starchenko. Multidifferential operational amplifiers and precision microcircuitry. International scientific-technical magazine “Elec-tronics and communications”, №20,2004,p.p. 37-45.

[3] S. Krutchinsky, M. Tsybin, A.Titov. Differential and multidifferential operational amplifiers input stages with high common-mode rejection ratio. Col-lected papers of 4th All-Russian scientific and tech-nical conference «Design problem of perspective micro- and nanoelectronics systems – 2010» (MES-2010), IDPM RAS, 2010. p.p.537-541.

[4] T. Chang, Y.Chu C.Jen. Low Power FIR Filter Re-alization with Differential Coefficients and Inputs. Circuits and Systems II, IEEE Transactions, 2000, N21 p.p. 137-145.

TABLE I. Modeling results of D-element Parameters Scheme

Scheme parameters OA pa-rameters

Accen-tuation

Scheme elements

fb σ δfb λ f1 δC R1=1.088k R2=1.088k С1=1nF С2=1nF С3=1nF R3=2k R4=2k R5=0.516k ОA µ=125dB

kHz dB - dB МHz % Ideal scheme 160 0.1 ∞ -40 ∞ 0

Scheme with real OA (Fig. 4a)

160 0.6 0 -30

4 -6 161 0.485 +0.6 5

161 0.408 +0.6 6 Scheme (Fig. 4b) with compensation loop by one

MOA (К2=0, К1=1,45) 159 0.17 -0.6

-51 4

-22 163.5 0.13 +2.2 5 167.2 0.101 +4.5 6

Scheme (Fig. 4b) with compensation loop by two MOA (К2=1, К1=1)

156 0.05 -2.5 -51

4 -25 161.9 0.045 +1.2 5

167 0.03 +4.4 6