Configurable Architecture for Memory BIST

Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi CAD Research Group, ECE Department, University of Tehran, Tehran 14399, Iran

{atieh, pani, navabi}@cad.ut.ac.ir

Abstract

The number of memory components in today’s chips

is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed. 1. Introduction

As almost all system chips contain some types of embedded memory, memories are considered as one of the most universal cores. According to the ITRS 2005 the memory part grows faster than the logic part in SoC (logic part 15% per year, versus, memory part 26% per year for total logic). Therefore, the embedded memory becomes the largest and essential part of SoC.

Both the number of embedded memory cores and area occupied by memories are rapidly increasing on system chips. The yield of on-chip memories thus determines chip yield [2]. As a result, testing of embedded memories is receiving growing attention from the industry.

One of the best solutions for memory testing is memory BIST. Due to the chip area constraints, having a configurable memory BIST architecture that can test different memory configurations is important. In this paper such a configurable architecture is proposed. The proposed architecture has enough flexibility for applying different test algorithms.

The rest of this paper is organized as follows: Section 2 overviews the supporting memory test algorithms. Section 3 presents the proposed configurable architecture for memory BIST. Section 4 presents the hardware implementation of the proposed

reconfigurable architecture for 3 known algorithms, and conclusions are drawn in the last section.

2. Supporting Algorithms 2.1. March based algorithms

March test techniques are the dominant test algorithms that are currently implemented in memory BIST hardware. March-based tests are all simple and have good fault coverage.

A March test is a sequence of read and write operations that is applied to every memory cell in either ascending or descending memory address order. Some of the March sequence algorithms are presented in Table 1 using Van de Goor notation [3] (Where wx and rx means write x to a cell or read an expecting x value from a cell, ↑ and ↓ denote increasing memory address order and decreasing memory address order respectively, and ↕ denotes that address order can be either ascending or descending). The complexities of these algorithms are also shown in this table. Table 1 – March Test Algorithms and their complexity

We explain March C- algorithm here, using an example n x 1 memory (with n rows and 1 bit words). This algorithm begins with writing 0s in every memory location. Then it starts reading from location 0 in ascending order and checks if 0s are actually there and then increases the cell content by 1. These operations

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continue until the last bit of the memory. Again, it starts reading from location 0 in ascending order. This time the read expecting value is 1 which is replaced by a 0. After doing the same operation for all the memory cells, the process will be reversed. It reads 0s in descending order (starting from N-1 location), and switch each read location to 1. The same test is then repeated in descending order. The read expecting value is 1 which replaced by 0. Finally the content of every cell is read in any order and check if 0s are actually there.

Hardware implementation of MATS and MARCH C- algorithms are described in Sections 4.1. MATS algorithm 2.2. Disturb algorithm

In the disturb testing, a checkerboard pattern is

written into the entire array in the “disturb write state”. After the data is left to settle, it is read back in the “disturb read state”. If the comparator detects any change in the read data, then a fail flag goes high and stops the test. This is a quick check for gross data retention faults.

Disturb testing is designed to study the robustness of the data storage of the flash or DRAM cells when the state of a neighboring cell is being changed. The change can occur either through writing or reading of a cell. Disturb failures are usually soft failures that require additional device commands to repair. Resistive short paths between memory cells, bit-lines, and word-lines are some common sources of disturb faults.

Finally, it should be noted that for a n x m memory; with n rows and m-bit data, the complexity of algorithm is O (n x m), it is important that for each bit in a row both transitions of 0 to 1 and 1 to 0 are considered.

3. Proposed Configurable Architecture for Memory BIST

Figure 1 shows the proposed configurable memory BIST architecture, the main part of this architecture has been inspired from [1]. The memory to be tested is shown in gray and solid line blocks show the test circuitry. Test data that is to be applied is generated by this MBIST circuitry and applied to the memory. As data is being read from the memory, it is compared with the reproduction of the same data that was written into specific memory locations. After writing and reading all locations, we expect all data read from the memory to be the same as those that were written into it.

Figure 1 – Configurable Memory BIST Architecture

In Figure 1 dataSize, adrSize and countSize are the number of bits required to represent data, address of memory, and the address counter, respectively. The architecture we presented applies to large memory chips, as well as short on-chip register files.

With this architecture, it is just necessary to set the desirable test algorithm and size of memory (width and length) in the script file. As the architecture is fully configurable, all memory parameters are set automatically. Table 2 shows the possible values for 2-bit TestMethod.

Table 2 –Values for three implemented test method

For disturb and MATS memory BIST algorithms, two multiplexers with select inputs Sel and cen are not used. In this architecture Sel and cen signals are used just for March C- method to specify that if the operation is read or write. The checkVal signal is also considered for march based algorithms which is used when the value written into a cell is different than the value being read. In this case, the read value from memory must be compared with the previous written value.

4. Configurable Architecture Hardware

The main common components for the three algorithms are shown below. Figure 2 shows the general purpose RAM model using the standard IEEE std_logic package. The wr signal in the process statement shown performs writing and reading of the memory.

ENTITY std_logic_ram IS

PORT (address : IN std_logic_vector; datain : IN std_logic_vector; dataout : OUT std_logic_vector; cs, rwbar : IN std_logic; opr : IN BOOLEAN);

END ENTITY std_logic_ram;

-- Architecture of std_logic_ram PROCESS

CONSTANT memsize : INTEGER := 2**address'LENGTH; VARIABLE memory : mem (0 TO memsize-1, datain'RANGE); BEGIN wr: IF cs = '1' THEN IF rwbar = '0' THEN -- Writing FOR i IN dataout'RANGE LOOP memory(conv_integer(address),i):=datain (i); END LOOP; ELSE -- Reading FOR i IN datain'RANGE LOOP dataout(i)<=memory(conv_integer(address),i); END LOOP; END IF; END IF; WAIT ON cs, rwbar, address, datain, opr;

END PROCESS; Figure 2- Unconstrained Memory

The VHDL code of Figure 3 shows the main part of the MBIST structure including the RAM that is being tested. Components instantiated in this description are according to the diagram of Figure 1. In addition to the components instantiated, this code has a process statement that issues the fail flag if the comparator finds a mismatch.

SIGNAL ram_testvalue : std_logic_vector (datain'length-1 DOWNTO 0) := "01111111"; SIGNAL q : std_logic_vector (countSize-1 DOWNTO 0); SIGNAL ramin, ramout : std_logic_vector (datain'length-1 DOWNTO 0); SIGNAL ramaddr : std_logic_vector (address'length-1 DOWNTO 0); CNTRL : ENTITY WORK.BIST_controller(procedural) PORT MAP (start, rst, clk, cout, Nbar_T, ld); CNT : ENTITY WORK.counter(procedural) PORT MAP (zero, clk, ld, '1', '1', q, cout); GEN : ENTITY WORK.SequenceGen(behavoral) PORT MAP (ram_testvalue, q(countSize-1 DOWNTO address'length), data_t);

MUX_D : ENTITY WORK.multiplexer(procedural) PORT MAP (datain, data_t, Nbar_T, ramin); MUX_A : ENTITY WORK.multiplexer(procedural) PORT MAP (address, q(address'length-1 DOWNTO 0), Nbar_T, ramaddr); rwbar <= rwbarin WHEN Nbar_T = '0' ELSE q(address'length); cs <= csin WHEN Nbar_T = '0' ELSE '1'; RAM : ENTITY WORK.std_logic_ram (behavioral) PORT MAP (ramaddr, ramin, ramout, cs, rwbar, opr); CMP: ENTITY WORK.comparator (expression) PORT MAP (data_t, ramout, gt, eq, lt); -- in a PROCESS statement, check the eq signal, if it is not ‘1’, it highs up the fail signal -- in a PROCESS Statement Compute faulty bit dataout <= ramout; END ARCHITECTURE;

Figure 3 - BIST structure

The BIST controller shown in Figure 4 starts the counter when it receives the start signal and waits for the carry-out (cout) of the counter. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BIST_controller IS

PORT (start, rst, clk, cout : IN std_logic; Nbar_T, ld : OUT std_logic);

END ENTITY ;

ARCHITECTURE procedural OF BIST_controller IS TYPE state IS (reset, test); SIGNAL current : state := reset;

BEGIN PROCESS (clk) BEGIN IF (clk = '1' AND clk'EVENT) THEN IF rst = '1' THEN current <= reset; ELSE CASE current IS WHEN reset => IF start = '1' THEN current <= test; ELSE current <= reset; END IF; WHEN test => IF cout = '1' THEN current <= reset; ELSE current <= test; END IF; WHEN OTHERS => current <= reset; END CASE; END IF; END IF; END PROCESS; Nbar_T <= '1' WHEN current = test ELSE '0'; ld <= '1' WHEN current = reset ELSE '0';

END ARCHITECTURE; Figure 4: BIST Controller

4.1. MATS algorithm

The MATS memory test algorithm is the simplest march test. Details of this algorithm are presented in Table 1. In this method, in order to generate test sequences, the module uses the counter output to determine which value must be written in the memory cells if the current operation is writing to memory. It also generates the last written value in the memory for comparing with the read value if the current operation is reading from memory. Since the memory word length can be more than 1, the write and read operations must be done for all existing bits in the memory word. So initially all four operations of MATS algorithm (writing 0 in all cells with the same bit position, reading 0 and then writing 1 in every cell before moving to the next cell with the same bit position and reading 1 from all cells with the same bit position) is done for all most significant bits of memory word and then these operations repeated for all other bits of memory words until reaching to the least significant bits.

Figure 5 shows the process statement which is used as the sequence generator in this method.

PROCESS (input) VARIABLE shiftAmount : INTEGER; VARIABLE tempshift : bit_vector(output'range) := (output'left=>'1', others=>'0'); BEGIN IF (cen='1') THEN shiftAmount := CONV_INTEGER(

input(LogDataSize+1 DOWNTO 2)); IF (input(1 DOWNTO 0)="00") THEN output <= (output'range=>'0'); ELSIF (input(1 DOWNTO 0)="10") THEN output <= To_StdLogicVector (tempShift SRL shiftAmount); END IF; IF (input (1 DOWNTO 0) = "01" OR input(1 DOWNTO 0) = "10") THEN lastValue <= (output'range=>'0'); ELSIF (input(1 DOWNTO 0) = "11") THEN lastValue <= To_StdLogicVector (tempShift SRL shiftAmount); END IF; ELSE output <= (output'range=>'Z'); END IF; END PROCESS;

Figure 5 - MATS memory BIST pattern generator

4.2. March C- algorithm

The March C- algorithm is the one of the March test methods which detects almost all memory faults. This

algorithm was explained in section 2.1. The implementation is very similar to the MATS method (which is described above) but the number of read and write operations are more than MATS method. (i.e. 10 consecutive operations for each memory cell instead of 4 operations in MATS method).

Figure 6 shows the PROCESS statement which is used as pattern generator in this method.

PROCESS (input) VARIABLE shiftAmount : INTEGER; VARIABLE tempshift:bit_vector(output'range):=(output'left=>'1', others=>'0'); BEGIN IF (cen='1') THEN shiftAmount := CONV_INTEGER(

input(LogDataSize+3 DOWNTO 4)); IF (input (3 DOWNTO 0) = "0000" OR input (3 DOWNTO 0) = "0100" OR input (3 DOWNTO 0) = "1000") THEN output <= (output'range=>'0'); IF (input(3 DOWNTO 0) = "0000") THEN lastValue <= (output'range=>'0'); ELSE lastValue <= To_StdLogicVector (tempShift SRL shiftAmount); END IF; ELSIF (input (3 DOWNTO 0) = "0010" OR input (3 DOWNTO 0) = "0110" OR input(3 DOWNTO 0)="0101") THEN output <= To_StdLogicVector (tempShift SRL shiftAmount); lastValue <= (output'range=>'0'); END IF; IF (input (3 DOWNTO 0) = "0011" OR input (3 DOWNTO 0) = "0111") THEN lastValue <= To_StdLogicVector (tempShift SRL shiftAmount); END IF; ELSE output <= (output'range=>'Z'); END IF; END PROCESS;

Figure 6 - March C- memory BIST pattern generator

4.3. Disturb algorithm

In this method, a test sequence generator is a simple rotate circuit. At the first, an initial value will be written to all memory cells, and after that as the data is being read from the memory, it is compared with the written data, for the next step, it is necessary to rotate the initial value one bit to the left and then this data is considered as a new test pattern, continuing this process until check both transition 0 to 1 and 1 to 0 for each memory cell which is resulted from rotating the initial value with size of data in each row of memory.

After writing and reading all locations, we expect all data read from the memory to be the same as those that were written into it.

The VHDL code of the sequence generator is shown in Figure 7.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- ENTITY and ARCHITECTURE definition of sequence generator PROCESS (sel)

VARIABLE ram_initialTestValue : BIT_VECTOR (output'RANGE) := (output'left=> '0', OTHERS => '1');

BEGIN

output <= To_StdLogicVector (ram_initialTestValue ROL CONV_INTEGER (sel));

END PROCESS; Figure 7 - Disturb memory BIST pattern generator

As the three above figures show the sequence generator is completely different for each 3 methods, and the test algorithm which has been read from script file determines which sequence Generator must be executed.

Finally, whole of circuit included the memory and its BIST are tested in the architecture of the BIST_Tester testbench. This testbench is shown in Figure 8. This testbench has been presented in [1]. The testbench initially loads external file data into the memory at time 5 ns when operate becomes TRUE. Then at some arbitrary times data is written into and read from the memory. The BIST test session begins when start becomes 1 at time 50 ns. Testing continues until all RAM locations have been tested. While the memory is being tested, external read and write operations are ignored.

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL;

ENTITY BIST_tester IS END ENTITY BIST_tester;

ARCHITECTURE timed OF BIST_tester IS SIGNAL ramin, ramout : std_logic_vector (7 DOWNTO 0); SIGNAL addr : std_logic_vector (5 DOWNTO 0); SIGNAL cs, rwbar, start : std_logic := '0'; SIGNAL rst, fail, clk : std_logic := '0'; SIGNAL operate : BOOLEAN; BEGIN UU1: ENTITY WORK.BIST (structural)

PORT MAP (start, rst, clk, cs, rwbar, operate, addr, ramin, ramout, fail);

clk <= NOT clk AFTER 5 NS WHEN NOW <= 800 NS ; operate <= TRUE AFTER 5 NS, FALSE AFTER 800 NS; cs <= '0', '1' AFTER 15 NS, '0' AFTER 337 NS; rwbar <= '1', '1' AFTER 190 NS; addr <= "101100" AFTER 020 NS, "101110" AFTER 040 NS; ramin <= "11110001" AFTER 010 NS, "00101100" AFTER 030 NS; rst <= '0'; start <= '0', '1' AFTER 50 NS;

END ARCHITECTURE timed; Figure 8: Memory and BIST Testbench

5. Conclusions

In this paper, the configurable architecture for memory BIST has been proposed, simply and completely consistent with this architecture, 3 famous methods of memory test algorithms have been implemented and adding other algorithms can be done easily. We used VHDL as a hardware language to implement the proposed configurable architecture. As VHDL allows the declaration of unconstrained arrays, all of the components in Figure 1 are unconstrained, which is particularly useful for developing generic descriptions or designs. The bounds of unconstrained arrays used for formal parameters are determined according to the actual parameters that are associated with them in the testbench. 6. References [1] Z. Navabi, VHDL: Modular Design and Synthesis of Cores and Systems, McGraw-Hill, Boston, 2007. [2] L.T. Wang, C.W. Wu, X. Wen, VLSI Test Principles and Architects, Elsevier Inc., United States of America, 2007. [3] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, Chichester, UK: John Wiley & Sons, Inc., 1991.