The Testware CAD

Victor Zviagin, Saint-Petersburg National Research University of

Information Technologies, Mechanics and Optics (ITMO), Victor_Zviagin@mail.ru

Abstract

ATPG (Automatic Test Pattern Generation) for arbitrary digital circuit is not possible without previously verification feature been realized at first and without testability been estimated and changed to appropriate level as second. ATPG for arbitrary digital circuit is not possible without hazard free sequences generation at third. At forth ATPG is divided into two versions: for verification test pattern generation and for hardware test pattern generation. CAD combined all four listed features is denoted as the Testware CAD. Our Testware CAD provides Design for Test & Test for Design technology (in brief DFT & TFD). Data about such kind system are described here and more completely at site http://twcad.ifmo.ru 1. Introduction

TestWare (Tw) is a new collective term and software system (TwCAD) based on cheap IBM-PC platform. TwCAD generates and supports testware for all phases of IC's lifecycle: project verification, design for testability, test design, production and user testing.

2. TwCAD's Unique ATPG & DFT Features

The TwCAD differs from other systems through

combination of testware generation and maintenance, as well automation of design of testable modifications and race- and hazard-free test sequences. Since 1979 TwCAD has generated thousands of tests for arbitrary integral circuits. Two problems arose: 1) circuit dimension growth - solution to that is porting the TwCAD to Windows operating system from DOS and porting the TwCAD code to Linux for cluster; 2) it is well known that test design costs depend not so

much on circuit dimension as on its testability - the second problem is of confidential nature: how to incline the designer to implement the testable modifications suggested? Voluntariness is not effective enough because of emerging vagueness; a more systematic approach is required. Such an approach was suggested by Joint Test Action Group (JTAG). JTAG incorporates over 200 leading manufacturers and consumers of microchips and other devices. Participants agreed to use a unified test architecture, four-wire test protocol and microchip compatibility. To implement JTAG architecture four supplementary pins and some additional circuitry are needed.

The TwCAD actualizes design for test concept in the newest Testware technology which implies the following role assignment between designer and the Tw system: - Designer creates a circuit project and debugs it using verification test created by the system or manually by designer; - TwCAD predicts ATPG fault coverage based on controllability and observability measures and generates recommended testable modifications; - Designer determines the style of testable modifications (Ad-hoc style in which the TwCAD provides recommendations for circuit modification or JTAG-style in which the TwCAD provides location and type of test points for additional observability and controllability. Designer has to implement JTAG architecture elements only once on circuitry selection). To provide testability and fault coverage, designer has only to control the amount of additional hardware. The TwCAD generates hardware test and creates files for tester. The TwCAD recommends hardware and software needed to check boards, LSI, gate arrays, PLDs, etc.

Although JTAG standard provides design for testability environment, it does not provide design for testability tools. That is where the TwCAD comes in. It guarantees solutions for all testware generation tasks: the TwCAD drives circuit into testable form,

978-1-4577-1958-5/11/$26.00 ©2011 IEEE

automatically generates high quality test at affordable costs and directs it to tester.

It's worth noting that full-scale JTAG architecture incorporates large-capacity boundary scan registers. Thus, the amount of additional hardware may exceed admissible level. The TwCAD provides a solution for this problem too, using only restricted scan register. It introduces points into circuit where register bits must be placed to increase controllability and observability. Combined with hierarchical structure of design for testability, it allows decreasing additional hardware amount by more than an order while maintaining ATPG. This is only achieved due to unique analytical capabilities of the TwCAD. As nomenclature of ICs, LSI and JTAG microprocessors expands, application area of the TwCAD expands too because TwCAD actively utilizes scan chains to simplify test generation.

3. TwCAD - General Information

Number of releases of the TwCAD is 18 (in 1979

for EC-computers, in 1989 for IBM/PC DOS, in 1993 for WINDOWS 3.1, in 1997-2002 for WINDOWS-NT/95/98/2000/XP, in 2006 for web-online with PHP, now it is redeveloped for cluster). System software is implemented in FORTRAN-95 and PHP languages. The TwLab is controlled via Internet. Code size is about 120,000 statements. Software can be ported to workstations or clusters. Programs require 30 MB of hard disk space, help files and documentation require additional 3 MB.

Data for TwLab. We don't know all about board offered by you to the TwCAD and don't ask you to deliver like following:

- board functions; - its clock or clocks; - pins are to be in or out or inout; - multisources or complex nodes, relays; - high impedance, tri state pins; - resistors transforming High Impedance to

VCC; - Where are FF and what types are they of ? - Are there sets, resets, etc, registers, counters?

Fortunately such kind information is been found by the TwCAD automatically. The only needed is usual Netlist to describe interconnections of parts and ports.

Three sample lines of our TwCAD’s Netlist are below: space in the fist position needed for non-comment line (elsewhere spaces are available except names). Board name is at 1-st line of description: Board:C31; 04-D3: 3/e; port-a:9/e;

Node named e consists of pin #3 of part D3 of type 04 and pin #9 of port A.

Thousands of tests for sequential circuits have been designed automatically and applied in engineering setup. Examples include airborne computers for spaceships, including Soviet space shuttle "Buran". 4. Original Basic Concepts

Achievable fault coverage percentage depends on testability and is predicted by the TwCAD before test generation. If verification is successful and good coverage is predicted the TwCAD guarantees high-quality test generation at moderate time for a non-redundant circuit. If prediction turned out bad the TwCAD simulates possible testable modifications and selects the optimal ones. If designer implements them automatic generation of high quality test becomes available. Advantages of the TwCAD supplement CADs used on IBM-PC. A CAD usually includes circuit editor, fitter, traceroute program, timing simulator like MR-CAD, MAX PLUS II, OrCAD, DixiCAD, KONDICIA, PCAD or others. The TwCAD adds such features as testability analysis, deterministic ATPG and fault coverage analysis. Combining with customer's system is realized on demand to successfully resolve the full range of digital circuits design tasks. The TwCAD provides ATPG for comprehensive checkup of LSI, PLDs, PBs, gate arrays, etc. The Testware includes project verification tests, buses contra tests, tests for comprehensive testing of produced circuit and additional hardware for testability. The TwCAD is designed to interface with other CADs at input (circuit description) and with CADs and testers at output (test generated). For this reason the TwCAD includes flexible programming interfaces to provide quick transformations from/to user formats. 5. About Good Circuits

To generate test or prior testable modifications, we need your circuit Netlist which is the only data needed. There are to be described for your circuit: its name, ports, parts and nodes. E.g. Altera's products contain complete set of descriptions in the internal *.rpt file. We do not need timing information, source project library, functional scheme and so on. Netlist extracted from *.rpt file is the only data needed. Remember - we can produce test automatically under conditions below: - circuit is testable enough for the TwCAD; - verification is OK; - circuit is irredundant;

- any bus (if any exist) at any moment has the only source (if any);

- it is possible to isolate a pulse generator (if any exist);

- it is possible to isolate any CPU element (if any exist);

- it is possible to address any RAM (if any exist) from external pins.

6. Benefit of Verification Test (Optional Yours or Optional Ours)

It is very important for automatic Test Generation System that the verification test is to be submitted to check model. The ATPG can produce a test of arbitrary circuit but you want maintain your circuit only. If you have such verification test then let us send too to verify model. On the contrary if you want let us do generate the verification test automatically to send it for your analyzing. We can check consistency of all buses of your circuit as well. At first we find all sources in each bus. Than we try to search any pair of signals compatible at the same time in any bus. If it is possible then appropriate bus is inconsistent. We shall send you such contra examples too. In ATPG process accidentally checked faults are marked in every segment.

7. Test Generated with the ATPG for "As Is Circuit"

The TwCAD offers simple principle: "your circuit –

our test”. It would have fault coverage not more than that usually predicted. Test is automatically generated for whole arbitrary circuit (it contains loops, complex nets, buried flip-flops, etc.) in opposite to the single chip of restricted structure traditionally. Test is subdivided to set of segments which are applied to UUT independently. Every segment consists of well-ordered patterns. Every segment is hazards free not only for the good circuit but for the detected faults as well. Every segment covers at least one new fault. Every segment is supplied with reset or initializing sequence. In ATPG process additional faults are covered symmetrically in some segments if it is possible. The ATPG uses time-restricted procedure guided by controllability measures. We transform test to the needed format MAX-II Plus, PCAD, DixiCAD, Mr-CAD. etc. List is to be continued. We produce too: - DFT report; - report on obstacles to reach high fault coverage; - list of undetectable faults;

- fault coverage report; - as additional feature logic verification test; - as additional feature bus inconsistency contra test.

8. Test Generated with Technology DFT&TFD

We keep technology DFT&TFD:

1) you offer testable circuit and we estimate it and recognize this fact. No obstacles to ATPG arisen than high quality test are generated automatically;

2) you offer untestable circuit but we estimate it and recognize this fact and recommend testable modifications. You transform circuit under recommended modifications and go to situation 1)

3) you offer not good circuit, see div. 5, but we recognize this fact and recommend to delete obstacles, and go to situation 2) 9. United Table with Results of ATPG for ISCAS-85, 89, 99 Benchmark Circuits

We have carry out ATPG for benchmark ISCAS-85, 89, 99 circuits, see Table 1. You can try do repeat this yourself via site http://twcad.ifmo.ru directly - if you want. Circuits in column 1 are ordered as at the source site - upon volume growth, see column 2. Table column 3 contains the ATPG times in seconds (note h is “hours” in below table column 3) corresponded to execution with web-site http://twcad.ifmo.ru based on 1.7gH Intel Celeron CPU, 166mH, 1gb RAM. Denominator of column 3 is number of time restrictions exceeded, absent one corresponds 0. Efficiency of ATPG procedure is measured, see column 4, as well the ATPG time, see column 3. Test length is presented at column 5, segments/patterns; test is subdivided to independent subsequences (segments) consisting well ordered patterns. Fault coverage reached, see column 6 in the real-life ATPG process does not exceed predicted one, see column 7. It is well known that testability order is other (see column 7). Column 7 contains prediction P=C*Ob*V*100%, where C-controllability - part of bits upon this measure from the zone of the sure ATPG, Ob-observability - part of bits upon this measure from the zone of the sure ATPG, V-verification rating - part of bits from the zone of the sure ATPG. Note that our prediction is optimistic and is near 100% level. For circuits of great volume there are no problems to use cluster for ATPG - circuits have simple structures which should been parallelized simply by cluster.

Table 1. Results of ATPG.

1 name

2 volume

3 Time

4 Effec-tiv-ness

5 Test length

6 Fault coverage

7 Prediction

gates/ gates per out

sec./ pieces % Segment/

pattern % P %

ISCAS-85 circuit names started with "c"

432 160/22 68/3 4 58/81 97 100

499 160/22 69/3 4 58/81 97 100

880 160/22 68/3 4 58/81 97 100

1355 546/17 225 1 80/110 94 100

1908 880/35 2339/737 .2 126/226 95 100

2670 1193/29 40/3 38 253/471 82 1*0.9*1*100

5315 2307/24 599/68 5 456/890 93 100

6288 2416/75 1182/262 .4 58/111 100 0.4*0.2*1*100

7252 3512/57 880/49 2 213/392 88 1.*0.9*1. *100

ISCAS-89 circuit names started with "s"

208 96/9 1 63 35/69 93 100

298 119/8 3 100 53/106 98 100

344 160/8 1 100 45/80 98 100

382 158/7 1 100 41/81 98 99

386 159/12 1 100 41/81 98 100

400 164/7 1 100 49/95 99 100

420 218/12 6 37 71/138 84 100

444 181/8 1 100 44/86 98 100

510 211/16 23 16 50/92 99 100

526 193/9 3 99 81/161 98 100

641 379/9 4 100 100/175 99 100

713 393/9 4 99 60/108 96 100

820 287/11 3 99 103/206 97 100

832 287/11 6 99 73/146 96 90

838 446/13 17/4 6 110/218 72 100

953 395/13 60 32 99/176 99 100

1196 529/17 96/3 16 170/289 99 100

1238 508/16 193 7 169/288 96 100

1423 657/8 49 98 206/407 97 100

1488 653/26 46 83 113/211 98 100

1494 647/25 47 84 109/206 99 100

5378 2779 379 79 467/893 97 99

9234 5597 960/26 3 495/956 96 100

13207 7951 1774/47 1 846/1673 96 100

15850 9772 6h/1522 0.1 1030/2009 95 97

35392 16065 12 h 100 3121/6128 97 100

38417 22179 7 h 63 2908/5329 97 100

38584 19253 16 h 2 2317/4528 88 85

ISCAS-99 circuit names from Torino started with "b"

1 Name

2 volume

3 time

4 Effec-tiv-ness

5 Test length

6 Fault

coverage

7 Prediction

gates/gates per out

sec./ pieces % Segment/

pattern % P %

03 122/4 2 100 77/153 95 100

04 652/9 346/72 2 216/424 95 100

05 927/15 291/73 2 105/198 76 0.9*0.8*0.9*100

06 39/4 1 100 18/36 100 100

07 383/14 91 2 159/301 94 100

08 149 6 4 92/168 94 P=V=98

09 140/5 2 100 82/164 96 100

10 172/10 3 100 94/188 99 P=V=96

11 726/23 107 12 132/251 90 100

12 944/8 369 81 333/666 98 100

13 289/5 8 89 110/219 98 100

14 9767 15h/1730 1 512/953 66 0.9*0.4*1*100