Parallelizing of Boolean Function System for Device Simulation

Alexander Chemeris,

G.E.Pukhov Institute for Modeling in Energy Engineering, Kiev, Ukraine

a.a.chemeris@gmail.com

Svetlana Reznikova G.E.Pukhov Institute for Modeling in Energy Engineering, Kiev, Ukraine

sreznikova@ukr.net

Abstract

The representation of digital circuits that are

designed by Boolean functions is considered. The syntax of Boolean function we use is presented. This digital circuit representation in the form of data-flow graph is used as a basis for parallelizing of simulation process for multiprocessor computers. 1. Introduction

During digital device design the parallel technic becomes very important approach to decrease the development time. The using of parallel computers such as multi-core architectures, GPUs, special purpose computers or MPI-clusters is the great direction for research and new EDA tools development.

A creation of Boolean function graph is very important task for the parallelizing of logic systems during simulation of logic circuits. It has some features we have to take into consideration and will describe in this paper.

The first chapter describes logic devices and them Boolean function representation. The next one is devoted to features of Boolean functions graph. These features determine an algorithm of graph creation and parallelizing. An example is presented in the last chapter. 2. Logic devices and Boolean functions

In general, digital devices may be represented as three parts. The first part L1 and the third one L2 are logic units and the unit M is the sequential circuit with memory elements. These parts are shown on Fig. 1 where the device has Xi inputs and Yj outputs. Q(t-1) are the outputs of sequential circuit and the index t-1 means that Q belong to the cycle t-1. D(t) is the value of sequential circuit input belonging to the cycle t we consider. Clk is the clock input.

Figure 1. The general scheme of a digital device

Any digit device may be described as a system of

Boolean functions taking into account the fact that signals on input and output are separated in the consecutive cycles [1].

Figure 2. An example: Two cells of a

register

L1

M

L2

XiYj

D(t) Q(t-1)

Clk

978-1-4577-1958-5/11/$26.00 ©2011 IEEE

As an example that have to show the format of

Boolean function we use, let’s consider a logic circuit of a register that have two data inputs ai and bi.

For the simulation of this device we describe it by the system of Boolean functions where ‘|’ is OR operation, ‘&’ is AND operation and ‘!’ is NOT one. This system for register on Fig. 2. is shown on Fig. 3.

NT1 = !T1; NT2 = !T2; NQ1(t) = !(b1&NT2|a1&NT1|T1&T2&Q1(t-1)); NQ2(t) = !(b2&NT2|a2&NT1|T1&T2&Q2(t-1)); Q1(t) = !(!S1& NQ1(t-1)); Q2(t) = !(!S2&NQ2(t-1));

Figure 3. The system of Boolean function for device on Fig.2

In general, systems of Boolean functions we may

present as the following expression

);,...,,,,...,,(2121 mn

FFFxxxF (1)

where is the set of complex logic functions with AND, OR and NOT operations.

A main goal of the automatic parallelizing is the partitioning of the system (1) and scheduling of blocks of logic equations on several processors. It is very important to realize an interchange of data between processors. So we need the graph of Boolean function system to solve the problem of Boolean functions partitioning. The graph defines links between equations and we may define the sequence of their execution on a processor and the order of data interchange. Further we consider some features of Boolean functions and graphs described them.

When we realize the simulation process, we use two steps of parallelizing. First of all we need to create a graph consists of nodes and arcs describing dependencies between nodes. This graph represents the system of Boolean functions, which describes designing device. During the second scheduling step we plan the tasks for every processor of multiprocessor computer using for simulation. For high quality parallelizing we have to keep two principles during scheduling. The first one consists in guaranteeing of processor balancing and the second one have to minimize inter-processor communications. Describing some graph features we suppose that we will use distributed computer systems for simulation. The next statement we use consists in the following. We guess one node of graph presents one Boolean function. So the way to solve the problem of graph creation consists

in retrieval of dependencies between Boolean equations.

Considering distributed computers that don’t have common memory we don’t need to consider some graph dependencies such as output dependencies and anti-dependencies taking into account in computer systems with common memory. So we consider only data dependencies for Boolean equations. But we have to remember that designing device has feedbacks that lead to cycles in the graph.

As an example let’s consider the circuit with feedback on the Fig.4.

a)

Q = U1(X1, Y); R = U2(X2, Q); Y = U3(X3, R);

b) Figure 4. An example of feedback: a) circuit,

b) system of functions.

This device consists of three units that realize complex logic functions U1, U2 and U3. As we can see the circuit Q→R→ Y→Q makes a loop both in the real device and in the system of Boolean functions and in the graph accordingly. Parallelizing of such sub-graphs makes the task of scheduling more complex and it leads to appearance of multiple inter-connections between data in various processors. Algorithms of processor task balancing will demand to put these sub-graphs into the same processor. So it will be right to put these nodes of graph on the same level.

The system of Boolean functions defines the structure of digital device. There is no meaning what order of Boolean functions we have. Designing device will function right regardless of the order of equations. So constructing graph we don’t take into view the lexicographical order of the functions. We must to look for dependencies of each node with the nodes both before and after current node.

The main feature of the Boolean function system is the following. Analyzing memory elements (flip-flops) we have to consider dependencies of another type. They define the using of memory elements on the next cycle but not now. So the example above (see Fig. 3) shows such dependence in equation Q1(t) = !(!S1&

U1 U2 U3

Q R

Y

X1 X2 X3

NQ1(t-1)); where it is distinguished the variables Q1 in the left part and the variable NQ1 in right part. The value of Q1 in the left part is regarded to the cycle t but NQ1 in the right part is regarded to the t-1 cycle. There are various variables which may be paralleled in time but we have to take into consideration that the value of NQ1(t) have to be forwarded to Q(t-1) by another function. So it is important for inter-processor exchange. We will call such sort of dependencies as dependencies of second kind.

So we may formulate an algorithm of Boolean equation’s transformation for calculating on a parallel computer. We make numbering of graph nodes taking into view that one Boolean equation corresponds to one graph node. We calculate workload on processor for every node of graph. We need such information to balance parallel processor’s work. There are defined data dependencies for every graph node. Here we define the second kind dependencies too. There are defined cycles in the graph and they are joined into complex nodes. So we get the acyclic graph. Using information about dependencies we assign the graph nodes to levels. There are used any scheduling method to plan graph nodes to processors of multiprocessor system.

3. Example

Figure 5. Graph of Boolean function system

for device on the Fig. 2.

Continuing the example on Fig. 2 we represent the graph for this system of Boolean functions on Fig. 5. Here the second kind links are represented by dotted lines. Practically the nodes 3, 4 may be performed in

parallel with nodes 5 and 6. But if the nodes 3 and 5 will be placed on various processors during scheduling then the variable Q1 have to be forwarded from processor with node 5 to processor with nodes 3. The same situation obtains with nodes 4 and 6. 4. Conclusions

Parallelizing is the way to decrease the time of digital device’s simulation and the design time accordingly. One of the tasks we need to solve is the creation of Boolean functions graph. If we have the graph then we may use any scheduling method to plan the work of every processor of multiprocessor system. One of such methods is described in [2]. So the graph creation is the very important process.

The creation of Boolean functions graph has some features we need to take into consideration. These features allow to increase the paralleling level and to build the right program for graph creation.

Our group has made the program, which create the Boolean functions graph. This program uses the unique inner data structure to decrease the time of program work. There is very important to simulate large systems of Boolean functions describing real FPGA projects. 5. References [1] W. Bielecki, P. Jaworski “Generating Boolean equations for synchronous-asynchronous logic described in VHDL language.” Advanced Computer Systems ACS’2000, Szczecin, Poland, 2000.- pp. 397-400.

[2] W. Bielecki, A. Chemeris, S.Reznikova “Parallel Simulation of Boolean functions by Means of GPU.” In Proceedings of East-West Design and Test Symposium EWDTS’2009, Moscow, 18-21 September 2009. – pp.162-164

2

T1 a1 b1 !S !S a2 b2 T2

1

3 4

5 6

Q2 Q1 NQ1

NQ2

NT1 Q2(t-1) Q1(t-1)

NQ2(t-1)NQ1(t-1)

NT2