Electromigration Testing on Via Line Structiires with Fast Wafer Level Tests

In Comparison to Standard Package Levell Tests

Anke Zitzelsberger, Robert Bauer, Jochen v. Hagen, Marco Lepper, Andreas Pietsch Infineon Technologies AG, Otto-Hahn-Ring 6, D-8 1739 Munich, Germany

Phone: + 49 89 234 46733, Fax: + 49 89 234 45822, E-mail: anke.zitzelsberger@infineon.com

Abstract

Experimental results show a good correlation between fast wafer level tests (WL) and conventional standard package level (PL) tests on via-line structures. Failure analysis show the same failure mechanism and no differences in the shape factor of the failure distributions. Similar tSON values are obtained, after extrapolating the data to operation conditions. As a consequence fast wafer level tests can not only be used for monitoring but also to quantify the reliability of metallization, if suitable stress condition are used.

Introduction

So far little trust is put in lifetime projections from highly accelerated wafer level electromigration tests, on deep sub- micron via-line structures. This is mainly due to a missing correlation between the highly accelerated wafer level tests and the conventional package level stress techniques. The failure times of lines stressed by these methods are usually in the order of tens of seconds. Therefore, highly accelerated wafer level tests are mainly used for process control (monitoring), in contrast to those electromigration tests, with milder stress, that are used to assess the interconnect reliability quantitatively (tens of hours), so far on PL. To ensure rapid and cost-effective reliability feedback during technology development we want to find out if and how highly accelerated tests can be used not only for monitoring but also for a more quantified approach in reliability testing. In order to do so, two types of fast wafer level tests using an improved SWEAT (Standard Wafer Level Electromigration Accelerated Test) algorithm [1,2] and an improved isocurrent test [3] were performed on via-line structures. The test conditions are varied in such a way that failure times range from hundreds to thousand of seconds. The data are compared to conventional Package Level (PL) tests with isocurrent stress.

Experimen tals

Improved S WEA T algorithm The idea of the SWEAT test is to control the target time to failure as estimated in Black’s Equation. This time-to- failure serves as a measure of the severity of the stress. In the control loop, a current density and temperature is found which attempts to maintain a constant target failure time.

An appropriate control is developed to avoid over- and undershoots in the stress current, as was the case for Jedec 119 [1,4,5]. The line temperature (TIme) due to Joule heating is determined by means of the dissipated power and the’ thermal resistance (R,,,) during the initial phase of each test. Here stress temperatures are obtained between 180°C and 27OOC for current densities of 350 - 400mA/pm2 leading to failure times of 50- 3000 sec in contrast to tens of seconds for monitoring tests. Although the algorithm controls the target failure time, the current density during the test and though the temperature v8aries less than 1% except of the last few seconds of the tesit. For the later extrapolation, the median line temperature TI^,,^,^,,) and current density is used.

Isocurrent Wafer Level and Package Level test The test routine for both PL and WL is a constant current stress at elevated temperature. The temperature level is preset by oven and chuck temperature respectively. The line temperature (Tline) due to Joule heating is determined via the temperature coefficient of resistance, during the initial phase of each test. Here oven/chuck temperatures of 25O/26O0C are used. The current densities vary between 5-10mA/pm2 for PL and 40-100mA/pm2 for WL leading to failure times of 0.1 - 0.3 h for WL and 50-120h for PL.

T a t structure The test structure consist of a C1 tungsten plug and a 100pm long nested M1 metal line with Ti/TiN barrier layers. The electron flow is upstream through C1 into M1, as can be seen in Fig. 1 .

Fig.1 Test structure; left: top down, right: side view, arrow indicates electron flow direction

Results

Failure distribution Fig.2 illustrates the failure distributions of all tests in a

180 0-7803-6678-6/01/$10.00 0 2001 IEEE

stress conditions.

2,s

2

1.6

1

0.6

N O

4.6

1

-1,s

2

n - Determination

SWEAT Isocurrent WL PL I

A I

17

12 A

0 Y - e 7

2

. I I

I , I

20

'Z I 9 - 8 1 8 -

o 17 s - e 16 v

+ A Ea = 0.8eV

15 ~~

4.6 : : : : A : : : : : I : : : ! : : : : : : t u + : : : : : : m : I : : :

I,OE+OI I.OE+O2 I,OE*O3 I,OE*M I,OE*OT I,OE*M

Fallum time (8)

Fig2 Distribution of failure times; A: SWEAT test, U: Isocurrent WL test, +: PL test

Determination of activation energy and current density exponent. The parameters of Black's equation [6] (activation energy E, and current density exponent n) have been determined using a three dimensional fit of all measured triples tso, T1her jhe. Here E, = 0.8eV and n = 2 is obtained. To illustrate the fit result graphically, the data is plotted as In tso+n*lnj versus IkT (Fig.3) and In tso (250°C) versus in j (Fig.4) respectively.

Fig 3 Determination of activation energy

Extrapolation to operating conditions

2

1 ,I

1

0,s

N O

4.6

1

-1,s

-2

-2.6 1,€+01 1,EW 1,E+06 1,E+07 1,ElOO 1,EW

Failure tlme (a)

Fig 5 : Projection to operation condition A: SWEAT test, H: Isocurrent WL test, +: PL test, open symbols: the projected distributions

Failure analysis Failure analysis confirms that the same failure mechanism is active for all tests (Fig. 6-8). The voiding is found close to and or directly above the upstream via in the upper metal layer. This is the expected failure location if the current flows upstream. Here the tungsten-via acts as a diffusion barrier for the moving aluminium ions.

illustrates the failure distributions as well as the projections for all tests. Although extrapolating over a wide time range (5 to 10 decades), the projected distributions cluster in a Fig 6.: Failure analysis of IPL test @ 25OoC, 9mA/pm2

t~ = 4un

181

tF = 720s

tF = 570s

Fig.7 Failure analysis of SWEAT test @ 197"C/213"C and 365mA/pm2/374mA/pm2 respectively

t~ = 3300s

Fig 8.: Failure analysis of isocurrent WL test @ 36OOC , 90 mA/pm2

ConclusiodSummary

A good correlation between conventional PL- and two types of fast WL-tests is found for product relevant structures. With the results fiom deep sub-micron via-line structures, we have verified the physical failure scenario, the underlying failure statistics and we have found reasonable parameters for Black's equation. We conclude that both fast wafer level test methods, as described above, cannot only be used for process control and split comparison but also for life time prediction. However one must state that the stress conditions have to be chosen carefblly and should be varied in a sufficient way to verify that the parameters of Black's equation are reasonable. A high accuracy in determination of the line temperature is necessary as well as the verification

of the physical failure scenario. We would like to mention that the methods are not limited for AlCu Metallization but can also be used for Cu metallization.

References:

[l] J.v Hagen, G. Antonin, J. Fazekas, L. Head and H. Schafft, New SWEAT Method for Fast, Accurate and Stable Electromigration Testing on Wafer Level., IRW 2000. [2] A.E. Zitzelsberger, A.Pietsch, J.v.Hagen, Electromigration Testing on Via Line Structures with a S WEA T Method in comparison to standard package level tests, IRW 2000. [3] M.Lepper, R. Bauer, A.E. Zitzelsberger, A Correlation between Highly Accelerated Wafer Level and Standard Package Level Electromigration Tests on Deep Sub-Micron Via-Line Structures, R W 2000. [4] JEDEC Publication 119, A Procedure for Executing SWEAT, Sept. 1994, Solid State Products Engineering Council, 250 Wilson Blvtl. Arlington, VA 2220 1-3824. [5] S.Menon, J.Fazekas, J .v.Hagen, L.Head, C.H.Ellenwood, H.Schat3, Impact of Test-Structure Design and Test Methoak for Electrontigration Testing, 1999 IEEE International Integrated Reliability Workshop Final Report, pp. 46-53, IEEE Catalog No. 99TH8460 [6] J.R.Black, IEEE Traris. Electron Devices; ED-16, 1969, p33.

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