A Microprocessor-Based Circuit Model with The Ability of Debugging-Assistance

Fang Jyh-Perng Department of Electrical Engineering National Taipei Institute of Technology

hBSTRACT

This paper describes a microprocessor-based circuit model which facilitates debugging and maintenance of the micro- processor-based circuit. A speed-adjustable mechanism was implemented which enables the microprocessor to execute instructions under either single-step mode or speed-adjustable mode. Through this mechanism. Datum of a malfunctional circuit can be fetched and compared to reference datum observed previously.

KEYWORDS Micioprocessor-based circuit, Single-Step, Debugging

I. INTRODUCTIOE

Microprocessor-based circuit is extensively applied to different fields nowadays because of its low cost and high flexibility. However, debugging these microprocessor-based circuits during either developing phase or maintenance stage absolutely demands high precision instruments and proficient personnel.

In order to save cost of enormous resources for debugging or troubleshooting microprocessor-based circuit, a circuit model for assisting debugging is developed. The straitened circum- stances when troubleshooting a malfunctional microprocessor- based circuit will be notably ameliorated.

11. CIRCUIT HODEL

8088CPU-based circuit is chosen as a platform of our circuit model because of not only its wide applications but also its consistency between different circuits.

The block diagram of a conventional 8088-based circuit is shown in Figure 1. There are two signals deserves some notice: ALE signal and READY signal.

ALE As the data bus and part of the address bus of 8088 is

time-multiplexed, the ALE signal presented by 8088 is specified for seperating address signals and data signals.

To seperate multiplex signals, ALE signal is typically used as a strobe of a transparent latch. When ALE signal gets high at the beginning of T1 of each bus cycle. latch enabled, address signals flow through latch, as TI terminates. ALE goes low,the falling edge latches address signals at output side of the latch.

READY The READY input is a signal used by either memory or IiO

device to notify 8088 when the requested dab operation is finished. When the data delivery is completed, the external device will tell 8088 that job is done by sending a high an the READY line. Typically, the READY input of 8088 is connected to the READY output of 8284, which is a clock generator. while the RDYl input of 8284 is connected to a wait-state generator. When a low-speed memory or U0 device in the 8088-based circuit can not catch up with the speed of 8088. this device may assert a "not ready" signal through the wait-state generator to the RDY 1 input of 8284, 8284 will then synchronizes READY signal with the CLK signal to request CPU to insert wait states into bus cycle while the count of wait states inserted is ajustable by setting jumper in the wait-state generator previously

The circuit model in this study modifies the conventional usage of wait-state generator so that the operation speed of the microprocessor-based circuit becomes controllable.

The circuit model is depicted as shown in figure 2. A countcr is used as a frequency divider, the oscillator frequency is lowered by the Frequency divider under the control of operation mode controller when the circuit is operated in speed-ajustable mode. On the other hand, if the circuit is set into single-step mode, the oscillator is disabled and the output of frequency divider is manually controlled by the operation mode controller. The input pulses of wait-state circuit will be synchronized by ALE came from 8088 and the synchronized pulse will substamtially control the speed of 8088 through 8284.

Although the bus status of the microprocessor is intricate, having the aid of speed-adjustable mechanism and multiplex display circuit, The status of address bus, signal bus, and data bus can be observed on the same time through the select input

come from n -:> 2" decoder which decodes the counter output into select input of the multiplex display circuit.

0-7803-2646-6 - 505 -

WAIT-STATE GENERATOR

CLK READY RESET

8086

Mil0 RD

WR

DTIR DEN

ALE

ADD/ DATA

3 BUFFER DATA BUS

Figure 1. Conventional circuit block of 8088

I I I . EVALUATION

To test the performance of our circuit model, a test program is designed to repeatedly light a LED located at U0 address 10H. As shown in figure 3, this test program is listed in . U T format which includes address, machine code, and souce code. As the test program is stored in ROM, the location 07FOH in figure 3 is mapped to system address FFFFOH, whenever the 8088 is reset, it begins executing instruction at memory location FFFFOH, and subsequently FFFF2H, FFFF4H, and then jump back to FFFFOH. and so forth.

The observed digital values on buses of the circuit at each single step is sequentially tabulated in figure 4. In addition to the address bus and data bus, some important signals in the circuit is also included. The meaning of each signal in figure 4 is explained as follows:

sgl : RAM RIW, 1-- read RAM, 0.- write RAM sg2: RAM SEL, 0-- enable RAM sg3: ROM RD , 0-- read ROM. sg4: ROM SEL, 0.- enable ROM.

I I OPERATION MODE

CONTROLLER

sg5: I/O SEL. 0.- select IiO. sg6: I/O WR . 0- write IiO. sg7: I/O RD , 0-- read I/O. sg8: 55 ACS , 0-- select 8255 PPI. (55 CS is a decoded output of signal5 and some address signals)

Checking the machine codes in figure 3 against the data column of figure 4, each byte of the machine code in figure 3 is observed on data bus in an orderly way. Although some superfluous data in the data column of figure 4 not listed in figure 3 are also observed, these surplus values are concluded as being caused by clearing internal instruction queue of CPU.

Checking the address in figure 3 against the address column of figure 4, values at address bus are consistent. Besides, comparing instruction column against signal column of figure 4, the status of the control signals and the instructions are also unanimous. Therefore, the function of this circuit is confirmed to be correct, and this circuit becomes a circuit of reference. The datum displayed at each step is compared to datum displayed on a doubted circuit executing the same test program.

FROM ALE18088 I

TO ~ ~ ~ 1 8 2 8 4

I SWITCHING CKT

\ I

ax7 SEGMENT

Figure 2 Single-step and speed-adjusytabk mechanism.

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TITLE Light a LED on an 1/0 Port

0000 FANG SEGMENT

07F0 ORG 7FOH 07FO BO 01 BEGIN: MOV AL,00000001B 0'7F2 E6 10 CYCLE: OUT 10H,AL 07F4 ER FC JMP CYCLE 07F6 FANG ENDS

ASSUME CS : FANG, DS : FANG, SS: FANG

END BEGIN

Figure 3. Test program

Interrupt, DMA, Coprocessor

Generally speaking, the case considered above is classified as polling U0 only. However, the same single-step mechanism can be applied to hardware interrupt, too. For example, suppose the same program in figure 3 is treated as a main program and is waiting for a hardware interrupt, whenever a hardware interrupt is asserted, the content of the registers in 8088 are stored, a lot of redundant datum displayed on the 7-segment displays in response to the dominance transfer from main program to interrupt service routine. Finally the interrupt service routine dominates the system, single-step mechanism resumes. Once the interrupt service routine is finished, dominance will be returned from interrupt service routine to main program. Again, a lot of redundant datum displayed echo the internal operations of CPU.

As to DMA, almost all of the 8088-based circuit with the ability of direct memory access(DMA) adopts 8237-- a DMA clontroller. Just llke the coprocessor such as 8087-- a numerical data processor, 8237 is treated as another processor in function in addition to 8088 on the circuit. In other words, the circuit with 8087 or 8237 may be treated as a multi-processor

environment. Fortunately, either 8237 or 8087 provides a READY input, which resembles the function of the READY input of 8088 Therefore, a single-step mechanism for such a mulli-processor circuit is also available, if necessary.

Through the speed-adjustable mechanism, the rhythm of a microprocessor-based circuit will be controllable, the signals on the bus can be easily observed or recorded without the assistance of high precision instruments.

A.lthough th.ere are many kinds of microprocessors which do not posses a READY pin. The same concept of the circuit model presented here still can be applied only if that microprocessclr has a control input pin for waiting for a low- speed U0 device.

V I REFERENCES

(11 C.M. Cilmore, "Microprocessors: Principles and Applications," blcCraw- H i l l Book Co., New York, 1989.

Figure 4. Observed information.

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[2J A. Singh, W.A. Triebel, "16-BIT and 32-BIT Microprocessors: Architecture, Software, and Interfacing Techniques. " Prentice-Hall Book Co., New Jersy. 1991.

131 B.B. Brey. "The Intel Microprocessors: 8086/8088, 80186, 80286. 80386, and 80486: architecture, programming, and interfacing." Macmillan Pub. Co. , New York, 1991.

[ill J I). Lenk. "Practical Electronic Troubleshooting, I'

PrenLice-Hall Book CO , New Jersy, 1990.

[SI J .A .S . Wilson, "Electronic troubleshooting procedures and servicing techniques," Prentice-Hall Book Co., New Jersy, 1990 New York. 1992

(61 W.B. Gilts, "Asseinhly language programming for the Intel 8OXXX family. I ' Macinillan Pub. Co., New York, 1991.

(71 D.V. MALL. "Microprocessors and interfacing : Prograiiiining aixl hardware 2iE. " McGraw-Hill Book Co., 1991,

[SI Robert Gioasblatt. "The 8088 Project Book," Tab Books. PA. 1989

[ NAMF FANG JYI-I-PERNG EMAIL ADDRESS jptang@sun cc tit edu tw ]

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