ICSE2.002 Proc.2002, Penang, Malaysia

Novel High-speed CMOS Modulator Integrated Circuit Design for Mixed-Signal VLSI Micro-Chips

Leng Mun Thong and Norlaili binti Mohd. Noh, School of Electric & Electronics Engineering

Universiti Sains Malaysia, Engineering Campus,

14300 Nibong Tebal, Penang, Malaysia. Email : mt lenp@,hotmail.com

eelaili@,ew.usm.mv

Absfrucl Sigma-delta modulator is famous for its inherent linearity, reduced anti-aliasing filter complexity and high tolerance to circuit imperfection. Band-pass sigma-delta converter is better for narrow-band signals in high-speed, high signal-to- noise ratio and high resolution system compared with ordinary architecture. Both type of converters have been applied in various architectures including quadrature architecture, two- path architecture and parallelism technique depending on the applications. This paper proposes a handpass sigma- delta modulator for mixed-signal to achieve higher SNR and resolution at lower power consumption using VLSI technology.

I. INTRODUCTION

THE sigma delta conversion technique has been in existence for many years, but recent technological advances now make the devices practical and their use is becoming widespread. The converters have found homes in such applications as communications systems, consumer and professional audio, industrial weight scales, and precision measurement devices. The key feature of these converters is that they are the only low cost conversion method which provides both high dynamic range and flexibility in converting low bandwidth input signals. So, sigma-delta modulation has become the method of choice for high resolution A/D conversion

for the past few decades [l]. The benefits of it include inherent linearity, reduced anti-aliasing filter complexity, high tolerance to circuit imperfections (without accurately matched analog components) and it ables the system architecture for switched-capacitor implementation [Z].

Further research on sigma-delta modulator are always stressed on high- speed, high resolution, high signal-to- noise ratio (SNR) and low power consumptions. These are to increase the performance of modulator in communications, computing, and especially in customer applications purposes including analog-to-digital or digital-to-analog conversion [3]. In this paper, a new design of sigma-delta . modulator containing all the demands is proposed.

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Figure 1 : Comparison of usage between bandnass modulator and low-uass modulator ~41.

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11. BANDPASS SIGMA-DELTA MODULATOR

The demand for better signal-to-noise ratio and resolution in the design of U modulator has encouraged more researches on bandpass ZA modulator. Comparing with the ordiniuy XA modulator (low-pass U modulator), bandpass w. modulator has a better S N R performance. Researches show that every doubling of the oversampling ratio in bandpass ZA modulator will cause the signal-to-noise ratio to increase by 3N+3dB, slightly better than half the 6N+3dB/octave rate for a low-pass modulator of order N [4].

Notice that the total order of both architectures (low-pass and bandpass) is the same in Figure 1. With the same signal bandwidth, the bandpass approach needs one modulator of order 2N to obtain the same performance as that of the zero-IF version with two parallel low-pass modulators of order N [2]. Result shows that when the center frequency is j , / 4

(where f. is the signal frequency), a bandpass converter with order 2N has the same performance as a parallel low-pass converter of order N.

Traditional converters (low-pass) place noise transfer-function zeros near

= 0 in order to null quantization noise in a nmow band around DC. This noise- shaping concept was extended in the badpass case, where the noise transfer- function zeros are placed at a non-zero frequency, 0, [21.

For narrow-band signals away from DC, the bad-reject noise shaping of a bandpass converter results in a high signal-to-noise ratio at lower sampling rates compared to that of a low-pass converter [2]. The oversampling ratio is defined as one-half the sampling rate divided by the width of the band of interest.

Band-pass ZAA/D converters are well suited at the front-end of radio applications that allows direct conversion to digital at either intermediate or radio-frequency (several MHz). Furthermore, the quantizer of modulator is often replaced by an additive noise source to yield a linear model in the analysis [5]. The input signal and the noise of the quantizer have different z-domain transfer functions to the

output. So, this can help us to justify the noise shaping transfer functions of the modulator to produce a better performance of a modulator or converter. The transfer functions can be derived as :

(2) OUf(2) H ( 2 ) -=__ I+H(Z)

where

NS(z) = noise-shaping transfer function Uut(z) = z transform of output signal In@) = z transform of input signal e(') = z transform of error signal added

by quantizer (quantization error) - Figure 2 : A bandpass modulator structure [7].

Based on Figure 2, a feedback loop is necessary to reduce the existing error of the circuit. There are many types of feedback loop that are relevant to the design [6].

111. VARIOUS MODULATOR ARCHITECTURES

The architecture of the bandpass w. modulator in Figure 2 shows that 'the resonator will modulate the input signal at various frequencies to differ the noises. These signals will go through a filter which will then extract the original signal in digital form. This architecture has been implemented into various types of topologies for different applications.

A. A QUADRATURE ZA MODULATOR

This quadrature technique in modulator (monolithic digital-radio- receiver design) allows straightforward complex AD conversion of an image- reject mixer's I and Q output [7]. Quadrature bandpass TA modulators provide a superior performance over a complex input signal. A modulation process to the input signal with cos and sin function will separate the real and

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imaginary part of the signal into different pave.

1

Figure 3 : A quadrature ZA modulator structure [7].

Architecture in Figure 3 shows that the quadrature XA modulator involves a complex resonator (bandpass modulator) with a z-plane flowing graph similar to the one showing in Figure 4. A complex filter with a single pole at real-axis coordinate (l+d) and imaginary-axis coordinate (c) has the transfer function [7]:

(3) vow - 1 -_ V, z - I - d - j c

XfZ)

Figure 4 : Complex signal flow graph [7].

B. A TWO-PATH EA MODULATOR

A two-path architecture will improve the circuit by making it more tolerant to analog circuit Iimitations at high sampling rate compared to switched-capacitor bi- quadratic filters [8]. For N-path architecture, the sampling rate of each path filter i s reduced by a factor of N relative to the effective throughput rate of the overall N-path shucture in Figure 5. The z- transform transfer function of the structure is [8]

where H ( z , ) is the transfer function of each identical path filter. z D corresponds to the z variable of single path.

modulator in Figure 6 has an output in z-domain :

A two-path

1 2

Y ( z ) = - (H , ( zZ ) + H,(z’)) .X(z)

t-

Figure 5 : A N-path filter Struchm [8].

Figure 6 : A hyo-path bandpass ZA modulator PI.

The performance of the resonators in direct single-path bandpass modulators degrade when the sampling speed increased because of incomplete operational amplifier settling, causing a commensurate decline in the performance of the modulator. Two-path architectures are proposed to relax the settling requirements or the operational amplifier.

C. PARALLEL EA MODULATOR

Parallel ZA modulator is a new design of analog-to-digital converter. As in Figure 7, the analog input is simultaneously applied to M amplitude modulators, each followed by a conventional delta-sigma modulator. These delta-sigma modulators are filtered, demodulated and summed together synchronously to produce a single digital output [9]. This means that the signal and the quantization noise are passing though the same filter, that is the low-pass decimation filter.

The 11 XA converter amplitude modulates the input to decouple the signal from the quantization noise such that the filtering of the signal is undone by amplitude demodulation. So, the signal is delayed when the noise is low-pass filtered. The quantization noise from each channel of the II EA A/D converter adds in power at the input. Thus, it makes A/D

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conversion without oversampling possible for bandpass modulator.

i ,

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Figure I : The I IXA modulator with analog input x(n) and digital output y(n) [9].

~ The increase in resolution for this I1 XA modulator is L bits for each doubling of the number of channel [XI. It differs with a single-channel oversampled Lth-order m converter in that the latter increases L+1/2 bits in resolution for each doubling in the oversampling ratio.

h'. NOVEL BANDPASS SIGMA-DELTA MODULATOR

In the progress of designing a better performance XA modulator, handpass architecture has been implemented to achieve higher signal-to-noise ratio and higher resolution than that of the conventional (low-pass) ZA modulator. To achieve even higher SNR, cascading technique can be implemented. Since bandpass ZA modulator exists in even order, several orders of bandpass m modulator will be considered ( 2"d order, 4Ih order and 6" order).

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Figure 8 : Complementary logic gate as a combination of a PUN and a PDN [ 101.

Based on previous researches [2], bandpass XA A/D converter can hardly to convert signal from analog to digital at microwave frequency ( 1 GHz). This design is there fore restricted to operate with an input signal at frequency less than 1 GHz .

To reduce the power consumption of the modulator, several implementations of CMOS design can be taken into consideration. Ordinary CMOS gate comes with a combination of two networks, the pull-up network (PUN) and the pull-down network (PDN) [lo] as showing in Figure 8. The PUN consists only PMOS transistors and provides a conditional connection to V,, . The PDN is connected to v, and are just NMOS transistors. Both circuits are mirror image to each other..

Figure 9 : Ratioed logic gates include resistive load, depletion load NMOS and pseudo- NMOS [lo].

To reduce the power consumption, the potential difference between V,, and Vss must be minimized to a value just enough to operate every CMOS transistor in the circuit. This can be done by replacing PUN and PDN with ratioed logic gates such as shown in Figure 9. Besides that, the order of the CMOS also gives some effect to power consumption. By arranging the transistor in parallel order, the power consumption can he reduced. By implementing both technique, the total voltage (and therefore power consumption) can significantly be reduced further. However, a study on the effects of this design to other performance criteria such as SNR, resolution, signal amplification and dynamic range need to be done extensively for an optimized performance.

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REFERENCES

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