17
IEEE EDS DL IEEE EDS DL – Tokyo Institute of Technology, Japan Tokyo Institute of Technology, Japan IEEE-EDS / DL EEE / NTU U ifi ti f MOS C tMdl ith th U ifi ti f MOS C tMdl ith th U ifi ti f MOS C tMdl ith th U ifi ti f MOS C tMdl ith th Unification of MOS Compact Models with the Unification of MOS Compact Models with the Unified Regional Modeling Approach Unified Regional Modeling Approach Unification of MOS Compact Models with the Unification of MOS Compact Models with the Unified Regional Modeling Approach Unified Regional Modeling Approach Xi Zh Xing Zhou School of Electrical and Electronic Engineering Nanyang Technological University, Singapore August 26, 2011 Email: [email protected] X. ZHOU 1 © 2011 Outline Outline IEEE-EDS / DL EEE / NTU Outline Outline Motivation for MOS Model Unification Unified Regional Modeling (URM) Approach Surface potential of generic MOSFET for bulk/SOI/DG/GAA Body doping and thickness scaling Model symmetry and asymmetric MOS modeling Model Extension to SB/DSS Modeling Model symmetry and asymmetric MOS modeling Shottky-barrier (SB) MOS with ambipolar transport Dopant-segregated Shottky (DSS) MOS with subcircuit approach Xsim Model Summary X. ZHOU 2 © 2011

IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

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Page 1: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

IEEE EDS DL IEEE EDS DL –– Tokyo Institute of Technology, JapanTokyo Institute of Technology, Japan

IEEE-EDS / DL EEE / NTU

U ifi ti f MOS C t M d l ith thU ifi ti f MOS C t M d l ith thU ifi ti f MOS C t M d l ith thU ifi ti f MOS C t M d l ith thUnification of MOS Compact Models with the Unification of MOS Compact Models with the Unified Regional Modeling ApproachUnified Regional Modeling Approach

Unification of MOS Compact Models with the Unification of MOS Compact Models with the Unified Regional Modeling ApproachUnified Regional Modeling Approach

Xi ZhXing Zhou

School of Electrical and Electronic EngineeringNanyang Technological University, Singapore

August 26, 2011

Email: [email protected]

X. ZHOU 1 © 2011

OutlineOutline

IEEE-EDS / DL EEE / NTU

OutlineOutline

Motivation for MOS Model Unification

Unified Regional Modeling (URM) Approachg g ( ) pp Surface potential of generic MOSFET for bulk/SOI/DG/GAA Body doping and thickness scaling Model symmetry and asymmetric MOS modeling

Model Extension to SB/DSS Modeling

Model symmetry and asymmetric MOS modeling

Shottky-barrier (SB) MOS with ambipolar transport Dopant-segregated Shottky (DSS) MOS with subcircuit approach

Xsim Model Summary

X. ZHOU 2 © 2011

Page 2: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

CMOS Technology Generations and Scaling LimitsCMOS Technology Generations and Scaling Limits

IEEE-EDS / DL EEE / NTU

CMOS Technology Generations and Scaling LimitsCMOS Technology Generations and Scaling Limits

Today

Technology?Technology?ec o ogyec o ogy

Physics?Physics?

Statistics?Statistics?

Economics?Economics?(Yield)(Yield)

X. ZHOU 3 © 2011

Models and Modeling GroupsModels and Modeling Groups

IEEE-EDS / DL EEE / NTU

Models and Modeling GroupsModels and Modeling Groups

NGSOI/MG ModelNGSOI/MG Model

BSIMBSIM EKVEKV HiSIMHiSIM ULTRAULTRA--SOISOIACMACMUFDG/UFSOIUFDG/UFSOI

XsimXsim Technology-dependent predictive model DG/SOI/GaN SiNW/CNT PCMOS

ISNEISNE

Low Eng/GaN

X. ZHOU 4 © 2011

XsimXsim Technology-dependent predictive model DG/SOI/GaN SiNW/CNT PCMOS Low Eng/GaN

Page 3: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

MOSFET Compact Models: History and FutureMOSFET Compact Models: History and Future

IEEE-EDS / DL EEE / NTU

1966 1978 1985 1995 2005

MOSFET Compact Models: History and FutureMOSFET Compact Models: History and Future

V basedQb linearization

1966 1978 1985 1995 2005

CA

Classical bulk-CMOS ~40 yrs

Sah–Pao (input)Voltage Equation

Pao–Sah (output)C t E ti

Qi-based

Vt-basedQi linearization

Iterative / explicitsso

n +

GC

ChargeSheetModel(Q =Q +Q )Current Equation s-based

Iterative / explicit

Po

is (Qsc=Qb+Qi)

Non-classical CMOS ntr

ivia

ln

triv

ial

Non-classical CMOS

SOISOIBulk Voltage/Current Equations, CSM

Partially-Depleted (PD)Fully-Depleted (FD), Ultra-Thin Body (UTB)

Non Charge Sheet

no

no

MGMG New Voltage/Current Equations

Non-Charge-Sheet

Symmetric/Asymmetric Double Gate (s-DG/a-DG)

Tri-gate, GAA, Schottky-barrier, DSS, TFET, …Body Contact/Floating Body

X. ZHOU 5 © 2011

Tri gate, GAA, Schottky barrier, DSS, TFET, …Body Contact/Floating Body

Need for an Extendable Core Model for Future GenerationNeed for an Extendable Core Model for Future Generation

IEEE-EDS / DL EEE / NTU

Need for an Extendable Core Model for Future GenerationNeed for an Extendable Core Model for Future Generation

Time

Vt-based models

’60 ’70 ’80 ’90 ’00 ’10

Q b d d l

Pao–Sah One model for each structure is

Qi-based models

s-based models

History has witnessed generations of MOS models

and efforts required from one generation to the next …

— Need for a core model extendable to future generations, MG/FinFET is just

duplicating efforts

IDGS

IDGS DGS DG1S

II

g ,and with less duplicating efforts

MG/FinFET is just a special case

ID

Ids (B)

ID IDID

B lk PD SOI FD UTB/SOI DG/GAA/SB/DSS

B Sub Sub

G2

X. ZHOU 6 © 2011

Bulk PD-SOI FD-UTB/SOI DG/GAA/SB/DSS

Page 4: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

New Challenges in SOI/MG/GAA MOSFET ModelingNew Challenges in SOI/MG/GAA MOSFET Modeling

IEEE-EDS / DL EEE / NTU

New Challenges in SOI/MG/GAA MOSFET ModelingNew Challenges in SOI/MG/GAA MOSFET Modeling

SymmetrySeparate S/D modeling

y

VSVD

VdVs Vd sat

VG1

Tox1

0Carrier type

Separate S/D modeling with G(B)-ref for complete symmetry, as well as for asymmetric device

L

y

n+n+ s1(y)

DGPN

VdVs Vd,sat0

Core model (s) applicable to both unipolar (PN) and

Xo(x, y)o(y)

Ei = qs(y)

PN

S/D Contact

‘ambipolar’ (SB)

s2(y)NA ND

Bulk

SB“Thick-body” effect due to 2D field in S/D

TSi + Tox2

V

VB

s2(y)NA ND

x

TSi

Body Contact

Body dopingBody thickness

TSi/NSi full scaling from Lightly-doped can be

X. ZHOU 7 © 2011

VG2x

thin/doped to thick/pure body “intrinsic” at high temp

Generic DoubleGeneric Double--Gate MOSFET with Any Body DopingGate MOSFET with Any Body Doping

IEEE-EDS / DL EEE / NTU

Generic DoubleGeneric Double Gate MOSFET with Any Body DopingGate MOSFET with Any Body Doping

VG1V VLLrx2 NA (cm3) 02 2dm Si FX qp VS VD

NNg1g1

LLgg

Tox1

00

y1

RR

r

p1p1

1017

1014

Bulk

FinFET/SiNW(unintentional doped)(ox1)

(< 60 m)

0dm Si F qp

s1s1

o1o1

nn++

00 R R nn++

XXo1o1(V(Vg1g1))1010

( p )(intrinsic @ 200 C)

Intrinsic doping(27 C)

0o1o1

00 o1o1 = = o2o2 = = VVrr = 0 = 0 (at (at VVgigi==VVFBiFBi, V, Vss==VVdd=0)=0)

Xdm (m)0.1 1 10010

(NA = ND = 0: undoped = “pure” Si)

03 60

TTSiSiNNsdsd 2200

o2o2XXo2o2(V(Vg2g2))

y2

Bulk: TSi >> Xdm, with BC: o = Vb = VB

SOI: T > X without BC: ‘floating’

0 0DA N nN p

TTSiSi

Tox2

s2s200

NNg2g2

y2

p2p2

(ox2)

SOI: TSi > Xdm, without BC: o floating

DG/GAA: TSi/R << Xdm: ‘volume inversion’

( : ‘virtual electrode’)2

X. ZHOU 8 © 2011

x1 VG2

(o: virtual electrode )

Page 5: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

DGDG FinFETsFinFETs / GAA/ GAA SiNWsSiNWs

IEEE-EDS / DL EEE / NTU

DG DG FinFETsFinFETs / GAA / GAA SiNWsSiNWs

G VG Vg = VFB~Vt In undoped ‘long’/thick body

DS

G G

VS VD

y0Tox

+ +

L

V Vd + V ( )

Vg

Nsd

g

0

Lg

s

FB In undoped long /thick-body DG/GAA, potential reference (Vr) is at one point: o at Vgr = VFB

and Vd = 0n+ n+

TSiNA ND

Xo [Eo = 0]

VsVdFn = F + Vc(y) Nsd

Xo

TSi

Xj = TSi

R

0 GAA:TSi = 2R

s

oo = VrFp = F + Vr

and Vds = 0

“Volume inversion” for VFB<Vgr<Vt: o follows Vg

x

Tox

Vg

TSi

G VG Vg

o follows Vg

“Strong inversion” for Vgr>Vt

In ‘short’/thick-body DG/GAAx

x

Vbi,s + Vs

Vbi,d + Vd

G

g In short /thick-body DG/GAA, source/drain (S/D) region 2D fields extend to the channel, causing VFB to be TSi dependent

S Ds(0)

s(L)

Go = Vr

causing VFB to be TSi dependent

‘Thin-body’ DG/GAA have ‘long’-channel behaviors

X. ZHOU 9 © 2011

yL0

o channel behaviors

The Generic SOI/DG/GAA MOSFETThe Generic SOI/DG/GAA MOSFET

IEEE-EDS / DL EEE / NTU

The Generic SOI/DG/GAA MOSFETThe Generic SOI/DG/GAA MOSFET

Vg1 Common/symmetric-DG [GAA]g

Vs Vd

Tox1 y0 LKox1s1

o(Xo)

Xj Vc

NA NDVr

y [ ] Vg1 = Vg2 = Vg: two gates with one bias Cox1 = Cox2: s-DG (Xo = TSi/2; [R]) Full-depletion: VFD = V (Xd=TSi/2)

V

Tox2x

TSiKox2

s2

oo

Vc

A Dr Full-depletion: VFD = Vg(Xd=TSi/2) Cox1 Cox2: ca-DG (Xo < TSi)

Independent/asymmetric-DGVg2

Zero-field potential: o [o'(Xo) = 0]

Independent/asymmetric DG Vg1 Vg2: ia-DG, biased independently Zero-field location may be outside body Consider two “independent” gates; linked

Imref-split: Vcr = Fn – Fp = Vc – Vr

Vr = Vb (BC: body-contacted)V = V = min(V V ) (“FB”: w/o BC)

Consider two independent gates; linked through full-depletion condition: Xd1 + Xd2 = TSi

Vr = Vmin = min(Vs, Vd) ( FB : w/o BC)

Bulk: special case of s-DG SOI: special case of ia-DG

GAA Unification of MOS

SOI ia-DG ca-DG s-DG bulk

X. ZHOU 10 © 2011

SOI ia-DG ca-DG s-DG bulk

Page 6: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

The PoissonThe Poisson––Boltzmann Equation and SolutionBoltzmann Equation and Solution

IEEE-EDS / DL EEE / NTU

2

2D A

DA

q p n N Ndn

qNNp

2 2d d GCA:

The PoissonThe Poisson Boltzmann Equation and SolutionBoltzmann Equation and Solution

Charge neutrality:

20 02

2

,1 FF thc cb hb tth

Si Si Si

cbSi Si

D

V v

A

VvV v

ndx

qp qpG V

NN

eee

p

2 2dy dx

GCA:

Fn thvin n e

Charge neutrality:

0 0

F th Fn th

A D

v vi

p n N N

n e e

Fp thv

ip n e

0, , 0,y y E y E y

B.C.’s: o dmX X

0F cb th

b

V viV

n n n e

10 exp sinh

2F th

b

v A Di iV

i

N Np p n e n

n

2 2

0s s sEsE qpd

E dE d G V d

2

2x x x

x

dE dE dEd dE

dx dx d dx d

x

dE

dx

Fp F bV

0, , 0,

, 0, , 0

s x s

o b x o

y y E y E y

X y V E X y

1 2

s

F V G V d

Fn F cV

020 0 0

,2

sx x cb

Si

qpE dE d G V d

dx

22 20 02 21 1 ,F th th tsscb hv v v

s th th s ssV

cs b

qp qpE e v e v e F V

0

, ,s s cb cbF V G V d thv kT q

02 Siq p

C

S Sii

2, sgn 1 12

sbF c sss s cb s ss

vth

EF v v e e e

qp

s s th

F F th

v

v

oxC

X. ZHOU 11 © 2011

02 Siqp cb cb thv V v

The Complete (“SahThe Complete (“Sah––Pao”) Voltage EquationPao”) Voltage Equation

IEEE-EDS / DL EEE / NTU

E E Q C TGauss law: E QE Q

The Complete ( SahThe Complete ( Sah Pao ) Voltage EquationPao ) Voltage Equation

Si s ox ox oxE E Q

gb MS ox sV V ox ox oxE V T

ox ox oxC T

02 Si oxq p C FB MS ox oxV Q C

Gauss law:

Potentialbalance:

Si s scE Q ox ox gE Q

ox gb MS s ox ox gb FB sox ox ox oxox ox oxs

Si Si Si Si

C V Q C V VV T QE QE

Poisson

sgn

2 2sgn exp exp 1 exp 1 exps

ss

gb FB s s

F Fs

cb cbth th s

V V f

v vv v v

V

v

V

p AN n DN

th th th thv v v v

g oxoxQQ C

oxsc CQ

ox os xdi C QQ CQ

strb acox ou xc s bC CQ Q QQ

= +

Ward–Dutton partition

Unified Regional Model (URM)Charge balance

b oxigQ Q Q Q smoothing

one-piece

Charge sheet model (CSM)

X. ZHOU 12 © 2011

Unified Regional Model (URM)Charge balance Charge-sheet model (CSM)

Page 7: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

The SurfaceThe Surface--Potential SolutionsPotential Solutions –– Piecewise RegionalPiecewise Regional

IEEE-EDS / DL EEE / NTU

The SurfaceThe Surface Potential Solutions Potential Solutions Piecewise RegionalPiecewise Regional

Accumulationths vh bv e V V

sgngb FB s sV V f

2

, Accumulation

,Depletion

,Strong inversionF th tb hsc

th gb FB

FB gb t

v vth gb t

V

s

v e V V

V V V

v e e V V

, gth gb t

Piecewise regional solutions

V V

2

2

2 ,Only holes,

,Only acceptors,2 4

gb FB th cc gb FB

s gb FB FB gb tdd A

cc V V v W V V

V V V V

p

V N

L exp22

gb FBcc

thth

V VW

vv

2 4

2 ,Only electrons,gb FB th ss gb tss V V v V nW V

L

2exp

22gb FB F

sst

c

hth

bV VW

vv

V

WL is the Lambert W function, which is the solution of the equation: exp 0X aX B

where and 21exp , thvB

W a

22, ,

2gb FB F cbss F cb

ss ss

V V VVX B

v v

, ,

2gb FBcc

cc cc

V VX B

v v

X. ZHOU 13 © 2011

a a 2 th th

v v2 th thv v

The SurfaceThe Surface--Potential SolutionsPotential Solutions –– Unified RegionalUnified Regional

IEEE-EDS / DL EEE / NTU

The SurfaceThe Surface Potential Solutions Potential Solutions Unified RegionalUnified Regional

Smoothing and transition functions ;f x g

2; 0.5 4f x x x

2; 0.5 4r x x x

satx

, ;eff satx x

x

;x

Unified regional solutions

;r

2, ; 0.5 4eff sat sat sat sat satx x x x x x x x

x

;r x

Unified regional solutions

2

2

2gb FB gbr

gbr th ccV V Vacc cc V v W

L ;r gbgbr FB aV VV

gbar FBgb gbVVV V

2

2 4

2

gb FB gbf

gb FB gbf

sub dds gbfV V V

gbs f th ssV V Vtr ss

V

V v W

L

;gbf f gb FB fV V V

• Turn f to satisfy charge neutrality s(VFB) = 0;• Tune for smoothness at V = V

;f gbgba FB aV VV

Single-piece unified solutions

;d ff b a ceff dss c b

• Tune a for smoothness at Vgb = VFB.

X. ZHOU 14 © 2011

, ;suds seff rb t a ceff dss c accsa sub

Page 8: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

The Surface Potential: Unified Regional Modeling (URM)The Surface Potential: Unified Regional Modeling (URM)

IEEE-EDS / DL EEE / NTU

The Surface Potential: Unified Regional Modeling (URM)The Surface Potential: Unified Regional Modeling (URM)

g FBdv depV V , ;dds seff rv t a ceff dss c Single

piece

Symbols: MediciLines: Model (Xsim)

V) 1.0

1.2

g p a ceff dss c

V (y) dependentSmoothing

2gbfs ttr h ssV v W L(volume inversion)

piece

tial, s (

V

0 6

0.8

s

acc

dep , ;bd ff fd d ,d g FD Sis X Vd Tf

Vcb(y) dependentSmoothing

TSi and NA

ce P

oten

t

0.4

0.6 dv

str

, ;subd eff fdp de

22

V

Adding(‘ tit hi ’

s at Vgb = VFB is not solved exactly but two pieces are

(e.g., FD-SOI) dependent

Sur

fac

0.0

0.2 2 4 gbfsub V

(‘stitching’,not ‘glueing’)

exactly, but two pieces are “stitched” (rather than “glued”) to form a single-piece (seff) seamlessly “Glued”/iterative

Gate Voltage V (V)

-2 -1 0 1 2-0.2

VFB VFD Vt

2V v W L

seamlessly. Glued /iterative solution requires retaining all the terms in the voltage equation.

X. ZHOU 15 © 2011

Gate Voltage, Vg (V) 2gbra tcc h ccV v W L equa o

SurfaceSurface--Potential Derivatives and Regional ComponentsPotential Derivatives and Regional Components

IEEE-EDS / DL EEE / NTU

SurfaceSurface Potential Derivatives and Regional ComponentsPotential Derivatives and Regional Components

S b l M di i1.2

R i l l ti lSymbols: MediciLines: Model (Xsim)

0 8

1.0sseffd

Regional solutions scale with body doping (NA), body thickness (TSi), o ide thickness (T ) and

dVg

(V/V

)

0 4

0.6

0.8 depdv

acc

str

ds

oxide thickness (Tox), and all terminal biases

Smooth higher-order d i ti

d s/d

0.2

0.4 derivatives

Regional charge model –key to physically-based

i

-2 -1 0 1 2-0.2

0.0 parameter extraction

Foundation to unification of MOS compact models

Common Gate Voltage, Vg (V)(bulk/SOI/DG/NW/SB/DSS)

X. Zhou, et al., (invited review article), J. Comput. Electron., Mar. 2011.

X. ZHOU 16 © 2011

http://www.springerlink.com/content/x8t0742r3m051650/

Page 9: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

DopingDoping--DependentDependent ss: “Depletion” vs. Volume Inversion: “Depletion” vs. Volume Inversion

IEEE-EDS / DL EEE / NTU

DopingDoping Dependent Dependent ss: Depletion vs. Volume Inversion: Depletion vs. Volume Inversion

“Depletion” (N = 1014)Symbols: MediciLines: Model (Xsim)

V)

1.0

NA (cm3)

s-DG (Vg1 = Vg2 = Vg)Depletion (NA = 1014)

Slope 1

21 1

2 4sd

dV V

ntia

l, s (

V

0.5

1 2

0

1014

1016

1018

Volume inversion(undoped NA = 0, or

2 4g grfdV V

ace

Pot

en

0.0

Vgs

(V

/V)

0.6

0.8

1.0

1.210beyond full-depletion)Slope = 1

“Low-doping depletion”

Sur

fa

-0.5

2 1 0 1 2

ds/

dV

0.0

0.2

0.4

0.6

Tox = 3 nm

T = 50 nm

Low-doping depletion and “zero-doping volume inversion” have similar behaviors but different

Common Gate Voltage,Vgs (V)-2 -1 0 1 2

-1.0Vgs (V)

-2 -1 0 1 2TSi = 50 nmphysics

Full-doping scaling (zero to high) is only possible to b d l d b th URM

X. ZHOU 17 © 2011

be modeled by the URM

Paradigm Shift: B/GParadigm Shift: B/G--reference and Source/Drain by Labelreference and Source/Drain by Label

IEEE-EDS / DL EEE / NTU

Paradigm Shift: B/GParadigm Shift: B/G reference and Source/Drain by Labelreference and Source/Drain by Label

S/D by convention (nMOS) S/D by convention (nMOS)

• Vd > Vs: Ids > 0 (‘D’ ‘S’)• Vd < Vs: Ids > 0 (‘D’ ‘S’)

• By convention, nMOS Ids always flows from ‘D’ to ‘S’• Terminal swapping for –Vds: involving |Vds| in model

,, ,d effds ef sf effVVV

S/D by label (layout)

Always Source Always Drain,, ,d effds ef b bf s effVVV

Effective drain–source voltage (Vds,eff)

FB: BC:

,ds i b th ds eff sdI q A v V

A A

I I

VV

Id

DGS

Is

,,i b th i s effb bd e b tf hfq A v q A v VV (B)

Ids

Key: Bulk/Ground-reference — auto switch to B/G f h b d t t i bi d fl tiSub

• Vd > Vs: Ids > 0 (D S)• Vd < Vs: Ids < 0 (S D)

B/G-ref when body-contact is biased or floating Intrinsic Ids is an exact odd function of Vds

Physical modeling of asymmetric MOS (nontrivial with “terminal swapping” for negative V )

X. ZHOU 18 © 2011

d s ds ( ) with terminal swapping for negative Vds)

Page 10: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

Modeling Asymmetric Source/Drain MOSFETModeling Asymmetric Source/Drain MOSFET

IEEE-EDS / DL EEE / NTU

Modeling Asymmetric Source/Drain MOSFETModeling Asymmetric Source/Drain MOSFET

Symbols: Medici0.8 “Source” and “Drain” by

Symbols: MediciLines: Model

mA

/m

)

0.4

0.6VDS

VSD L = 90 nmt 2

104

ylabel (rather than by MOS convention); i.e., VDS and VSD are different

ent,

|I DS

| (m

0.2

0.4 tox = 2 nmt

(S/

m)

103

10

G Structural asymmetry (e.g., Xj, ND) can be captured by refitting

rain

Cur

re

-0.2

0.0

0 0 0 5 1 0 1 5 2 0

r ou

102

S D

B

p y gphysical parameters (e.g., vsat,s and vsat,d)

M d l b d S/D

0.0 0.5 1.0 1.5 2.0

Dr

-0.4 VDS or VSD (V)0.0 0.5 1.0 1.5 2.0 Models based on S/D

terminal swapping for negative Vds at circuit level can never model

DrainSource/SourceDrain Voltage, VDS or VSD (V)

Xj,s = 80 nm, ND,s = 1019 cm3; Xj,d = 30 nm, ND,d = 1018 cm3

level can never model asymmetric device easily (need to have two sets of symmetric model

t )

X. ZHOU 19 © 2011

G. H. See, et al., T-ED, 55(2), p. 624, Feb. 2008. parameters)

Gummel Symmetry Test on Undoped sGummel Symmetry Test on Undoped s--DG Without BCDG Without BC

IEEE-EDS / DL EEE / NTU

Gummel Symmetry Test on Undoped sGummel Symmetry Test on Undoped s DG Without BCDG Without BC

“Floating body” (without body contact): Key – “ground-referenced” model

Symbol: MediciLine: Model

0.10L = 10 m, Tox = 3 nm, TSi = 20 nm

Floating body (without body contact): Key ground referenced model

1.5 10Ids I'ds

Line: Model

/V-

m)

0.05

Vg

Vg Vx Vg + Vx0.0 5

dVx2

(mS

/

0.00

dVx6

0

10

20Vg

-1.5 0

501.5

I''ds I'''ds

d2 I ds/

d

-0.05

-60 -40 -20 0 20 40 60

d6 I ds/

d

-20

-10

0

0

0.0

V (V)

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15-0.10

Vx (mV)Vx step size: 10 mV

Vx (V)-0.2 0.0 0.2

-50

Vx (V)-0.2 0.0 0.2

V V V

X. ZHOU 20 © 2011

Vx (V)Identical curves with any Vg , , ,ds eff d eff s effV V V G. J. Zhu, et al., T-ED, 55(9), p. 2526, 2008.

Page 11: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

HarmonicHarmonic--Balance SimulationBalance Simulation

IEEE-EDS / DL EEE / NTU

HarmonicHarmonic Balance SimulationBalance Simulation

ln 2 ln s th d thV nv V nvnv e e SIC S t i I f C ti

-110SIC (n=1)Without SIC

ln 2 ln s th d tho thnv e e SIC: Symmetric Imref Correction

-130

-120

Without SIC

1st

I ds

(dB

)

-140

130

2nd

V

-150 3rd Vrf

Vg

~

V f (dB)

-30 -28 -26 -24 -22 -20

-160

X. ZHOU 21 © 2011

Vrf (dB)

UndopedUndoped--Body DG FinFET vs. GAA SiNWBody DG FinFET vs. GAA SiNW

IEEE-EDS / DL EEE / NTU

UndopedUndoped Body DG FinFET vs. GAA SiNW Body DG FinFET vs. GAA SiNW

FinFET (DG) SiNW (GAA)DGS

2

2c thV vi

Si

qnde

dx

1

c thV vi

Si

qnd dr e

r dr dr

V) 2.0G

s c th o c thV v V vgf s i thV v e e

First integration

n C

ha

rge,

Vgt

(V

1.0

1.5

0Symbols: SiNWLines: FinFET

G

22 gf c thV V viV y V v e

L

Ignore the o term

aliz

ed In

vers

ion

0.0

0.5 0.050.61.2

Vds (V)

22

s c gf th

th

V y V v ev

L

Second integration ox o ox oxC K T ln 1 ox o ox oxC K R T R

GateSource Voltage, Vgs (V)

-0.5 0.0 0.5 1.0 1.5 2.0

Nor

m

( ) ( )

, sin4

s c c o c c

th th

V V V V

v vi ox Sigt c c i th th

Si th

C TV V v e v e

v

2 2, 2

s o c thV vigt c c

ox

RqnV V e

C

X. ZHOU 22 © 2011

Si th

Page 12: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

ss--DG/FinFET: ShortDG/FinFET: Short--Channel Transfer CharacteristicsChannel Transfer Characteristics

IEEE-EDS / DL EEE / NTU

ss DG/FinFET: ShortDG/FinFET: Short Channel Transfer CharacteristicsChannel Transfer Characteristics

Transfer Ids–Vgs Transfer gm–Vgs

Symbols: Measurement10-3 0.25

L = 0 5 m T = 140 nm T = 4 nm Symbols: Measurement0.15

L = 0 5 m TS = 140 nm T = 4 nmSymbols: MeasurementLines: Model (Xsim)s-DG FinFET

s (A

/m

)

10-5

10-4

(mA

/ m

)

0 15

0.20

L = 0.5 m, TSi = 140 nm, Tox = 4 nm Symbols: MeasurementLines: Model (Xsim)s-DG FinFET

, gm

(S

/m

)

10-5

10-4

g m (

mS

/m

)

0.10

L = 0.5 m, TSi = 140 nm, Tox = 4 nm

in C

urre

nt, I

d

10-7

10-6

n C

urre

nt,

I ds

0.10

0.15

0.05

Vds (V)

cond

ucta

nce

10-7

10-6

cond

ucta

nce,

0.050.050 6

Vds (V)

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Dra

10-9

10-8 Dra

in0.00

0.050.61.2

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0T

rans

c

10-9

10-8

Tra

nsc

0.00

0.61.2

GateSource Voltage, Vgs (V) GateSource Voltage, Vgs (V)

Symmetric-DG FinFET model comparison with Measurement

X. ZHOU 23 © 2011

Symmetric-DG FinFET model comparison with Measurement.

ss--DG/FinFET: ShortDG/FinFET: Short--Channel Output CharacteristicsChannel Output Characteristics

IEEE-EDS / DL EEE / NTU

ss DG/FinFET: ShortDG/FinFET: Short Channel Output CharacteristicsChannel Output Characteristics

Output Ids–Vds Output gds–Vds

Symbols: Measurement L = 0.5 m, TSi = 140 nm, Tox = 4 nm Symbols: Measurement)

10-3

L = 0.5 m, TSi = 140 nm, Tox = 4 nmLines: Model (Xsim)s-DG FinFET

s (m

A/

m)

0.10

0.15

Vgs (V)

0.00.3

Lines: Model (Xsim)s-DG FinFET

e, g

ds (

S/

m)

n C

urre

nt,

I d

0.00

0.050.6

1.20.9

Con

duct

ance 10-4

Vgs (V)

0.00 3

-0 5 0 0 0 5 1 0 1 5 2 0

Dra

in

-0.10

-0.05

-0 5 0 0 0 5 1 0 1 5 2 0

Dra

in C

10-5

0.30.6

1.2

0.9

DrainSource Voltage, Vds (V)

-0.5 0.0 0.5 1.0 1.5 2.0

DrainSource Voltage, Vds (V)

-0.5 0.0 0.5 1.0 1.5 2.0

Symmetric-DG FinFET model comparison with Measurement

X. ZHOU 24 © 2011

Symmetric-DG FinFET model comparison with Measurement.

Page 13: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

GAA: Model Comparison with MeasurementGAA: Model Comparison with Measurement

IEEE-EDS / DL EEE / NTU

GAA: Model Comparison with Measurement GAA: Model Comparison with Measurement

Symbols: MeasurementLines: Model (Xsim)

10-6

10-5

8

10

1.0

1.2

Vds (V)

GAA SiNW Symbols: MeasurementLines: Model (Xsim)

10

GAA SiNW

(A

)

10-8

10-7

10-6

A)6

8

0.6

0.80.051.2

Vds (V)

A)

5

log(

I ds)

10-10

10-9

I ds,

sat (

2

4,li

n (

A)

0 2

0.4 I ds

(

5

0

Vgs (V)

00 3

10-13

10-12

10-11

0

2

I ds,

0 2

0.0

0.2

L = 180 nm, R = 2 nm, Tox = 4 nm -10

-5

L = 180 nm, R = 2 nm, Tox = 4 nm

0.3

0.6

1.20.9

Vgs (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.210-13 -0.2

Vds (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2-10

X. ZHOU 25 © 2011

GAA: Model Comparison with Measurement (1GAA: Model Comparison with Measurement (1stst Derivative)Derivative)

IEEE-EDS / DL EEE / NTU

GAA: Model Comparison with Measurement (1GAA: Model Comparison with Measurement (1 Derivative) Derivative)

Symbols: MeasurementLines: Model (Xsim)

6

10-5

10

121.5

Vds (V)

GAA SiNW Symbols: MeasurementLines: Model (Xsim)

80

100

(S)

10-5

10-4

GAA SiNW

) (S

)

10 8

10-7

10-6

(S

)

6

81.00.051.2

ds ( )

S) 60

-0.4 0.0 0.4 0.8 1.2

log(

g ds)

10-7

10-6

log(

g m)

10-10

10-9

10-8

g m,s

at (

4

6

in ( S

)

0.5

g ds

(

20

40Vds (V)

Vgs (V)

00 3

10-12

10-11

10-10

0

2

g m,l

0.0L = 180 nm, R = 2 nm, Tox = 4 nm 0

20

L = 180 nm, R = 2 nm, Tox = 4 nm

0.30.6

1.20.9

Vgs (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.210 12

Vds (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

X. ZHOU 26 © 2011

Page 14: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

GAA: Model Comparison with Measurement (2GAA: Model Comparison with Measurement (2ndnd Derivative)Derivative)

IEEE-EDS / DL EEE / NTU

GAA: Model Comparison with Measurement (2GAA: Model Comparison with Measurement (2 Derivative) Derivative)

Symbols: MeasurementLines: Model (Xsim)

30

0.051 2

Vds (V)

GAA SiNW

Symbols: MeasurementLines: Model (Xsim)

10

20 Vgs (V)

00.30 6

GAA SiNW

S/V

)

201.2

S/V

) 0

0.6

1.20.9

gm

' (

10

g ds'

(

-20

-10

0

L = 180 nm, R = 2 nm, Tox = 4 nm -30 L = 180 nm, R = 2 nm, Tox = 4 nm

Vgs (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vds (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

X. ZHOU 27 © 2011

GAA: MeasuredGAA: Measured GummelGummel Symmetry TestSymmetry Test

IEEE-EDS / DL EEE / NTU

GAA: Measured GAA: Measured GummelGummel Symmetry Test Symmetry Test

Symbols: Measurement8L = 180 nm R = 5 nm T = 4 nmV (V)

Vx

(A

/V)

15

20

25y

Lines: Model (Xsim)

(A

)

0

2

4

60.40.60.81.01.2

L = 180 nm, R = 5 nm, Tox = 4 nmVg (V)

dIds

/dV

5

10

(b)

I ds

8

-6

-4

-2

0Vg

Vg/2 Vx Vg/2 + Vx(Vx = 0.02 V)(a)

/V2 )

40

60

-8( )

/V3 )

0.2

0.4

2 I ds/

dVx2 (

A/

40

-20

0

20

3 I ds/

dVx3 (

A/

-0 4

-0.2

0.0

V (V)

-0.4 -0.2 0.0 0.2 0.4

d2

-60

-40

(c)

V (V)

-0.4 -0.2 0.0 0.2 0.4

d3

-0.6

0.4

(d)

X. ZHOU 28 © 2011

Vx (V) Vx (V)

Page 15: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

SchottkySchottky--Barrier MOSFET: Ambipolar CurrentBarrier MOSFET: Ambipolar Current

IEEE-EDS / DL EEE / NTU

SchottkySchottky Barrier MOSFET: Ambipolar CurrentBarrier MOSFET: Ambipolar Current

Symbols: Medici10-2

L = 65 nm T = 20 nm T = 3 nm Symbols: MediciV) 2

L = 1 m, R = 10 nm, Tox = 3 nmSymbols: MediciLines: Model (Xsim)

s (A

/m

)

10-7

10-6

10-5

10-4

10-3 L = 65 nm, TSi = 20 nm, Tox = 3 nm Symbols: MediciLines: Model (Xsim)

oten

tial, s

(V

0

1

0 0

Vs, Vd

L 1 m, R 10 nm, Tox 3 nm

n C

urre

nt,

I d

10-11

10-10

10-9

10-8

10

V (V) 2 1 0 1 2

Sur

face

Po

-2

-1

0, 0 0, 1 1, 0 0, 0.50.5, 0

2 1 0 1 2

Dra

in

10-15

10-14

10-13

10-12

0.050.61.2

Vds (V)

M,s/d = 4.6 eV

ElectronVg

T

Flatband-Shifted GateSource Voltage, Vgs VFB (V)

-2 -1 0 1 2

GateSource Voltage, Vgs (V)

-2 -1 0 1 2

Hole tunneling

Electrontunneling

Electron thermionic

VdVsTSiS D

Tox

No drift-diffusion! Vg

0L

y

Body Gate Oxide

Gaussian box

Medici: two-carrier Xsim: sum of two

unipolar (I + I )Ambipolar possible in undoped SB MOS with mid gap

X. ZHOU 29 © 2011

xy

Schottky Contactunipolar (Ids,n + Ids,p)SB-MOS with mid-gap M,s/d

SBSB--MOS: Total Current = (Electron + Hole) CurrentsMOS: Total Current = (Electron + Hole) Currents

IEEE-EDS / DL EEE / NTU

SBSB MOS: Total Current (Electron Hole) CurrentsMOS: Total Current (Electron Hole) Currents

10 5

10-4

n

A/

m)

10-8

10-7

10-6

10-5 n

Symbols: MediciLines: Model (Xsim)nt

, Ids

(A

10-11

10-10

10-9

10-8

n + p

Ambipolar(In + Ip)current

Lines: Model (Xsim)

n C

urre

n

10-14

10-13

10-12

10

00.3

Vgs (V)M,s/d = 4.6 eV

n + p

Dra

i

10-17

10-16

10-15

100.60.91.2

L = 65 nm T = 20 nm T = 3 nm

p

Drain Source Voltage V (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.010-18

10 L = 65 nm, TSi = 20 nm, Tox = 3 nm

X. ZHOU 30 © 2011

DrainSource Voltage, Vds (V)

Page 16: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

SBSB--MOS: Model Applied to Measured SBMOS: Model Applied to Measured SB--MOSMOS

IEEE-EDS / DL EEE / NTU

SBSB MOS: Model Applied to Measured SBMOS: Model Applied to Measured SB MOSMOS

nMOS operation (+Vds) pMOS operation ( Vds)

-4-3

L = 200 nm, R = 12.5 nm, Tox = 28 nm -4-3

L = 200 nm, R = 12.5 nm, Tox = 28 nm

nMOS operation (+Vds) pMOS operation (Vds)

s) (

A/

m)

10-9-8-7-6-5

Vds (V) ) (A

/ m

)

-9-8-7-6-54

Vds (V)

Symbols: MeasurementLines: Model (Xsim)

log(

I ds

15-14-13-12-11-10 0.05

0.30.61.22.5 (a)

M,s = 4.73 eV

M,d = 4.77 eVSymbols: MeasurementLines: Model (Xsim)

log(

I ds

15-14-13-12-11-10 -0.05

-0.3-0.6-1.2-2.5

ds ( )

(b)M,s = 4.73 eV

M,d = 4.77 eV

GateSource Voltage, Vgs (V)

-4 -2 0 2 4-15 Lines: Model (Xsim)

GateSource Voltage, Vgs (V)

-4 -2 0 2 4-15

( )M,d

SB-MOS model comparison with Measurement.(Same model and same device with different bias)

G J Zhu et al T ED 56(5) p 1100 May 2009

X. ZHOU 31 © 2011

G. J. Zhu, et al., T-ED, 56(5), p. 1100, May 2009.

DSSDSS--SiNW: Subcircuit ModelSiNW: Subcircuit Model

IEEE-EDS / DL EEE / NTU

DSSDSS SiNW: Subcircuit ModelSiNW: Subcircuit Model

Vg

Tox

r

Dopant-Segregated Schottky (DSS) SiNW:

S DVs Vd2R

Tox

0R

Dopant Segregated Schottky (DSS) SiNW:

• Thermionic/tunneling (TT) + drift-diffusion (DD)• The unique convex curvature in Ids–Vds can

only be modeled by a subcircuit model:

Symbols: TCAD (Medici)Lines: Model (Xsim)

40Symbols: MesurementLines: Model (Xsim)5

-4-3

L = 100 nm, R = 10 nm Tox = 2nm

Vg

y0 Lseg Lg

only be modeled by a subcircuit model:SBD (TT) + MOS (DD)

Lines: Model (Xsim)

urr

ent,

I ds

(A

)

20

30

0.5 1.0 1.5 2.0

g ds

Lines: Model (Xsim)

Cur

rent

, Ids

(A

)

11-10-9-8-7-6-5

VgSB MOS

0 0 0 5 1 0 1 5 2 0

Dra

in C

u

0

10

0 5 0 0 0 5 1 0 1 5 2 0 2 5

Dra

in C

-16-15-14-13-12-11

Vs VdVs'Leff

gS OS

DSS MOS

DSS-SiNW MOS subcircuit model comparison with Measurement.

DrainSource Voltage, Vds (V)

0.0 0.5 1.0 1.5 2.0

GateSource Voltage, Vgs (V)

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

X. ZHOU 32 © 2011

G. J. Zhu, et al., SSDM, p. 402, Oct. 2009; T-ED, 57(4), p. 772, Apr. 2010.

Page 17: IEEE-EDS / DL EEE / NTU U ifi ti f MOS C t M d l ith ... · MOSFET Compact Models: History and Future IEEE-EDS / DL EEE / NTU 1966 1978 1985 1995 2005 MOSFET Compact Models: History

DSSDSS--SiNWSiNW:: SubcircuitSubcircuit Model for Two Measured DevicesModel for Two Measured Devices

IEEE-EDS / DL EEE / NTU

DSSDSS SiNWSiNW: : SubcircuitSubcircuit Model for Two Measured DevicesModel for Two Measured Devices

(a) Device 1

A) 12 Lg = 40 nm, R = 10 nm Tox = 4 nmVgs (V) (c)

25Symbols: MesurementLi M d l (X i )

Lg = 40 nm, R = 10 nm Tox = 4 nm

rren

t, I d

s (

A

6

8

100.60.81.01.21.41.6

g

e, g

ds (S

)

15

20

Lines: Model (Xsim)g

Vgs = 1 V

Dra

in C

ur

0

2

4

1.61.82

Con

duct

anc

10

15

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

(b) Device 2

s (

A)

10

12

14

0.60 8

Symbols: MesurementLines: Model (Xsim)

Vgs (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Dra

in C

0

5Device 1Device 2

n C

urre

nt,

I ds

4

6

8

10 0.81.01.21.41.61.82 0

DrainSource Voltage, Vds (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

DSS-SiNW MOS subcircuit modeli ith t d d i

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Dra

in

0

22.0 comparison with two measured devices:

Device 1: normal concave curvatureDevice 2: unique convex curvature

X. ZHOU 33 © 2011

DrainSource Voltage, Vds (V) G. J. Zhu, et al., T-ED, 57(4), p. 772, Apr. 2010.

XsimXsim: Basic Bulk: Basic Bulk--MOS Model ParametersMOS Model Parameters

IEEE-EDS / DL EEE / NTU

XsimXsim: Basic Bulk: Basic Bulk MOS Model ParametersMOS Model Parameters

Physical parameters [6] Total: 33 basic parameters Physical parameters [6] Oxide thickness (Tox), S/D junction depth (Xj) Doping: channel (Nch), gate (Ngate), S/D (Nsd), overlap (Nov)

AC/Poly/QM parameters [8]

Total: 33 basic parameters

(less for DG/GAA)

AC/Poly/QM parameters [8] Bulk charge sharing (BCS): channel (c), gate (p), overlap (ov) Potential barrier lowering (PBL): accumulation (acc), depletion/inversion (ds)

E t i i l t l d ( ) i i /b lk h f t ( ) Extrinsic: lateral spread (), inversion/bulk charge factor (i, b) DC parameters [19]

Mobility: vertical-field mobility (, 2, 3, ) Effective field: vertical (n, b), lateral (L) PBL: accumulation (acc), depletion/inversion (ds), long-channel DIBL (dibl) BCL/lateral-doping: BCL (), halo-peak (), halo-spread (), halo-centroid (l) Series resistance: bias-dependent (), bias-independent () Velocity saturation (vsat), velocity overshoot (), effective D/S voltage (s)

Smoothing parameters — internal model requirement

X. ZHOU 34 © 2011

g p q