112 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Concurrent Error Detection of Binary andNonbinary OLS Parallel Decoders

Kazuteru Namba, Member, IEEE, and Fabrizio Lombardi, Fellow, IEEE

Abstract—This paper presents a concurrent error detection(CED) scheme for orthogonal Latin square (OLS) parallel de-coders. Different from a CED scheme found in the technicalliterature that protects only the syndrome generator, the proposedCED scheme protects the whole OLS decoder for single stuck-atfaults. This paper presents the detailed design and analysis ofthe proposed CED scheme and shows that it is strongly faultsecured for single stuck-at faults. Extensive simulation resultsare also provided; different figures of merit such as area, powerdissipation, gate depth, and coverage are assessed. It is shown thatthe proposed decoder designs for (n, k) t-bit error correcting OLScodes (k = 16 · · · 256; t = 2 · · · 5) have reasonable overhead;for example, the average area overhead of the proposed CED is35.5 (23.6) % compared with an OLS decoder with no CED (i.e.,the previously reported CED scheme). However, the most signif-icant advantage of the proposed scheme is that it achieves 100%fault coverage for the whole CED circuit, thus providing a veryefficient and fully fault-tolerant implementation. The proposedCED is applicable to both binary and nonbinary OLS codes; theCED for a nonbinary OLS decoder achieves comparable or betterresults than a binary OLS decoder. Moreover, simulation showsthat the proposed CED scheme is better than double modularredundancy.

Index Terms—Error correcting code (ECC), concurrent errordetection (CED), strongly fault secure (SFS), orthogonal Latinsquare (OLS) codes, parallel decoder.

I. INTRODUCTION

R ECENTLY, memory systems have experienced significanttechnology developments; so-called emerging designs

and technologies provide higher density and lower costs thana traditional dynamic random access memory (DRAM). Forexample, the zero-capacitor RAM (Z-RAM) is a new class ofvoltage RAM [1]; the Z-RAM is expected to achieve a higherdensity while operating at a supply voltage lower than for aDRAM. A non-volatile based memory (NVM) system (suchas a NAND CMOS-based flash memory) is economic, but thistechnology is encountering major challenges due to scaling.The phase change memory (PCM) is one of the most promisingtechnologies for a NVM system [2]; PCM is already providinga higher density and lower costs than DRAM. In addition toPCM, the resistive RAM (ReRAM, RRAM) [3], the conductivebridging RAM (CBRAM) [4] and the spin-transfer torque RAM

Manuscript received August 31, 2013; revised December 27, 2013; acceptedJanuary 6, 2014. Date of publication January 14, 2014; date of current versionMarch 4, 2014.

K. Namba is with the Graduate School of Advanced Integration Science,Chiba University, Chiba 263-8522, Japan (e-mail: namba@ieee.org).

F. Lombardi is with the Department of Electrical and Computer Engineer-ing, Northeastern University, Boston, MA 02115 USA (e-mail: lombardi@ece.neu.edu).

Digital Object Identifier 10.1109/TDMR.2014.2300101

(STT-RAM) [5] have been proposed as explorative technologiesfor implementing a NVM system.

However, these technologies are still facing significant chal-lenges for attaining an acceptable level of reliable operation.For example, multilevel memory systems using PCM [6] havea high storage density; however, this is achieved by reducingthe margin between adjacent resistive levels of a cell, thuslikely degrading data integrity in the presence of noise anddrift [7]. So, error tolerance for emerging memory systems isof increasing importance. Error correcting codes (also referredas error control codes, ECCs) are frequently used for improvingthe reliability of a memory system [8]. Orthogonal Latin Square(OLS) codes have drawn considerable attention in the last fewyears [9]–[11]; OLS codes provide multiple-bit error correction[12] and utilize high-speed parallel decoding by using one-stepmajority-logic decoding (OSMLGD) [8].

Errors are controlled in a memory system by using encodersand decoders for ECCs; however, ECCs do not protect fromerrors in the encoders and decoders. Control of these errorsis usually accomplished by concurrent error detection (CED).One of the most-used CED scheme utilizes double modularredundancy (DMR), in which circuits are simply duplicatedand their outputs compared. DMR is applicable to any circuit;however, it incurs in a large hardware overhead (more than100%) due to the additional checking hardware for the twocopies. An extensive literature exists on CED schemes forspecific and commonly used circuits (such as ECC encodersand decoders, [13] for Reed-Solomon codes and [14] forEG-LDPC codes); however these approaches cannot always begeneralized.

Reviriego, et al. have presented in [15] a CED scheme forOLS codes in OLS decoders. This scheme protects the entireOLS encoders, but only part of the decoders, i.e. the syndromegenerator. The remaining circuits commonly found as partsof the OLS decoders are not protected. Initially, this paperprovides experimental evidence that as it protects only thesyndrome generator, the CED scheme of [15] does not providecomplete coverage for the entire OLS decoders. Specifically,this CED scheme [15] achieves 100% coverage for only 43.4%(on average) of the circuit area of the OLS decoders (as corre-sponding to the syndrome generator); hence, a CED scheme forthe entire OLS decoder is required.

This paper then presents a CED scheme that protects theentire circuit of the OLS parallel decoders at 100% coverageof single stuck-at faults. A detailed analysis of the design andits properties is pursued to complement the initial findings of[19]; it is proved that the proposed CED scheme is stronglyfault secure for single stuck-at faults. Extensive simulation

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NAMBA AND LOMBARDI: CED OF BINARY AND NONBINARY OLS PARALLEL DECODERS 113

results are provided; different figures of merit (such as area,power dissipation, gate depth and coverage) are assessed forits implementation. It is shown that the proposed decodersfor (n, k) t-bit error correcting OLS codes (k = 16 · · · 256;t = 2 · · · 5) have an acceptable overhead (better than a doublemodular redundancy for example). For example the averagearea overhead of the proposed CED is 35.5 (23.6) % comparedto an OLS decoder with no CED (the previously reportedCED scheme of [15]). It is also shown that the proposed CEDscheme can be used for non-binary OLS codes as applicable toPCM [2].

II. PRELIMINARIES

The OLS code [12] is reviewed. The OLS code uses orthog-onal Latin squares, which are m×m square arrays of digits0, 1, . . . ,m− 1. The following matrix H is an H matrix (i.e. aparity check matrix) of a t-bit error correcting OLS code:

H =

⎡⎢⎢⎢⎢⎣

M1

M2

M3 I2tm...

M2t

⎤⎥⎥⎥⎥⎦

where Mi (1 ≤ i ≤ 2t) is an m×m2 matrix generated fromthe m×m orthogonal Latin squares. The generation of thematrices Mi has been presented in [12].

OLS codes can be decoded using OSMLGD [8] as follows.Let Sj be a vector that contains all i-th elements in a syndromesuch that hi,j in the H matrix is 1. Suppose that a t-bit erroroccurs on a received word u. If the i-th bit in u is erroneous,then the values of at least (t+ 1) bits in Sj are 1’s. If not, thevalues of at least t bits are 0’s. Based on these conditions, errorscan be corrected by simply flipping all received bits, such thatat least (t+ 1) bits in Sj are 1’s, i.e. by adding the majority ofall values in Sj and a value 0 to all received bits.

Next, the existing CED proposed in [15] is reviewed; theCED is for the syndrome generator in an OLS decoder. Then, itis shown that the CED scheme of [15] achieves CED with 100%coverage for only a relatively small part of the OLS decoders.

Note that this paper uses the following terminology for“error” and “fault” (as also found in the technical literature):

• “Error” represents an error occurring outside the ECCdecoder and its checker, i.e. in this case occurring inmemory. Errors must be controlled by the ECC, and notby the CED.

• “Fault” represents a fault occurring in the decoder or itschecker. Faults must be detected by the CED.

The CED of [15] is totally self-checking (TSC [16]) forsingle stuck-at faults at gate-level (faults at the input(s) andoutput(s) of gates). The CED circuit outputs rsyn1 and rsyn2as fault detection signals. So, if no fault occurs, rsyn1 = rsyn2;if a fault occurs, rsyn1 �= rsyn2, thus achieving detection. Theoutputs rsyn1 and rsyn2 are the parity of the check bits c and thesyndrome s; they are expressed as rryn1 = ⊕ c and rsyn2 = ⊕ swhere ⊕x is a parity of a vector x, i.e. ⊕ x = 0 (1) if the

Fig. 1. Area ratio of syndrome generator in OLS decoder versus differentvalues of t and k.

Hamming weight of x is even (odd). The interested readershould refer to [15] for more detail.

This paper does not discuss any scenario following faultdetection; these scenarios have been extensively analyzed inthe technical literature [16]. For example, a fail-safe systemcan be designed following detection; this system stops in a“harmless” mode such that operation can be continued, albeit ata lower level of functionality. However, this feature affects otherreliability metrics such as the mean time to failure (MTTF);the value of the MTTF of a fail-safe system is smaller thanfor a no fail-safe system due to the area overhead of the CED.The fail-safe property however is highly desirable in manyapplications. Additional system-level features (such as repairor recomputation) can also be implemented following faultdetection to further improve the tolerance to faults and continueoperation; also in these cases, the area overhead for the CEDand other units must be accounted.

The CED of [15] does not provide 100% fault coverage forthe entire OLS decoder; Fig. 1 shows the area ratio of thesyndrome generator to the entire OLS decoder circuit versusdifferent values of k (word length) and t. The area ratio is43.4% on average; on the assumption that faults are normallydistributed in occurrence over the entire OLS decoder, then theCED for the syndrome generator of [15] achieves 100% faultcoverage for only 43.4% the OLS decoder (i.e. 100% coveragefor the syndrome generator). This implies that the goal of 100%coverage for the entire OLS decoder requires a new scheme forCED of the remaining circuits not protected by [15].

III. PROPOSED CED DESIGN

This section shows the design of the proposed CED scheme.Let ci be a sub-vector of check bits c corresponding to Mi. ci isgenerated as ci = dMT

i where d denotes the information bits;so, c = (c1 c2 · · · c2t) and the length of ci is m. Let si be a sub-vector of the syndrome s corresponding to Mi. si is found as

114 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Fig. 2. Decoder design using proposed CED.

Fig. 3. roth1 generator.

si = uMTi ⊕ ci where u is the information bits in a received

word, s = (s1 s2 · · · s2t) and the length of si is m.Fig. 2 shows the construction of the OLS decoder by the

proposed CED scheme; the decoder includes the roth1 gen-erator, (its construction is shown in Fig. 3). As shown in alater section, the proposed CED is strongly fault secure (SFS[17]) for single stuck-at faults at the inputs and outputs of thegates. It requires two pairs of signals for fault detection: (rsyn1,rsyn2) and (roth1, roth2). If no fault occurs, rsyn1 = rsyn2 androth1 = roth2. If a single stuck-at fault occurs, either or bothrsyn1 �= rsyn2 and/or roth1 �= roth2, thus detecting the fault.The two pairs can be combined into a single pair(r1, r2) using atraditional two-rail checker; r1 = rsyn1roth2 + rsyn2roth1 andr2 = rsyn1roth1 + rsyn2roth2.

The signal roth1 is generated in the roth1 generator; thisconsists of a MUX and two circuits, denoted as MAJ and EQ.The MAJ circuit is a 2t-input majority voter (and is also usedin the error calculator of the OLS decoder). MAJ outputs a “0”if the number of “1”s is equal to that of “0”. The EQ circuitoutputs a “1” if and only if the number of “1” is equal to “0”.Otherwise, EQ outputs a “0”. The signal roth1 is a function of⊕ ci and ⊕ si, and it can be expressed as follows:

roth1 =

⎧⎪⎪⎨⎪⎪⎩

maj(⊕ c1,⊕ c2, . . . ,⊕ c2t, 0)

(2t∑i=1

⊕ si �= t

)

(⊕ c1) + (⊕ s1)

(2t∑i=1

⊕ si = t

)

where maj(. . .) is the majority of the input values; the followingcondition is then applicable:

maj(⊕ c1,⊕ c2, . . . ,⊕ c2t, 0) =

⎧⎪⎪⎨⎪⎪⎩

1

(2t∑i=1

⊕ ci > t

)

0

(2t∑i=1

⊕ ci ≤ t

) .

The signal roth2 is the parity of the decoded word v, i.e. it istrue that roth2 = ⊕ v

The proposed CED scheme utilizes the CED circuitry forthe syndrome generator of [15], i.e. the scheme for generatingrsyn1 and rsyn2 is the CED of [15]. The operations ⊕ ci and⊕ si can be shared with the roth1 generator; rsyn1 and rsyn2 aregiven by rsyn1 = ⊕2t

i=1 ⊕ ci and rsyn2 = ⊕2ti=1 ⊕ si. If a fault

occurs on the syndrome generator, detection is accomplished byrsyn1 �= rsyn2.

Initially, consider the case when no fault occurs. The decoderoutputs the correct information bits, while the checker outputsthe fault detection signals, such that rsyn1 = rsyn2 and roth1 =roth2 even if a correctable error (t-bit error) occurs as explainedbelow. The following Lemma is therefore applicable.

Lemma 1: For any k-dimensional vector x, ⊕ x = ⊕ xMTi .

This Lemma is valid, because there is exactly one “1” for anycolumns in Mi. The check bits ci are generated as ci = dMT

i

from the information bits d, therefore ⊕ ci = ⊕ d.The OLS decoder of [15] is used with no modification in the

proposed design, although some internal signals are utilized bythe checker. Thus, the decoder outputs the correct informationbits even when a correctable error occurs. Next, it is shown thatthe fault detection signals of this design satisfies the conditionsrsyn1 = rsyn2 and roth1 = roth2.

• If no error occurs, for the received information bits uand the check bits ci, ⊕ u = ⊕ ci. As ⊕ ci is constantregardless of i, then it is valid to establish that

2t∑i=1

⊕ ci = 2t(⊕ u).

Thus, MAJ outputs ⊕ u. As there is no error, the syndromeis all-zero and the inputs of EQ are all-zero. Thus, theoutput value of MAJ is selected as roth1. The decodedword v is the same as u, because there is no error. So,roth2 = ⊕ u and roth1 = roth2.

• Assume that a correctable error e occurs on the informa-tion bits u and u′ = u+ e is received; no error occurson the check bits (where x′ represents x when the erroroccurs). As there is no error on the check bits, then theoutput value of MAJ does not change from ⊕ u. Hence

s′i =u′MTi + c′i = (u+ e)MT

i + ci

= si + eMTi = eMT

i .

So, it follows that:

⊕ s′i = ⊕ eMTi = ⊕ e.

Thus, ⊕ s′i is constant regardless of i and so∑2t

i=1

⊕s′i = 0 or 2t; the output value of EQ is 0. As a result,

NAMBA AND LOMBARDI: CED OF BINARY AND NONBINARY OLS PARALLEL DECODERS 115

r′oth1 = ⊕ u. As the error is correctable, then the decodedword v is equal to the correct word u. Thus, r′oth2 = ⊕ uand therefore r′oth1 = r′oth2

• Assume that an error e occurs on the information bits andthe value x changes to x′, i.e. u′ = u+ e. In addition,the errors ei occur on the check bits ci and the valuex′ changes to x′′, therefore c′′i = c′i + ei. Assume thatw(e) +

∑i w(e) ≤ t and

∑i w(ei) < t(where w(x) is the

Hamming weight of vector x). So, the errors e, ei arecorrectable. As

∑i w(ei) < t, then it is true that∣∣∣∣∣

2t∑i=1

⊕ c′i −2t∑i=1

⊕ c′′i

∣∣∣∣∣ < t.

As shown previously,∑2t

i=1 ⊕ c′i = 2t(⊕ u). If ⊕ u = 0,then

∑2ti=1 ⊕ c′′i < t and MAJ outputs a 0. If ⊕ u = 1,∑2t

i=1 ⊕ c′′i > t and MAJ outputs a 1. Therefore, MAJoutputs ⊕ u and it is established that

s′′i =u′′MTi + c′′i = (u+ e)MT

i + ci + ei

= s′i + ei.

As∑

i w(ei) < t, then the following is valid:∣∣∣∣∣2t∑i=1

⊕ s′i −2t∑i=1

⊕ s′′i

∣∣∣∣∣ < t.

Moreover as∑2t

i=1 ⊕ s′i = 0 or 2t; then either∑2ti=1 ⊕ s′′i < t or

∑2ti=1 ⊕ s′′i > t is true. In either

case,∑2t

i=1 ⊕ si �= t; EQ outputs a 0 and r′′oth1 = ⊕ u.As the error is correctable, it follows that r′′oth2 = ⊕ u andtherefore, r′′oth1 = r′′oth2.

• Assume that the errors ei occur in the check bits, suchthat

∑i w(e) = t and the value x change to x′′, so c′′i =

ci + ei; no error occurs on the information bits. If thenumber of non-zero ⊕ ei is less than t, r′′oth1 = r′′oth2 (justas in the previously treated case). If the number of non-zero ⊕ ei is equal to t, then

∑2ti=1 ⊕ s′i = t. So, r′′oth1 =

(⊕ c′′1) + (⊕ s′′1). As there is no error on the informationbits, it follows that s′′i = ei. So, it is established that

r′′oth1 = (⊕ c′′1) + (⊕ s′′1)

= (⊕(c1 + e1)) + (⊕ e1)

= ⊕ c1

= ⊕ u.

The error is correctable, so r′′oth2 = ⊕ u; r′′oth1 = r′′oth2.In conclusion, r′′oth1 = r′′oth2 for any correctable error, hence

proving the CED properties of the proposed scheme.

IV. FAULT DETECTION OF PROPOSED CED

This section shows that the proposed CED is SFS for singlestuck-at faults. Initially, an important feature of the error patterncalculator is presented; next it is shown that the proposed CEDis fault secure and finally, its SFS property is outlined.

Fig. 4. Error pattern calculator for the (21, 9) OLS code.

The error pattern calculator consists of majority voters (Fig. 4shows the error pattern calculator for the (21, 9) OLS code);the voters are completely separated in the output bit. Voterscould share few gates to reduce the area overhead; however,the H matrix of the OLS code satisfies the RC constraint andthis does not allow the use of shared gates. Hence, every singlestuck-at fault on a voter affects no more than two outputs of thecalculator.

Next, it is shown that the proposed CED is fault secure forsingle stuck-at faults. Even if a fault occurs on the checker, thefault does not affect the decoded word v and thus, the decoderoutputs v correctly, regardless of whether the fault is detected ornot. Assume that a fault occurs on the syndrome generator. Asthe syndrome generator is TSC, then either the fault is detected,or the generator outputs the correct syndrome. If the generatoroutputs the correct syndrome, the decoder outputs the correct v,because there is no fault other than in the syndrome generator.If a fault occurs in the error pattern calculator, then at most abit in e flips. If there is no bit flipping in e, then the decoderoutputs the correct v. If a bit flips in e, then the correspondingbit in v flips too; hence, roth2 flips too. As the fault does notaffect roth1, then the fault is detected. If a fault occurs on anXOR gate calculating u+ v, it flips exactly one bit in v andthen roth2 flips too. Also in this case, roth1 does not change andso, the fault is detected.

Consider next the SFS property. In circuits without the TSCproperty, there may exist faults that are not detected for anyinput. Let P be a system and let P ′ be a sub-system in P .Assume that a fault f occurs in P , but f is not detected. Thefault f can cause erroneous system outputs when another faultf ′ occurs in P .

There are three cases in which f is sensitized by anotherfault f ′:

• The fault f is not sensitized to the output of P ’ before f ′

occurs, so the fault f is not sensitized to the output of P ′

by supplying a vector x to the input of P ′. However xnever appears at the input prior to the occurrence of f ′. Thefault f ′ makes x to appear at the input.

• The fault f ′ occurs inside P .• The fault f is sensitized to the output of P ′ but not to the

output ofP before f ′ occurs. The fault f ′ occurring outsideof P ′ causes to sensitize it from the output of P ′ to theoutput of P .

116 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

However, the SFS property does not allow these cases toexist; therefore, next it is shown that the proposed CED is SFSfor single stuck-at faults.

• The syndrome generator and its checker are TSC. Inaddition, its inputs and the error detection signals rsyn1and rsyn2 are controllable and observable. So, there is nofault that is not detected by any input.

• Assume a fault f occurs on the error pattern calculator. Ifanother fault f ′ changes the input value, then it is detectedby the checker for the syndrome generator. The calculatorconsists of MAJs that are fully separated. Thus, if f ′ in thecalculator sensitizes f , then they must occur on the sameMAJ. This is equivalent to the case in which a single faultoccurs on the calculator. The output of the error patterncalculator is always sensitized to roth2.

• Every fault in the XOR gates (that calculates u+ v) flipsexactly one bit in v, and in turn, it flips roth2.

• Every fault in the XOR tree for roth2 flips roth2 and so, itis detected.

• Assume a fault f occurs in the roth1 generator. If anotherfault f ′ changes the input value, then it flips either rsyn1 orrsyn2. This is detected. If f ′ in the generator sensitizes f ,then this flips roth1, but it does not flip roth2. Therefore,it is detected because the output of the roth1 generator isdirectly connected to roth1.

From the above observations, it is possible to conclude thatthe proposed CED is SFS for any single stuck-at faults.

V. EVALUATION

This section evaluates the proposed OLS decoder with CED.In this evaluation, the proposed decoders for (n, k) t-bit er-ror correcting OLS codes (k = 16 · · · 256; t = 2 · · · 5) are de-signed by using the Synopsys Design Compiler. The DesignComplier could invalidate the SFS property of the proposedscheme; so each circuit (namely the syndrome generator, theerror pattern calculator, the roth1 generator and the XORs) isindividually compiled as a so-called separate group; then, allcircuits are assembled together but with no grouping [19]. TheOLS decoders with the CED scheme for the syndrome genera-tor of [15], the OLS decoders with DMR and the OLS decoderswithout CED are also designed for comparison purposes withother schemes. DMR requires a comparator for the outputs ofduplicated modules; the comparator uses a two-rail checker.Different figures of merits are evaluated.

• Fig. 5 shows the normalized area overheads for both CEDschemes, i.e. the area ratios of the OLS decoder with-out CED to either (Ssyn_chk + Soth_chk)/(Ssyn + Soth)for the proposed CED or Ssyn_chk/(Ssyn + Soth) for theCED of [15]. Note that Ssyn_chk, Soth_chk, (Ssyn, Soth)denote the areas of the checker for the syndrome gener-ator and the remaining circuits (the syndrome generatorand the remaining circuits parts) in the proposed scheme(the scheme of [15]). In addition, this figure shows thearea overhead for DMR, i.e. 1 + Scomp/(Ssyn + Soth)where Scomp denotes the area of the comparator. Theaverage values of (Ssyn_chk + Soth_chk)/(Ssyn + Soth)

Fig. 5. Area overhead for CED (normalized by decoder without CED).

Fig. 6. Power consumption overhead for CED (normalized by decoderwithout CED).

and Ssyn_chk/(Ssyn + Soth) are 35.5% and 23.6%. Hence,these are reasonable ratios because the average value ofSsyn_chk/Ssyn is 55.7%; the area overhead however issmaller for larger values of k. The average value of 1 +Scomp/(Ssyn + Soth) is 119.4%; hence, the area of theproposed CED scheme is significantly smaller than DMR.

• Fig. 6 shows the normalized overhead in power consump-tion (utilizing the same comparative conditions as usedpreviously for the area overhead).

• Fig. 7 shows the gate depth of the OLS decoders withand without CED (normalized by an inverter). The use ofthe proposed CED increases the gate depth by 18 ∼ 34.The proposed CED achieves a reduction of 6 ∼ 29 ingate depth than DMR. Fig. 8 shows the gate depth of theproposed scheme; the increase is mostly caused by theroth1 generator and the XOR-tree for calculating roth2.

• Fig. 9 shows the relation between the normalized areaoverhead and fault coverage. The use of the CED for the

NAMBA AND LOMBARDI: CED OF BINARY AND NONBINARY OLS PARALLEL DECODERS 117

Fig. 7. Gate depth of OLS decoder with CED (normalized by an inverter).

Fig. 8. Gate depth of OLS decoder with CED (normalized by an inverter).

syndrome generator increases the area overhead and thefault coverage by 23.6% and 43.4% on average. The useof the proposed CED increases them to 35.5% and 100%.As shown in Fig. 9, the slope for the plot of the proposedCED for all (t, k) values except (2, 16) is lower than theCED for the syndrome generator, hence the proposed CEDprovides an efficient design. DMR (not shown in Fig. 9)also achieves 100% fault coverage; however it incurs in asignificantly larger hardware overhead than the proposedscheme (as shown previously in Fig. 5).

VI. PIPELINED CED SCHEME

As mentioned in the previous section and in [19], the use ofthe proposed CED increases the gate depth; this decreases theclock frequency of the decoder. This issue can be resolved bypipelining the CED scheme; Fig. 10 shows the pipelined CEDversion of the proposed scheme. As mentioned in the previoussection the roth1 generator and the XOR-tree for calculating

Fig. 9. Area overhead versus fault coverage.

Fig. 10. Pipelined CED scheme.

roth2 increase the delay time; these circuits operate in differentstages. In this case, the clock frequency is nearly the same as forthe case with no CED. The pipelined CED scheme outputs thedecoded words at the same clock frequency as the words arereceived at the inputs (i.e. in a fashion similar to the originalparallel decoder); the check results are then provided at theoutputs of the next clock cycle. So, a latency still exists. Twopossible options are available in this case.

• Do not use the decoded words till the output of the checkresults is available.

• Use the decoded words before the output of the checkresults.

118 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 1, MARCH 2014

Fig. 11. Majority voter for non-binary OLS decoder.

In the former case, the scheme still retains the SFS property;in the latter case albeit incurring in a small latency, the designof the entire system must allow this additional delay in itsoperation.

VII. CED FOR NON-BINARY OLS CODES

Consider next the cases of a CED for non-binary OLS codes.These codes are applicable to multilevel storage (such as phasecharge memories [2]) in which a higher base is utilized in a cellto increase capacity. The interested reader should refer to [18]for a detailed discussion of non-binary OLS codes for PCM. Itis then possible to use the H matrix of an (n bits, k bits) binaryt-bit error correcting OLS code as an H matrix for (n symbols, ksymbols) t-symbol error correcting code. The H matrix consistsof only additive and multiplicative identities, 0 and 1.

For example, the matrix H of a (21, 9) binary double-biterror correcting OLS in (2) can be used as the H matrix for a(21, 9) double-symbol error correcting OLS code over GF(22).Consider the information data d = (123 000 000), its codewordappears as u = (123 000 000 | 000 123 123 123); uHT = 0 istrue over GF(22).

We can decode the non-binary OLS code using OSMLGD,that requires a non-binary majority circuit. Fig. 11 illustratesan example of a majority circuit for a double-symbol errorcorrecting OLS code over GF(23); it generates the majorityfor every bit in the binary-coded digits. This circuit does notalways work as a majority circuit; however, it has sufficientfunctionality for use in the non-binary OLS decoder. For exam-ple, if Sj = (3, 3, 4, 5) = (011, 011, 100, 101), then it outputs1 = (001) although the majority is 3. However, such Sj doesnot appear when a t-symbol error occurs, because at least t+ 1symbols in Sj are equal to the error magnitude ej , and thus,every bit in the binary-coded ej is selected as the majority ofeach digit.

Fig. 12 illustrates the proposed CEDs for non-binary OLScodes; this figure shows an example over GF(23). It utilizesonly one checker; so, ⊕ ci, ⊕ si and roth2 are included in theXOR gates prior to the checker. Let x[i] be x for the i-th bit inthe binary-coded digits; the following equations are true:

⊕ ci = ⊕j ⊕ ci[j]

⊕ si = ⊕j ⊕ si[j]

roth2 = ⊕j roth2[j].

Fig. 12. Non-binary OLS decoder with CED.

The other detection signals rsyn1, rsyn2 and roth1 are generatedfrom ⊕ ci and ⊕ si in the same manner as for the binary case.This CED is shown to be SFS for stuck-at faults as follows.

Initially, consider the case in which no fault or error occurs.If so, ⊕ u[j] = ⊕ ci[j] is true for any j and it is correct toestablish that

2t∑i=1

⊕j⊕ ci[j] =

2t∑i=1

⊕j⊕ u[j].

So, the output value of MAJ in the roth1 generator appearsas ⊕j ⊕ u[j], i.e. it is equal to roth2. Since the syndromeis all-zero, then the output value of MAJ is selected as roth1and therefore roth1 = roth2. This is the same as for the binarycase, except that u, ci, ⊕ u and ⊕ ci are replaced with u[j],ci[j], ⊕j ⊕ u and ⊕j ⊕ ci. It is then possible to show thatroth1 = roth2 for any correctable errors in a similar manner byreplacing x and ⊕ x by x[j] and ⊕j ⊕ x (x = u, e, ci, si andei) in the discussion presented previously for the binary case.

Consider the fault secure property. If a fault occurs on thesyndrome generator, the error calculator (MAJs) or an XORgate (that calculates u+ v) for a j-th bit in the binary-codeddigits, then the fault affects ci[j], si[j] and roth2[j], but notci[j

′], si[j ′] and roth2[j′] for any j ′( �= j). So whenever ci[j],

si[j] and roth2[j] flip, the output of the corresponding XORgates (for ci, si and roth2 as inputs) flips too; the checker detectsthe fault (if needed) just like in the binary case. Even if a faultoccurs on the XOR gates or the checker, the decoder outputs thecorrect decoded word regardless of whether the fault is detectedor not. In conclusion, the CED is fault secure also in the non-binary case.

The difference between the CEDs for binary and non-binaryOLS decoders occurs in the XOR gates (for generating theoutput for the inputs ci, si and roth2). If a fault occurs on theXOR gates for ci, si and roth2, the values of rsyn1, rsyn2 and

NAMBA AND LOMBARDI: CED OF BINARY AND NONBINARY OLS PARALLEL DECODERS 119

Fig. 13. Area overhead for CED, non-binary OLS decoder.

Fig. 14. Power consumption overhead for CED, non-binary OLS decoder.

roth2 flip, thus detecting the fault. Therefore, the proposed CEDis SFS for faults in the XOR gates. If a fault flips an input valueof one of the XOR gates, the output value always flips; thus,the SFS property is still applicable for a single stuck-at faultoutside the XOR gates, so is again similar to the binary case.

Figs. 13 and 14 show the area and power consumptionoverheads of the CED for binary and non-binary OLS decodersover GF(2b) (k = 16 · · · 256; t = 2 · · · 5; b = 1, 2, 3, 4, 8). Theplots have solid lines connecting the cases with the same (k, t);for any (k, t), the CED for a non-binary OLS decoder achievescomparable or better results than a binary OLS decoder. Fig. 15shows the gate depth of the binary and non-binary OLS de-coders with CED; for large b, the gate depth is increased, i.e.for b = 8 it is 12 (15) longer than for the binary case on average(in the worst case).

Fig. 15. Gate depth of non-binary OLS decoder with CED.

VIII. CONCLUSION

This paper has presented a concurrent error detection (CED)scheme for OLS parallel decoders. Different from an CEDscheme found in the technical literature [15] that protects onlythe syndrome generator, the proposed CED scheme protects thewhole OLS decoder for any single stuck-at fault. This paperhas presented the detailed design and analysis of the proposedCED scheme and has shown that it is SFS for any single stuck-at fault. Extensive simulation results have also been provided;different figures of merit such as area, power dissipation, gatedepth and coverage have been assessed. It has been shownthat the use of the CED for the syndrome generator of [15]increases the area overhead and the fault coverage by 23.6%and 43.4% on average. The use of the proposed CED increasesthem to 35.5% and 100% respectively. Therefore, the proposeddecoders for (n, k) t-bit error correcting OLS codes (k =16 · · · 256; t = 2 · · · 5) have modest overhead while providing100% fault coverage of the whole circuit, thus making it fullyfault tolerant. Comparison with DMR (double modular redun-dancy) has shown that the proposed CED scheme is superiorin terms of all considered figures of merit. The extension ofthe proposed scheme to CED for non-binary OLS codes hasalso been presented as applicable to emerging memories suchas PCM. It has been shown that the CED for a non-binary OLSdecoder achieves comparable or better results than a binaryOLS decoder. This paper has dealt only with CED; future workincludes the design and development of an error correctionscheme for OLS parallel decoders.

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Kazuteru Namba (M’04) received the B.E., M.E.,and Ph.D. degrees from Tokyo Institute of Technol-ogy, Yokohama, Japan, in 1997, 1999, and 2002,respectively.

In 2002, he joined Chiba University, Chiba, Japan,where he is currently an Assistant Professor with theGraduate School of Advanced Integration Science.His current research interests include dependablecomputing.

Dr. Namba is a member of the Institute of Elec-tronics, Information and Communication Engineers

and the Information Processing Society of Japan.

Fabrizio Lombardi (M’81–SM’02–F’09) receivedthe B.Sc. (Hons.) degree in electronic engineeringfrom the University of Essex, Colchester, U.K., in1977; the Master’s degree in microwaves and modernoptics and the Diploma degree in microwave engi-neering from University College London, London,U.K., both in 1978; and the Ph.D. degree from theUniversity of London, London, in 1982.

He is currently the holder of the InternationalTest Conference Endowed Chair Professorship atNortheastern University, Boston, MA, USA. He has

extensively published in his areas of research interest, which are bioinspired andnanomanufacturing/computing, very large-scale integration design, testing, andfault/defect tolerance of digital systems, and he has also coauthored or editedseven books.

Dr. Lombardi currently serves as an Elected Member of the Board ofGovernors of the IEEE Computer Society and on the Administrative/ExecutiveBoards of the IEEE Nanotechnology Council and the Computing-in-the-Corenon-partisan advocacy coalition for K-12 Computer Science education. In2007–2010, he was the Editor-in-Chief of the IEEE TRANSACTIONS ON

COMPUTERS. He is also an Associate Editor of the IEEE TRANSACTIONS ON

NANOTECHNOLOGY and the inaugural Editor-in-Chief of the IEEE TRANS-ACTIONS ON EMERGING TOPICS IN COMPUTING.