Design of an EEPROM in RFID Tag: Employing Mapped EPC and IPv6 Address

Labonnah F. Rahman #1, M.B.I. Reaz #2, M.A. Mohd. Ali#3, Masaru Kamada*4 # Dept. of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Malaysia

1labonnah @eng.ukm.my 2mamun@eng.ukm.my 3mama@eng.ukm.my

*Dept. of Computer and Information Sciences, Ibaraki University, Japan 4m.kamada@mx.ibaraki.ac.jp

Abstract— In this paper, an approach of RFID tag EEPROM circuit design is presented. The method of designing such tag EEPROM circuit with other tag modules is discussed. The main purpose of this paper is to discuss RFID tag EEPROM circuit modules based on the mapped EPC-IPv6 address format. Also, direct mapping procedure of EPC 64 bit with IPv6 address structure is presented, which will provide a universal identification number to the objects, physical location identification with seamless global mobility. The proposed methodology focused on the process of future EEPROM chip circuit to fabricate without impacting cost and/or data rates. Keywords— RFID, Active tag, EEPROM, EPC, IPv6

I. INTRODUCTION Radio Frequency Identification (RFID) is a promising and

emerging wireless technology for automated data capturing. An RFID system is a contact-less data capturing technique that uses RF waves for data transmission. A typical RFID system is comprised of a base station reader and transponders (tags). Tags/ transponders are known as data carrying devices in RFID systems. The main purpose of a transponder is to carry ID information of the object where it is placed on. As computers, RFID tags started off with greater physical dimension and power consumption and are now minimized to the scale of microscopic IC and microprocessors with low power consumption. RFID transponders are generally classified upon their power supply, and thus we can define here types of RFID transponders: Passive, Active and Semi passive transponders [1].

The passive tag is energized by an electromagnetic radio frequency (RF) wave transmitted by the reader, while the active tag is energized by a battery. Due to a great demand for longer reading distances and lower cost, there is a strong interest in low-power passive RFID tag integrated circuits. Active Tag Systems have an active radio frequency (RF) transmitter (i.e. they are capable of peer-to-peer communication) and the tags use batteries to power the logic chip and to communicate with the reader (i.e. they do not use harvested power). Read range increases (up to several kilometres) and reliability improves; active tags can be read while moving at up to 100 miles an hour (e.g. in automatic

toll-road payment systems). Semi-passive tag Systems require the tag to use battery power for the digital logic on the chip, but still use harvested power for communication [2].

Another part of RFID systems is the interrogator/reader, which interrogates the tag and extracts the data from the tag. In brief, RFID technology is based on radio waves in order to transmit data by the reader to the tag. The transponder modulates the EM wave and transmits the data back to the reader, where it is processed for real-time ID, asset tracking, security surveillance and many other authentication and management purposes [3]. The most expensive part of using RFID is the reader. For example, reader of a typical EM or RF theft detection system cost approximately $1,500 to $7,500 [4]. The most important thing is that, though RFID is an emerging technology, it is lagging behind for some limitations. Also by using the reader, we place a limitation on RFID tag implementation such as vendor specific solution and expensive implementation cost and local mobility. These drawbacks can be easily overcome by using Wi-Fi network and IPv6 address as tag ID [5].

Like the Universal Product Code (UPC), the Electronic Product Code™ (EPC) is a globally unique serial number that identifies an item in the supply chain. This allows inquiries to be made about a single instance of an item, wherever it is within the supply chain. EPC can be 64 bits or 96 bits to contain information about the manufacturer, the type of object and a specific serial number that relates to the specific object being monitored.

To identify any object or instances an identification code is required. Unique identification mechanism has the capability of secure and efficient communication. Due to the requirement of global unique address structure a new protocol known as IPv6 (IP version 6) will be used for objects-to objects communications [6]. EPC, EUI-64 (Extended Unique Identifier), MAC (Media Access Control) addresses, URI/URL, etc are some examples of identification codes. To manage a large number of different identification codes requires a large address space, so IPv6 (128 bits) network infrastructure will become vital for future network. IPv6 will provide universal any-to-any connectivity using unique local

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address with enough address space. It will enable self organization and service discovery by using auto configuration. In addition, it will provide enhanced service capabilities using IPv6 header information. Moreover, it will facilitate multi-homing using IPv6 addressing.

Portable devices or identification tools like RFID Tag, smart card or mobile communication media has a straight impact on the use of EEPROM. Indeed, EEPROM have become very significant alternative for any application requiring non-volatile semiconductor memory over the last few years’. In this paper, an innovative EEPROM circuit for RFID tagging system is introduced. This EEPROM circuit will be a low-power EEPROM circuit to store mapped EPCIPv6 address for RFID tagging system. Finally a design of low-voltage low-power circuit design techniques is employed.

II. METHODOLOGY

A. EPC-IPv6 Tag Circuit In the proposed system, a RFID tag will consists of an

antenna and an integrated circuit (IC). A memory block, rectifier, modulator, modulator, low power digital logic and RF front end will make the complete tag IC. The antenna connected with RF Front End will control the system’s data acquisition and communication. The tag contains an electronic microchip, as shown in Figure 1, which will be fabricated as a low power IC.

The tag memory block can be Electrically Erasable Programmable Read Only Memory (EEPROM), Static Random Access Memory (SRAM) or Ferroelectric Random Access memory (FRAM). In the proposed system EEPROM will be used as a storage medium and data buffer of EPC mapped IPv6 address. It will be used in a wide range of applications due to its low manufacturing cost and high number of possible reprogramming cycle.

The modulator block will be used to power the modulation of the carrier signal received from the WNIC in order to send valid signal. The demodulation block will work as a decoder towards the tag.

The rectifier circuit will be used as there will be a limiter and voltage pump circuit for either limiting or increasing the dc power. The RF front-end existing herein will be designed in a way that it will be intended to operate in the 2.4-GHz ISM band. It will be conceived to support high data rates. The RF front end will be worked as everything between the antenna and the digital base band system. It will be worked as a receiver. For a receiver, this area will include all the filters,

Low Noise Amplifiers (LNAs), and down-conversion mixer(s).

All these circuits will need to process the modulated signals received at the antenna into signals suitable for input into the base band analogue-to-digital converter (ADC). Therefore, it will work as an analogue-to digital or RF-to-base band portion of a receiver.

Figure 1. Block diagram of the proposed EPC-IPv6 Tag B. EEPROM with EPC-IPv6

The EEPROM architecture is globally similar to conventional RAM architecture and consists in an array of memory cells. In this system these cells will be used as an identifier by their row and column position. Typically this array will be surrounded by the elements like control logic and registers, row decoder, bit line decoder, high voltage generator and a sense amplifier. In figure 2 the whole architecture of the EEPROM circuit has been shown.

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The EEPROM control logic and registers will be used to

manage the interface to the RFID tag digital controller to perform the read and write operations. Different procedures will be used to store data depending on the array organization.

In addition, in order to improve the reliability it will be necessary to consider the charge and discharge of the parasitic capacitance existing on the nodes of each memory cell. Furthermore, the dummy bit cells effectively reduces the

Figure 2. Architecture of the EEPROM with EPC-IPv6 Address

A row decoder will be used to select the active row.

Whereas a bit line decoder will be used for write operation of the EPC-IPv6 address. A column decoder for selecting the active column, data and address latches. To read the EPC mapped EPC-IPv6 address a sense amplifier will be used in this proposed system.

The 2Kb EEPROM array will be arranged with 16 rows and 16 × 8 columns to store total 128bit structure of EPC-IPv6 address.

The read or write processes of the whole EEPROM memory will be operated on a byte-by-byte basis. In this proposed design, the memory array will be divided into four pages. This arrangement will increases the speed of storing EPC-IPv6 address data because the erase and write operations of the page can be worked as a whole.

impact of parasitic capacitance imposed on the array and consequently enhances the reliability and stability.

To store the mapped EPC-IPv6 address in the EEPROM memory structure a high voltage generator such as a charge pump will be used in this EEPROM design.

C.EPC-IPv6 Address Mapping IPv6 is a network protocol that succeeds IPv4 and provides

end to end connection with 128 bit address space. It helps IP-networked devices to communicate by providing secure and specific addresses to each of these devices. IPv6 eradicates the address depletion problem and future networks are based on IPv6. Figure 3 shows the address format of typical 128 bits IPv6 address.

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The first 64 bits are for the subnet portion and the last 64

bits are for the interface ID portion. Network prefix or Subnet prefix portion identifies the physical location and is determined by the router. On the other hand the interface ID portion is used for unique identification.

Figure 3. 128 bits IPv6 Address format

There is a simple algorithm of converting the MAC (Medium Access Control) address into a modified EUI-64: the global flag (7th bit) of the MAC address is inverted and the value “fffe” is inserted between the 3rd and 4th byte of the MAC address. For example, the MAC address-00:8c:a0:c2:71:35 is converted to 028c:a0ff:fec2:7135 which is 64. This EUI 64 is used as interface ID of an IPv6 address [7].

Similarly, we can map total 64 bits of EPC into IPv6 address structure and used as IPv6 Interface ID. Thus the IPv6 address will contain the whole information of EPC and find out the way to reach any object to the destination. IPv6 address as shown in Figure 1 can be one of IPv6-based unified address structures. EPC information will directly map into the Interface ID portion of the IPv6 address using direct mapping.

In a mapped EPC-IPv6 code mapping mechanism, the EUI-64 (Extensible Unique Identifier) portion of the network prefix will be replaced by the EPC (64 bit) code value [8].

Figure 4. IPv6 Address format after mapping with EPC

In figure 4 the address mapping procedure of EPC 64 bits with IPv6 address 64 bits of interface ID portion is shown. Total 64 bits of EPC will directly map into IPv6 address structure. After that this mapped address will be stored in the proposed EEPROM structure. Thus each RFID tag becomes addressable in the IPv6 network and at the same time physical location identification will also be possible.

III. CONCLUSIONS In the proposed system, an EEPROM circuit design for

RFID tagging scheme is discussed which consists of EPC mapped IPv6 address. By using this design RFID tag circuit will be able to store mapped EPC-IPv6 address into tag EEPROM section. As the RFID tag contains IPv6 address, it will be accessed from any location. Additionally, the EPC will provide the general information about the object, which is presently used. As a result, it is possible to find out the physical location of any objects. Thus, the proposed system will reduce the cost of RFID tagging system for future network of things.

ACKNOWLEDGMENT The Authors would like to express sincere gratitude to the

Ministry of Science Technology and Innovation for supporting this research project through its Brain Gain Malaysia (BGM) program.

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[3] Preradovic S., Karmakar N., Balbin I., "RFID Transponders," IEEE Microwave Magazine, vol. 9, pp. 90-103, Oct. 2008.

[4] (2003) The ALA website. [Online]. Available: http://www.ala.org/ala/mgrps/divs/pla/plapublications/platechnotes/rfid technology.cfm

[5] (2004) The World Internet Center wbsite. [Online].Available: http://www.worldinternetcenter.com/Pubs/Pubs2004/feb05

[6] Gyu Myoung Lee, Jun Kyun Choi and Taesoo Chung, "Address Structure for Supporting Ubiquitous Networking using IPv6," in Proc. of the 10th international Conference on Advanced Communication Technology, 2008, vol. 2, pp. 1088 – 1090.

[7] (2005) 6net website. [Online]. Available: http://www.6net.org/book/deployment-guide.pdf

[8] Yoon D.G., Lee D.H., Seo C.H. and Choi S.G., "RFID NetworkingMechanism Using Address Management Agent," in Proc. of the 4th International Conference on Networked Computing and Advanced Information Management, 2008, pp. 617 - 622. 128 bits

EPC-64 bits

Subnet Prefix Interface ID

64 bits 64 bits

128 bits

Subnet Prefix Interface ID

64 bits 64 bits

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