Bumpless Flip Chip Packages For CostRerformance Driven Devices

Charles W. C. Lin, Ph.D., Sam C. L. Chiang and T. K. Andrew Yang Bridge Semiconductor Corporation

3F, 157 Li-Te Roa4 Peitou District, Taipei, Taiwan, ROC. Email: charleslin@bridgesemiconductor.com

Tel: +886-2-2896-9568 Fax: +886-2-2896-9567

Abstract This paper presents a novel bumpless flip chip package for

cost/perfomce driven devices. Using the electrochemical plating (ECP) method, a pattern of fme-line traces down to 25 pm linekpace is fabricated and connected to the die pads directly without using wire-bonds or solder bumps or an interposer substrate or vacuum processes such as thin film sputtering. This method enables the production of BGA- format packages up to 256 WO using a single layer of metal.

Package-to-board level connection is made through a series of resin-filled terminals that provide excellent mechanical compliancy between the package and the assembled board. The electroplated fme-lie traces that provide signal redistribution in this package are similar to those in wafer level packages. More importantly, their “fan- out” feature is the key to enabling high lead count devices to be accommodated in the BGA format with this package.

Details of the design concepts and processing technology associated with this package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with package-level and board-level reliability is highlighted as a critical path to an optimal design for cost-driven and/or performance-driven devices.

Introduction The key factors driving semiconductor integrated circuit

(IC) package development for today’s demanding electronics markets are cost, size, electrical performance and reliability.

In many high-speed applications and high-end processors that require logic and memory devices stable and clean signal outputs are necessary. This requirement becomes increasingly difficult to achieve at higher clock speeds due to the inherent electrical parasitic effects in IC packages. This is because both package and board designs are significant factors in noise generation.

Thus, it is necessary to minimize package and board parasitics early in the system design cycle for fast clock speed, high bandwidth applications. However, new IC package designs are often notoriously expensive to implement and often result in signifcant changes to the manufacturing infrastructure that adds to manufacturing cost.

One way to introduce new packaging technologies without increasing the manufacturing burden is to leverage existing processes and infrastructure to create novel packaging solutions. This approach has the benefit of integrating state- of-the-art packaging techniques. where the underlying technologies are well understood, to achieve lower cost and/or higher performance targets.

State-Of-Tbe-Art Packaging Technologies Thin Film Re-dishibufion & Wafer-Level Packaging. To

date, most ICs are still designed with peripheral bond pads with notable exceptions in advanced microprocessors and some system-on-chip (SOC) designs that have bond pads over the die and dynamic random access memories (DRAM) with bond pads in a central row on the die.

The peripheral pad pitch is typically 150-pm and is decreasing to 60-pm due to the increasing number of WOs. While automated wire bonders can handle this pitch, the high- density boards required to directly connect solder balls with this pitch are far too expensive for commodity products. Therefore, pad redistribution is often required in order to meet the high-density interconnect (HDI) substrate manufacturing capability for reasonable assembly yield.

Wafer-level pad re-distribution schemes provide higher routing density than re-distribution schemes on interposer substrates because they utilize front-end wafer processing environments, equipment and processes. These re-distribution layers and their associated solder balls for later second-level interconnect are typically fabricated while the die are still in wafer form: hence the name wafer-level packaging (WLP).

However, WLP requires “fan-in” routing as opposed to “fan-out” routing as the edge of the die itself defines the boundary of the package. Therefore, the only way for WLP to meet the need for higher number of WOs with “fan-in” routing is to reduce the solder ball pitch of the fmal package. Such pitch reductions must be compatible with current surface mount technology (SMT) assembly capability for reasonable production yield.

Current SMT-compatible pitches for grid-array packages have come down from 0.8 mm to 0.5 mm along with the emergence of a 0.4 mm pitch. However, for practical reasons, it is not always possible to miniaturize the connection scheme concurrently with die-level and board level improvements.

In addition, most pad re-distribution approaches use thin- film dielectrics materials, polyimide or benzocyclobutene (BCB) layers followed by vacuum sputtering and semi- additive plating to build the traces for re-routing. Since the plating bus is vacuum deposited and photolithography is processed at the wafer-level, it is difficult to lower manufacturing cost effectively.

Therefore, the lack of “fan-out” routing capability, design cycle mismatch between die and board and the need for process steps not common to packaging industry are some of the obstacles for wider adoption of WLP. As a result, only a handful of devices (e.g. low WO count devices) are able to take full advantage of WLP technology.

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Flip Chip Technolop. A major advantage of flip-chip packages is that it provides shorter connection paths between the chip and the external circuitry.

With careful design, the IC package often demonstrates better electrical characteristics such as less inductive noise; signal cross talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and mass increase which results in a smaller packaging footprint and a lighter package.

While flipchip technology has tremendous advantages, its cost and technical limitations are not insignificant. For instance, there is the manufacturing cost to fabricate the solder humps on the chip. Additional adhesive material is normally under-filled between the die and substrate to reduce stress on these solder joints.

Finally, the solder is typically a eutectic tin-lead alloy and lead-based materials are becoming less popular due to environmental concems in many countries.

Board Level Reliability. Board level reliability is an important issue for tin-lead based solder on grid array packages. For solder alloys, thermal fatigue failure frequently results in cracked solder joints. In high temperature regimes, a significant amount of creep and creepinduced fracture can also occur.

Since the thermal fatigue of solder joints is strongly affected by a number of parameters such as package configuration, manufacturing, material composition and interfaces, modifying some of these parameters may significantly improve hoard level reliability.

The use of polymer stud bumps to increase board level reliability is one recent example developed jointly by IMEC and Siemens (now “eon). The polymer stud grid array (PSGA) package is lead-free by construction and features excellent hoard-level reliability. The substrate body is realized by injection molding and includes a die cavity and studs that replace the solder balls.

Similarly, bumped chip carrier (BCC) packages developed and introduced by Fujitsu feature similar resin bumps at the bottom of the package. The BCC has a lead-less, transfer molded body with terminals protruding from the hottom that are connected to the die pads by wire bonding. The molding compound encapsulates the chip and supports the terminals that serve as interconnects from the package to the PCB.

The reliability of the BCC solder joints has been evaluated with thermal cyclmg conditions between -65 OC and 150 ‘C and no degradation in solder joint strength was observed during these tests. According to Fujitsu, this package has the electrical performance and reliability equivalent to or better than those of leaded packages.

Thus, the use of compliant bumps represents the state-of- the-art approach to relieve package-board stress while maintaining compatibility with volume SMT assembly. In particular, Fujitsu’s BCC packages have reportedly entered early production for certain flash memory devices.

Novel Bumpless Flip Chip Package Bridge Semiconductor has patented a portfolio of

interconnect technologies and has developed several

innovative IC package designs aimed at delivering a variety of IC packaging solutions.

Unlike most new IC packaging designs, the solutions are built on conventional PCB and lead-frame manufacturing and IC package hack-end assembly processes, equipment, materials, parts and services.

While the bumpless flip chip IC package is targeted primarily for low-cost applications, its basic design and fabrication steps can be extended and optimized to achieve high-performance, high-density and high VO requirements. This is because the same basic manufacturing process steps can be used as “huildmg blocks’’ to produce single-chip packages, stacked or three-dimensional (3D) packages, multi- chip packages and application-specific packages for radio- frequency (RF) or optc-electronic (OE) devices. Thus, the bumpless flip chip package enables cost-effective and size- effective IC packaging and provide packaging engineers the ability to quickly achieve cost-performance targets and speed time-to-market.

The unique features and characteristics of the bumpless flip chip package are summarized as follows:

A truly bumpless, substrate-free, wire-bond-free IC package with total design flexibility and extendibility.

An IC package with leading-edge wafer level processing (WLP) benefits without its limitations.

A capability to produce most IC packages (e.g. SOP, QFP, BGA, CSP, stacked or multi-chip) with the same low- cost starting material and basic manufacturing process steps.

An existing and readily available manufacturing infrastructure for prototyping and leveraged for future volume production.

A design for manufacturing approach to ensure that f ~ s h e d IC packages meet cost-effective and size-effective targets and are fully compatible with existing back-end SMT assembly and test processes.

Key Concepts For Bumpless Flip Chip Package Thin Film Re-dishibufion. A more economical way of

fabricating re-distribution fme line traces is to avoid expensive vacuum processes altogether. In other words, the thin film process can be simplied horn sputtering-plating- etching steps to plating-etching steps if a plating bus already exists.

This can be easily achieved by using a copper panel as the starting carrier material as it is electrically conductive. Such copper panels are widely used in conventional PCB and lead- frame manufacturing processes.

In lead-frame manufacturing, copper is stamped or patterned-etched to form the leads. However, it is impractical to achieve ultra-fme Circuitry compatible with the normal die bond pad pitch with etching processes due to the thickness of the copper used (0.125 mm to 0.2 mm). This is because wet chemical etching of the copper is inherently isotropic. Wire bonding is therefore needed to bridge the bond pads and the metal leads.

On the other hand, an additive processes such as electrochemical plating on the copper plate can achieve fme- lme circuit traces down to 50-pm lmelspace resolution.

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Achieving this degree of resolution during photolithography is already common practice for most lead- frame makers. More advanced lead-frame makers can achieve fie-line resolution in the range of 25-pm or less.

The bumpless flip chip package utilizes this electrochemical plating approach on copper panels to allow f i e line re-distribution circuit traces to be patterned and brought closer to the bond pads of the chip than ever before. In addition, this method is intrinsically low-cost and is highly scalable for volume production. Figure 1 shows the fine lime NdCu traces plated on the copper carrier with 50-pm minimal linehpace design rule.

Figure 1: Fme line NUCu traces on copper carrier

Flip Chip Attachment. In conventional flip chip technology, solder bumped die (chip) are flipped over and attached to an interposer substrate patterned with the re- distribution circuitry and re-flowed to complete the connection. For reliable connections, the dimensional stability of the interposer substrate is critical. In the bumpless flip chip package, electroplated copper re-distribution (or re-routing) traces (see above) are fabricated on the thick copper plate (substrate) because the latter provides excellent dimensional stability due to its homogeneous characteristics. Electroplating 15-pm of copper with 50-pm linelspace circuit densities onto a 150-pm thick copper experiences almost no global as well as local deformation. Excellent placement accuracy can subsequently be achieved with flip chip attachment of dies to this rigid, homogeneous substrate using conventional non-conductive die attach adhesives. This is because there are no solder bumps and no self-aligning effects in this process and the chip needs to stay exactly where it is placed. Advanced vision systems are used to ensure the accuracy of die placement. Figure 2 shows the proximity of the trace to the die pad that can be achieved.

Figure 2: Fine line NdCu traces at close proximity to pads.

Once the chip is attached to the nickelkopper re-routing pattern on the copper plate, the entire chip and any re-routing circuit traces that "fan out" !?om the chip are protected with molding compound via a conventional transfer molding process. This is followed by the selective removal of bulk copper from the opposite side of the substrate by choosing an etching solution that differentiates copper from nickel (e.g. an ammonia system) such that the fine line circuitry with a nickel overcoat will remain un-etched while the bulk copper is completely removed. The re-routing circuit traces that are mechanically coupled to chip are thus exposed and precisely aligned with respect to their corresponding bond pads. For packages with fan-out circuitry, the protective molding compound provides the critical mechanical support and protection during the etching process.

At this stage, the re-routing circuitry is transferred to the chip surface but not electrically connected yet as a thin-layer of non-conducting die-attach adhesive still separates them. In short, this unique use of flip chip technology transforms the role of flip-chip attachment fiom a simple die placement tool to an enabliig technology which brings the physical gap between f i e line traces and bond pads from 1 . 0 " or more (wire bonding) to less than a few microns (the thickness of the die attach adhesive). Figure 3 shows the 50-pm copper traces precisely aligned to the pads after copper base removal.

Figure 3: Exposed fine line NdCu traces aligned to pads.

Novel First Level Interconnects. Electrochemically plated interconnect is a very low-cost yet highly reliable connection method. In most conventional flip chip BGA bonding approaches, f i e pitch solder bumps are typically electroplated before they are re-flowed to connect them to the interposer substrate.

Instead of using solder bumps, the humpless flip chip package uses an electrochemical plating process to complete the f i s t level interconnect. This method builds on the fact that the fme-line circuitry has been precisely placed in close proximity to the bonding pads of the die (see Figure 2 above) such that a conventional blind via metallization process may be used to make the plating joint.

The f is t step is to create a via between each trace and its corresponding bond pad so that the latter can be accessed. This is achieved by laser drilling to selectively ablate away the resin (cured adhesive) layer that separates them.

Figure 4 below shows a series of vias opened by laser drilling to allow access to the die pad to create the electroplating joint between the trace and the pad.

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Figure 4: Vias opened to expose die pads.

Now that the material on each of the bond pads is exposed, it is ready to be plated on. Using the electrochemical plating process, the conductive trace over each pad is electrically connected and when submerged in the plating solution, the trace will selectively grow in the via and make contact with the bond pad. Once the growing trace touches the bond pad, it will initiate the electrochemical plating process on the latter and both trace and pad will grow at the same time. The plated material will eventually serve as the intrinsic conductive material between bond pad and trace without the need for wire-bonds or solder re-flow.

From the processing viewpoint, this is much like the electrolytic bumping process except that in this case, the plating bus is pre-formed and used to selectively deliver current to the designated locations over the bond pads. Furthermore, as solder re-flow is not needed to complete the connection, a wide selection of materials and alloys that can be electrochemically plated can be applied. Therefore, a robust and permanent connection between bond pad and conductive trace can be achieved at ambient (room) temperahue.

Similarly, if the connecting material is designed to extend from both bond pad and trace sides, the same phenomenon described above will occur. This can be achieved by using electro-less nickel-plating with the bond pads chemically activated before the reaction can he initiated. For example, aluminum bond pad surfaces are typically activated with zincate solution. This process approach is similar to electro- less nickel deposition for under-bump metallization (UBM) except that in this case, the plated electro-less nickel serves as the intrinsic conductive material between bond pad and conductive trace as well.

Several other methods can be used to form the fust level interconnect joints so long as the re-routing trace is placed in close proximity to the corresponding pad. These methods may include direct liquid solder dispensing, solder paste printing, conductive adhesive bonding and ball bonding; each applied depending on the fmal applications. The shape and material composition of the joint depends on overall design and reliability considerations.

With this novel approach, the connection mode for fust level interconnects shifts from mechanical coupling to metallurgical coupling to ensure sufficient metallurgical bond strength. Furthermore, as the conductive traces are mechanically coupled to the chip surface without wire bonding, TAB, flip-chip bonding, polishing, or solder joints,

packaged die field reliability is expected to increase. Figure 5 shows a completed trace to pad interconnect by electroplating process.

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Figure 5 : Trace to pad interconnect.

Novel Second Level Interconnects. To address board-level reliability issiies in the bumpless flip chip package, we extend the compliant terminal concepts discussed earlier directly into the design of the IC package terminals.

In the bumpless flip chip package, these terminals are specially designed to form part of the thin film routing circuitry plated directly on the copper panel. To achieve this, we have designed the electroplated conductive trace to include a hinnped terminal that was originally a recess (dimple) in the copper plate. This method requires forming an anay of recesses in the copper base by etching or drilling them fwst, followed by electroplating the conductive traces onto the copper panel such that each conductive trace includes the bumped terminal in the recess as well as the routing l i e that m s outside the recess to the die pad. Each conductive trace thus becomes a single continuous low-profile metal segment from the bond pad end to the package terminal end. After flip chip die attach and encapsulation, the resin (cured die attach adhesive or mold compound) that intentionally fills each recess becomes part of the resin-filled bump when copper substrate is removed by etching. The elastic properties of the resin permits each humped terminal to provide a compressible compliant contact terminal thereby ensuing excellent hoard level reliability.

An advantage of this method for producing compliant terminals is that the process has very low manufacturing costs and need not include complicated precious metal plating and wire bonding steps. Figure 6 below shows a completed resin- filled compliant terminal for package stress relief and increased board-level reliability.

Figure 6: Resin-filled compliant terminal.

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Fabrication Process The process steps for different bumpless flip chip

packages are similar whether the die has die pads on the periphery, in a central row (e.g. SDRAM) or anywhere on the die (e.g. certain SOC). The same basic mannfacturing process will accommodate these differences as well as die-shrink as chip technology improves. This ensures a reasonable level of package latency for efficient back-end SMT assembly operations.

Figure 7 below illustrates a cross-section view of the finished bumpless flip chip package. Figure 8 that follows illustrates the various process steps in the fabrication of a bumpless flip chip package in a generalized process flow. In this case, we illustrate the process for SDRAM memory packages with die pads located in the center.

The general process steps to fabricate bumpless flip chip packages are as follows:

Die pads, terminal locations and fme line trace pattern are defmed with system and chip designers.

A series of recesses or dimples corresponding to the terminal locations are formed by half-etching in a copper panel along with tooling holes to handle the panel.

Poweriground lines and signal traces are formed by resist patterning and electroplating process.

Die attach adhesive is precisely dispensed to ensure complete filling of recesses in the copper carrier.

Bare dies are flip chip bonded onto the copper frame using an image scan to align the traces and the die pads.

The composite smcture of chips and frame is cured under heat and encapsulated with mold compound using transfer molding.

A wet chemical etching process removes the copper frame under each chip. The trace material acts as an etch stop and a series of raised bumps is revealed.

Via holes are then drilled by laser over the chip pad positions. Any polymer debris and residual film can be removed by plasma etch. Via hole taper can be adjusted by varying the laser scan condition and can be formed with high reliability and continuity in the via hole.

Electroplating to form the connection joints between each trace and chip pad. Electroplating is precisely controlled by design such that the traces do not grow laterally and violate lineispace design rules hut make excellent contact with each chip pad.

The package is sealed with a fmal layer of epoxy leaving the tops of each bumped terminal exposed for board level contact and singulated.

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Figure 7: Cross-section of bumpless flip chip package.

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Etch Dimples In Capper Carrier For Contact TBrmtPB

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N w L P - - w V i r .-

Prim Adheslre. Fill Dimpies 8 Attach Flipped Chip

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Via Open10 Expose Die Pads

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Chip Encapwlmion 4 Final Encapwlatiw 6 Sinoulation

Figure 8: Generalized Process Flow

Considerations For CostlPerformance Devices Lower Package Cost. The humpless flip chip package

presented here can dramatically drive the cost of packaging advanced IC devices from current levels to near-commodity levels and simultaneously address the need for higher performance and/or higher density packages.

First, the need for expensive wafer bumping, fme-pitch wire-bonding steps and expensive high-density interposer substrates has been eliminated. Second, the use of a low-cost starting material such as copper and a simplied manufacturing process lowers costs and increases throughput.

To illustrate the cost advantage of the bumpless flip chip package in volume production, consider that each copper panel can be designed to accommodate several packaging molds. The number of packages that can be singnlated from each mold depends on geometric constraints such as number of UO, terminal pitch and package height. Figure 9 shows a sample copper panel with 12 BGA-format packages within each of the 5 molds.

Figure 9: Copper strip utilization example.

Clearly, the higher the number of packages derived from a given copper panel area. the lower the cost per package. In addition, the smaller the pitch between bumped terminals the lower the cost per U 0 in each package. In practice, a combination of optimization techniques for copper strip utilization, batch processing to increase throughput and

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stream-liniig of back-end assembly processes can he concurrently used to achieve high IC packaging production yields. This results in a lower bill-of-material (BOM) and package assembly costs are expected to decrease with increasing volume.

Improved Package Performance. The reduced inductance and capacitance of this novel bumpless flip chip package is expected to be similar to those in wafer-level packages. Improved noise characteristics enable bigber system-level performance. In addition, thermal impedance and board-level reliability can also be improved. Costs savings in terms of both board real estate and actual component cost may contribute significantly to system-level savings. In terms of thermal performance, the molding can be replaced with a beat sink situated directly on top of each the chip in the package to facilitate escient heat dissipation for h i g h 4 0 devices.

Smaller Package Size & Height The elimination of interposer substrates and wire-bonds in the novel bumpless flip chip package allows smaller package footprints to be achieved. More importantly, it significantly reduces package height and allows ultra-thin packages such as sub-0.5mm high packages to be produced.

Design For Manufacturing. The desired cost and performance benefits of bumpless flip chip packages are hest achieved when the IC package design is entered into early in the development cycle with die-level andlor system-level design teams focusing on design for manufacturing methods.

Through the exchange of electrical, mechanical and material-related information, various IC package designs may be explored and fabricated based on a set of package design rules that cover the geometxy of the chip, the circuit layout and the package ontlme specifications to achieve an optimized bumpless flip chip package design that balances cost and performance with package and board-level reliability.

The package design rules are themselves derived from the underlying capabilities and process parameters of PCB and lead-frame manufacturers and outsourced package assembly service providers and is updated as such technologies improve. This ensures that scalability for volume manufacturing is always available as an option.

Thus, with this approach, designers of cost/petformance driven devices may bridge time-to-market, technology and cost-effectiveness gaps more effectively.

Conclusions The novel bumpless flip chip package presented here

represents a bold step forward to deliver a robust, flexible, low-cost and simplified way to manufacture different IC packages. Combined with a design for manufacturing approach in which performance and cost trade offs are made concurrently with die-level and/or system-level design teams, we believe that the bumpless flip chip package presented here can deliver cost-effective and size-effective solutions for costlperfonnance driven devices for the long term.

559 2003 Electronic Components and Technology Conference