EFFICIENT SCAN-PATH AND BIST LATCHES FOR STATIC CMOS ASIC CIRCUITS

Shridhar K. Mukund*, Suchai Thanawastien and T. R. N. Rao

Center for Advanced Computer Studies University of Southwestern Louisiana

P. 0. Box 44330 Lafayette,

This paper presents a scan-path and BIST(Bui1t-in Self Test) implementation scheme evolved to reduce the cost of incorporating testability in a CMOS ASIC( Application Specific Integrsted Circuit) environment. Minimal penalty on circuit performance, low area overhead and ease to design are the main goals, achieved by taking into account CMOS semicustom design specific conditions. Scan-path and BIST latches are designed in a way as to have minimal impact on normal latch performance. Design independence is achieved by using an independent clock for testing, while area overhead is reduced by careful use of MOS gates and dynamic latching stages to incorporate testability in an otherwise fully static and complementary CMOS environment.

Introduction

This work addresses to the salient requirements of the medium/low investment ASIC vendors in providing state-of- art in VLSI to semicustom and user designers. Since the intention underlying semicustom design is to achieve low-volume manufacture of a great variety of circuits in a very short turn- around time, the factors of high cost and test preparation time are becoming more critical, as compared with universal chips produ'zed in large quantities. Since 35% of the production cost of ASIC chips is due to testing[b], it is essential to greatly improve the testability of semicustom design in order to curb the cost of test preparation, even if the chip area becomes somewhat larger.

While DFT techniques for combinatorial circuits and struc- tured :sub-circuits are well studied, testing for random sequential logic is less understood. Serial test techniques like scan-path, BIST and others based on linear feedback shift registers(LFSR) offer ;a circuit independent solution. These techniques are becoming popular, especially in view of the recently proposed IEEE testability bus[5]. Although the silicon area overhead has to be minimized, it is not a major concern considering the task on hand. The performance overhead has to be within a fair margin, to make such a scheme attractive. In an ASIC environment, with relatively naive designers, the technique must not pose many design constraints. As far as possible it should not affect the circuits logic and timing, thereby making testability-incorporation independent of the circuit design process.

In the following section, we develop our notions of efficient cell library environment. This discussion is aimed at providing a perspective for further discussions. In the subsequent section, we discuss our approach to incorporation of testability in the said environment. In the final section we discuss the design of the reconfigurable bistables. * On study leave from the Center for Development of Telematics, Bangalore, India.

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Approach to Cell library design

\V,? attempted to create a cell library to meet the goals of semicustom design environment, mentioned earlier. Following are the notions on which the cell library design is based.

Technology : CMOS technology is a popular choice in the ASIC area. Lower power consumption, higher density, better noise margin etc., are among the other advantages. CMOS also lends itself KO scaling, making technology migration easier. Among the variations available in CMOS, stat ic fully-complementary CMOS is most easy to work with. Although it has speed and density disadvantages compared to other CMOS styles, aspects such as better noise margin, lesser design constraints etc., easily override, at least in the ASIC environment.

-~ Standard cell : Increased demands in quality and performance are making way for standard cell approach. While standard cell approach is used in general, intermix of PLA4 and gate arrays is allowed to accommodate already existing modules and exceptions.

Reduced-set library : Considering the fact that in most ap- plications only 20% of the cells are used 80% of the times, an efficiently designed reduced-set standard cell library can reducr the costs of library maintenance, cell characterization and te,chnology migration, with minimal penalty on functional density, performance and design flexibility[3]. In a reduced-set cell litirary approach, all cells are built over a very small set of efficiently hand-packed, most-often-used primitives. The typical set includes inverters, NAND, NOR, multiplexer, transmission gate, latches, flip flops, adder and a few other cells. Most other cells can be built as macros over the primitive cells.

Cell structure and layout considerations : We expect our ap- proach to be effective for a wide range of applications, where the demand for performance and shorter turnaround time has to be met even in an environment of lower expertise. Accordingly our layout and routing mechanism had to be suitable for hand layout by naive designers, at the same time suitable for automation.

All cells are of standard height. The standard height depended upon how well complex cells such as latches and adder could be compressed in height. The cells were constructed over grids whose pitch depended upon how close vias could be placed at every grid point. Power is routed in metal 1 at the top and bottom of the cell. Metal 2 routing takes off vertically from the vias on the cell. The most interesting feature of the cells are the metal l/poly butting contacts on either sides of the cell[3]. Terminal contacts are brought out in such a way that most often used macros and data-path can be constructed without any metal 2 connections. The cells have vertical transparency

CH2819-1/90/oooo-0576$01.0001991 EEE

for metal 2 along those grids where there are no vias. The cells are designed so that tiling of two cells does not violate any of the design rules. This takes away a major burden off the design-rule- checker. It also absorbs all the technology dependent details, thereby making it highly suitable for technology migration.

Simulation abstraction : In the reduced-set approach, only the primitive cells need to be characterized in detail, and the simula.tion abstraction of the cell can be used for higher level simuhtions. This, of course assumes that the inputs/outputs can be accurately characterized in the presence of external connections. Due to the use of instances of a very small number of wel! characterized cells, the overall simulation is expected to be bester.

Fault-model abstraction : The small number of cells are care- fully laid out such that the probability of occurrence of peculiar faults that cannot be modelled as stuck-ut f u u h are reduced. In the standard cell approach this could be achieved with very minimal area overhead by making use of the otherwise unused silicon. Hence, stuck-at fault model can be more effectively applied against realistic faults.

Testability incorporation

While the need for DFT is well established, automating DFT in an ASIC environment is also a must because,

1. ASIC designers may not have sufficient training in DFT to design testable IC’s.

2. ASIC circuits tend to adopt varying styles, making it diilicult for any particular test strategy to be used. Often a combination of various techniques is required to optimize the testability effort.

Intricate relationships between the choice of testability and circuit design/performance has been the primary cause for the need of complex automatic DFT systems. Building complex automatic DFT software is impractical for ASIC vendors with limited research capabilities. So a concept of testab-lity-by-construction was suggested, where in the cells are designed in such a way that the resulting circuit is automatically testable[l,2]. In line with this, we have adopted a similar strategy. A blend of techniques like scan-path, BIST etc. are adopted. In all these techniques the problem of testability incorporation reduces to that of reconfiguring the circuit bistables, i.e. latches/flip flops.

Synchronous design

Asynchronous bistables are not suitable for structured designs. Among the synchronous(c1ocked) bistables, the D-type is most suitable for such techniques and is popular too. In fact, all other types can be built over the D-type elements. SILC silicon compiler(l1, the DFT-CMOS cell library at Stanford[2] and the reduced-set CMOS cell library at BNR[3] indicate the use of only the D-type elements. Since the need to take care of nasty spikes and other timing problems conflicts with the semicustom design philosophy, we rely on strictly synchronous design method using D-type bistables.

Impleinentat ion

The only types of basic bistables provided are the D-latch and the D-flip flop. To recall, a latch has one feedback loop and is level sensitive. A flip flop is made of two latches in series, with one clocked by the complement of the other’s clock, thereby making it edge sensitive. The D-latch forms the primitive cell and the D-flip flop is obtained by butting a flip flop extension as shown in the following figure. A test D-latch/test D-flip flop is obt;lined by appending a test extension to the D-latch/D-flip flop. The test extension may have either scan-path or BIST capability.

D-LATCH - - TEST D-LATCH * t

D-FLIP FLOP 4 t

4 t TEST D-FLIP FLOP

1 F L I P P 1 D-LATCH 1 1 Fig. 1 Modularity in layout

The figure below depicts the function of the scan-path and the BIST bistables. The data at D is latched and is available at Q when CLK is pulsed. The data at Q is also available at S C l N OUT(actual1y inverted in our implementation). The data at SCAN IN is latched when TEST CLK is pulsed. Pseudo-random pattern generators, signature registers and other circuits required for BIST can be efficiently built using modified scan-path bistable to include an X-OR gate[9], as shown.

-ATEST CLK I Fig. 2 Scan-path and BIST bistables

so

+TEST CLK I

Circuit design is done independent of testability, as the latches/flip flops have the same user abstraction whether or not they have test capabilities. In a post process, those bistables that need to have scan-path/BIST capability are identified and the layout is done appropriately. The routing of the signals related to testability is also done separately in a straight forward manner as shown in the following figure.

SCAN-PATH BISTABLES

TEST CLK SCAN

t

b

Fig. 3 Additional wiring

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Tlie test clock is broadcast and the scan chaiii is directcd along the channel. As the distance between any two intercom nected bistables is small, there are no hazards due to clock skew. Furtlicr, routing of scan chain is done through liiit,t,ing cont,acts when ;he bistables are laid next to each other. SOII~C of the extra signal:; associated with BIST are routed in a similar fashion.

Design of the bistables

As implied earlier the bottom line of tlic testahi1it)y prohlcni is in the design of cost effective latches/flip flops wit11 tcst features.

Scaii-l)ath bist ables

The primary step in making a circuit testable using scan path lor BIST technique is to modify cvcry bistablc(D-type) such that in the test mode, they arc rcconfigurcti into a long chain of shift registers.

Tlie D-type bistable[ll] used is as shown in the figlire below. A particular combination of sub-circuits makes a latch, a flip flop. 6 scan-path latch or a scan-path flip flop.

D-LATCH *-.

D-FLIP FLOP c

SCAN D-LATCH SCAN D-FLIP FLOP

t

b Q ( b u f f c r e d ) 6

Q*(normal)

RESET* SCAN OUT SYSTEM TEST MASTER MASTER SLAVE

Fig. 4 Scan-path latch/flip flop circuit

This is basically a two-port flip flop. Tlic data latched is either the normal data D or tlie test data SCAN IN depending on which of the two clocks is pulsed. The circuit is constructd using three latches as shown. The system mast,c:r and tlie slave latchej are static and complementary, while the tcst niaster is dynamic and uses pass-transistors. The syst,em master and the slave latches form the popularly used traiisiiiission-gnte type resettable flip flop. The clocks CLIT and CLK* could bc two-phase non-overlapping or derived locally by inverting CLIT.

Addition of the test master latch to a normal flip flop conveits it into a scan-path flip flop, functionally. With the test clock and RESET high, the circuit acts like a system flip flop, latching the input data D to Q on the low going edge of CLK. With the CLK and RESET high, the circuit acts like a scan-path flip flop, latching SCAN IN to SCAN OUT on the low going edge of the TEST CLK. Notice that SCAN OUT and Q are inverts of each other. This is equivalent to scanning out Q*.

In the test mode, the flip flops form such an orderly chain of shift-registers that it is easy to take care of the adverse effects of using pass-transistors and the dynamic latch. The test clock being independent, it is easy to ensure that the low period is small enough for reliable operation of the dynamic latch, while the high period is large enough to allow for the worst case propagation delays through the conibinatorial logic. The degradation of noise margin within the slave latch due to the pass-transistor is not critical, as it is contained xell within the cell. The reduction of noise margins within the test master chic tcs the pass-transistors results only in a marginal reduction in the test speed.

Tliere is no performance degradation at Q; since the testability circuit does not affect the critical path between D a n d Q. There is an additional delay at Q*. Buffered versions. obtained by butting normal or buffer inverter cells as shawl, have 110 performance degradation. Weak Q* can be used as an input to an adjacent gate, without any significant loading. High clrims are rarely required, hence the basic cell is designed to achieve maximum functional density.

Scan D-latch is realized by simply removing the system master portion of the circuit. A D-flip flop is realized by removing the test master portion of the circuit, and by further removing the system master, a D-latch is obtained.

B E T latch/flip flop circuit

Tlie figure below shows the implementation of the BIST bistable.

BIST D-LATCH BIST D-FLIP FLOP

q:pm CLK CLK* 4 b K ' I Q (normal) E S T 1 - CLK

-

4 SCAN IN

MODE v SCANIX-OWEST DATA LATCH

Fig. 5 BIST latch/flip flop circuit

In the normal MODE, it behaves like a scan-path elenient, aiid in the B E T mode, it shifts out the X-OR of D and SC-4Y IN. Tlie BIST flip flop is obtained by modifying only the test latch portion to include an X-OR gate. When MODE is high. it behaves like a scan-path latch else like a BIST element.

It is very interesting to note that the normal circuit performance is not degraded, since the depletion mode transistor in the mode selection arrangement remains off. The point D in the critical path does not get loaded.

This circuit can also be converted to D-type BIST latch bp stripping off the system latch.

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Coniparisons

A lot of circuits with scan-path feature have been proposed ;riid u:xd earlier. Some of the more efficient ones among them, t,liilt, arc applicable in comparable situations are discussed. In g c ~ i c ~ ; 1 there are three drawbacks of making a testa,ble bistable :

1. Pcrformaiicc degradation 2. R(diicct1 design flexibility 3. A 1 . c ~ ovcrhead

1. Stanford MD-flip flop : [2] discusses the Stanford MD-flip flol) (inult,iplcrrer type). A part of this flip flop is the MD-latch. 111 t,liis implementation, a multiplexer is introduced at the input so t,li;rt rither the system data D or the test data SCAN IN can I ) ( - sc,l,Tct,cd, based on a TEST MODE signal. Weak inverters :ire iiscxtl for the feedback loops.

1ii;rotluction of the multiplexer at the input introduces delay i l l i,hc critical path. Further, weak inverter implementation of thc, feedback loops have inherent delays due to output collision. The outputs of the weak inverters cannot be used wit,lioiit liuffering. One major constraint is that the clocks iiscd for both the system and testing are same. Hence there is n s(’vcre reduction in the design independence. The area o v d i w ( 1 is only to the extent of the input multiplexers. In ilct,ilitl iiiil)lCiii(!iit,ations the weak inverters take up large space.

2. Two-port flip flop : [2] discusses the construction of a two- I)ort, flip flop. A part of this flip flop is a two-port latch. In t,liis circuit an additional test port controlled by the test clock is adtl(:d to the weak inverter based bistable.

Ail additional delay is introduced in the critical path to ;icconiiuodatc dual clocking. Due to independent clocking, the only ticsign constraint introduced is that the system clock be iiiactivc during testing. There is a substantial increase in the iiiinilx~r of circuit components in the flip flop implementations. Tliv umrheads in the latch-based designs are smaller though.

3. Bliwsar’s latch : [lo] discusses an interesting circuit of D- liitcli. In tliis implementation a static latch is converted into a dyiiiiniic flip flop when testing, by opening up the feedback loop.

Wlirii used in the form of a system latch, there is no l)ciformance degradation at Q. It’s major drawback is that tlie circuit has to meet contradicting requirements. The test clock l ins to be fast enough to ensure reliable operation of the tlynniiiic latches but slow enough to accommodate the delays in the combinatorial logic. This is tough to meet in general. Fiii tlii.1, the clocking scheme is very complex, and hence not flcsihlc. The area overhead is by far the least. Multiple clocking may t alte up significant routing area.

4. Iiitcgrated CMOS Systems flip flop : The design indicated iii [5] has by far the least performance overhead. An additional fill1 la.:cli is introduced to make a flip flop scan testab1.e.

Tlic circuit does not degrade the performance since the tcstnlility circuit is not in the critical path. Use of independent clocltiiig improves design flexibility. The circuit overhead is very liigli due to the full implementation of an additional latch.

the design independence, also allowing both single phase clock- ing and two phase clocking. The area overhead is far too less. Clock routing is lesser since only one clock is routed.

In Conclusion

In this paper, we developed a scenario conducive to efficient design of semicustom ASIC’s. The choice of static CMOS, standard cell approach and the reduced-set cell library greatly helps in meeting the goal of low-volume manufacture of a great variety of circuits in a short turn-around time, even in an environment of lesser expertise. Considering the multifarious applications and design styles, structured DFT techniques namely, scan-path and BIST are aptly suited for ASIC products. Malting the process of testability incorporation less dependent on circuit design as discussed, greatly reduces the burden off the ASIC designers and introduces a scope for easy automation of DFT. The design of reconfigurable latches and flip flops discussed, have by far the least overall cost overhead of providing testability in the semicustom environment.

Acknowledgements

The authors would like to acknowledge the contribution made by Dr. R. Venkatesan and Prof. M. Bruce-Lockhart in the initial developments. This work was supported in part by the LaSER grant of the Board of Regents, State of Louisiana.

References

H. S. Fung and Hirschhorn, ‘An Automatic DFT System for SILC Silicon Compiler, ’ IEEE Design and Test, Feb 1986. Dick L. Liu and E. J . McCluskey, ‘ A CMOS Cell Library Design for Testability, ’ VLSI Systems Design, May 1987. Stephen Sunter, ‘ Designing a CMOS Standard Cell Library, ’ IEEE CICC, 1987. Ralph D. Kilmoyer, David J. Hathaway and Albert M. Chu, ‘ A reduced circuit library design system, ’ IEEE CICC, 1988. P1149/D5 IEEE Standard Testability Bus Specifica- tion - a draft, May, 1988. Steven S. Leung, P.David Fisher and Michael A. Shan- blatt, ‘ A Conceptual Framework for ASIC Design, ’ Proc. of the IEEE, July 1988. F. Joel Ferguson and John P. Shen, ‘ A CMOS Fault Extractor for Inductive Fault Analysis, ’ IEEE Transactions on CAD, Nov 1988. Dervisoglu I. Bulent, ‘ Using Scan Technology for Debug and Diagnostics in a Workstation Environment, ’ IEEE International Test Conference, 1988. Liu L. Dick and Edward J. McCluskey, ‘ High Fault Coverage Self-Test Structures for CMOS ICs, ’IEEE CICC, 1987. Bhavsar K. Dilip, ‘ A New Economical Implementation for Scannable Flip-Flops in MOS., ’IEEE Design & Test, June 1986. Shridhar M. K., Venkatesan R., and Bruce-Lockhart M., ‘ A novel Design of Scan Testable Sequential Cell, ’ IEEE VLSI Test Workshop, Atlantic City, 1989.

Thr new circuit : There is no degradation in performance. T h e is an independent clock for testing. The circuit enhances

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