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Characterization of Vertical Strained SiGe Impact Ionization MOSFET for Ultra-Sensitive Biosensor

Application

Ismail Saad, Mohd. Zuhir H., Bun Seng C., Khairul A.M, Bablu Ghosh, N. Bolong

Nano Engineering & Material (NEMs) Research Group, Faculty of Engineering, Universiti Malaysia Sabah,

88999, Kota Kinabalu, Sabah, Malaysia. ismail_s@ums.edu.my

Razali Ismail Computational Nanoelectronics (CONE) Research Group,

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310, Skudai, Johor, Malaysia.

zuhirhamzah@yahoo.com

Abstract—This paper venture into prospective ideas of finding viable solution of nanoelectronics device design by an assessment of incorporating vertical impact-ionization MOSFET (IMOS) with strained SiGe technology into a formation of an emerging device structure with elevated performance and reliable outcomes for future bio-based sensor application. Impact Ionization FET biosensors can be extremely promising for applications where ultra-high sensitivity and fast response is desirable. An ultra-low power with low Subthreshold Swing and high breakdown voltage are imperative for ultra-sensitive biosensor. Impact ionization MOSFET (IMOS) is expected to have a subthreshold swing (S) down to 20 mV/dec which is much lower compared to Conventional MOSFET (CMOS). This will eventually enhanced the switching behavior of the transistor and enhancing its electrical performance and response time particularly when scaled down into nanometre regime. However, vertical IMOS experience parasitic bipolar transistors (PBT) effect and low breakdown voltage. Parasitic Bipolar Transistor effect is a phenomenon where the MOSFET act as a minority carrier device like BJT instead of majority carrier device. This is not favorable for any power device or sensor. Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the performance of the device. Eventually, this device will prolong the increase density of transistor in a chip for future application of biosensor nanoelectronics.

Keywords—IMOS, Dielectric Pocket, VESIMOS, VESIMOS-DP, Parasitic Bipolar Effects, Biosensor

I. Introduction Biosensors are central key component for modern society

due to their wide applications in public healthcare, security, forensic industries, and environmental protection. Currently, enzyme-linked immunosorbent assay (ELISA) based on optical sensing technology is widely used as a medical diagnostic tool as well as a quality-control check in various industries. ELISA needs biomolecules labeling which requires bulky and expensive optical instrument to analyze the specimen. On the other hand, biosensors based on field-effect-transistors (FETs) [1–2] are highly attractive as they promise real-time label-free electrical detection, scalability,

inexpensive mass production, and on-chip integration of both sensor and measurement system.

However, the conventional FET (CFET) based biosensors exhibit some fundamental limitations on the sensitivity and response time [3–5]. Therefore, Impact ionization MOSFET (IMOS) is believed to be the potential candidates to solve some of the limitation leading to an ultra-sensitive and fast electrical biosensor [6]. The vertical IMOS device which is a planar-doped barrier MOSFET has been introduced and investigated [7]. The device does not suffer from either VTH shifts or a change in subthreshold slopes with repeated measurements, mitigate hot electron damages [8−9] and capable functioning properly under high temperature [10]. Therefore, it was observed that the vertical concept of IMOS is better than the planar IMOS in terms of hot carrier effects and hence, device reliability. The vertical IMOS nevertheless suffer remarkable hysteresis and high supply voltage (VDS) [11].

The concept of strained SiGe vertical IMOS was introduced as an attempt to bring down the supply voltages [12]. Both supply and threshold voltage reduce significantly when strained SiGe layer were integrated into the structure. Nevertheless, the device still experiencing low breakdown voltage causes by parasitic bipolar transistors (PBT) effect which affecting reliability of the device. An ultra-low power with low subthreshold swing and high breakdown voltage are imperative for ultra-sensitive and fast electrical biosensor. Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the performance of the device [13]. This paper will therefore investigate the characteristic of Vertical Strained-SiGe Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) of finding viable solution for future biosensing applications.

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II. Structure and Physical Models The expansion of new approach towards high sensitive

detection technique remains a major challenge in bio-based sensing field particularly on the electrical detection of biological species. It is broadly recognized that the sensor sensitivity will increase with the increasing of surface area per unit mass. Thus, high sensitivity at low biomolecule concentration is desirable. Response time is another vital parameter to determine the performance of biosensors. Response time is defined as the time required to obtain a desired sensitivity. Response time can be related to the subthreshold swing (S). Low S value implies low response time. In order to achieve lower S value, an application of strain or alternate materials/design is required for lowering the operating bias.

In general, electrical characteristics of a device are calculated by solving Poisson’s equation and continuity equation numerically within the device defined meshes [15]. Poisson’s equation relates variations in electrostatic potential to local charge densities. Continuity equations are then used to calculate the current densities of the electrons and holes. Continuity equations describe the electron and hole densities that evolve from transport processes and generation-recombination processes. Boltzmann transport framework is use to solve these two equations. The relationship between current density of holes and electrons and carrier concentration is exhibited during this self-consistent process.

Since VESIMOS-DP is an impact ionization based device, avalanche multiplication is the principal carrier injection mechanism for IMOS device operation. At sufficiently high electric field, the carrier is able to initiate the first impact ionization event to create an electron-hole pair. The resulting electron and hole pair created then begin a process of carrier multiplication known as avalanche breakdown. This helps to increase the current tremendously. When the electron travelled through a distance (dx), it will create an average of (αn.dx) electron-hole pairs in the process.

This increment in electron current density due to the electron and hole multiplication event [16] is given by:

dxJdxJ

nnn

n αδ = (1)

dxJdxJ

nnn

n αδ = (2)

Hence,

dxJ

dxJ np δδ

−= (3)

Impact ionization model of carrier generation mechanism

has been employed in this study. II occurs in a sufficiently high electric field, under which the free carriers gain sufficient amount of energy to undergo collision with other free carriers and generate electron-hole pairs (EHP). When the generation rate of the free carriers is high enough, it would result in avalanche breakdown. The impact ionization model employed in this research study was Selberherr’s [17] models, which is a local impact ionization model. The general II process can be described by the equation 6.

(4)

Fig. 1 shows the detailed cross-sections schematic which simulated for the analysis of S value and suppressing the PBT effect of the VESIMOS transistors using Sentaurus package [14]. This structure comprises a source and a drain region with n+ doping, an intrinsic channel containing a highly doped δp+ layer (Boron = 4x1019/cm3) and two sided gates. The source/drain junction thickness was 200nm, the nitride spacer of 20nm and the polysilicon gate thickness of 100nm. The strain SiGe layer thickness is 20nm with Ge concentration of 30%. The thickness of DP layer is also 20nm.

Fig. 1. Schematic cross-sections of vertical strained IMOS structure: (a) standard VESIMOS device, and (b) VESIMOS with DP device.

(a) (b)

ppnn JJG αα +=

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III. Profiles and Characterization An ultra-low power with low S value and high

breakdown voltage are imperative for ultra-sensitive and fast electrical biosensor. Fig. 2 shows the transfer characteristics (IGS – VGS) of VESIMOS-DP device with channel length Lg = 50nm and DP size = 60 nm and body doping NA = 4x1019/cm3.

Fig. 2. Transfer Characteristics, IDS-VGS of VESIMOS – DP for Si0.7Ge0.3, S/D doping =2.0x1018/cm3, VDS=1.75V

By using a linear extrapolation of transconductance gm

(VGS) to zero, 1.39V threshold voltage (VTH) is obtained at VDS = 1.25V and reduced to 1.37V at VDS = 1.75V. The moderately high VTH is expected since the device has two potential barriers to get through which are DP layer and existing δp+ triangular potential barrier. Hence, require large amount of VGS needed to collapse both barriers. The dependence of VTH on VDS that decreased from 1.39V at VDS = 1.25V to 1.37V at VDS=1.75V as the supply of drain voltage provides sufficient energy for the electrons to cross the δp+ potential barrier forming an ON current of the device. In the off-state operation mode, the transistors show a leakage current (Ioff) which is independent of the VGS, but increases with increasing of VDS. A very low off-state leakage current Ioff = 2.32 x 10-15 A/µm and good drive current Ion = 1.6x10-5 A/μm at VDS = 1.25V was explicitly shown in fig. 2. It increases to Ioff = 2.74 x 10-14 A/µm and Ion = 1.8x10-4 A/μm for VDS=1.75V.

Subthreshold value is in direct proportion to the leakage currents. Thus, low S value indicates low leakage currents. A considerable low S value of VESIMOS-DP (S = 19 mV/dec) has justified incorporating DP layer at the drain end intrinsic region. This subthreshold voltage obtained, is much lower than the conventional MOSFET limit which is 60 mV/decade due to impact ionization mechanism of VESIMOS-DP device. It gives the VESIMOS-DP device fastest switching behavior and enhanced its electrical

performance and response time which is imperative for bio-based sensor characteristic. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage as shown in figure 3. It was happen due to the existence of strain SiGe at the channel region has enhanced the carrier transport in the VESIMOS-DP channel. Fig. 3 shows the superb performance of the output characteristics (IDS – VDS) for VESIMOS-DP device with Lg=50nm.

Fig. 3 show that the VDS rise sharply then grew steadily before going into breakdown state. The device undergoes breakdown state above VDS = 2.5V instead of entering bipolar mode for VGS > 1.80V. In bipolar mode, the device acts as a Bipolar Junction Transistor (BJT) where n+ source of the device become an emitter, drain as a collector and δp+ layer as a base. The current flows between collector and emitter when base current which is created by holes generated during impact ionization process existed in δp+ layer region. This mechanism contributes to the lower subthreshold slope, but suffers from hysteresis [12] due to the PBT effect. However, with the presence of DP layer at the drain side region, the PBT effect has been suppressed for VDS ≤ 2.5V. For VDS > 2.5V, the PBT effect has been minimized to a minimum level as the δp+ layer cannot contain with the surge of holes current due to higher II rate. Nevertheless, most of the device application operation voltage is below 2.5V which merit the incorporation of DP layer into the device.

Fig. 3. Output characteristics of VESIMOS-DP device at different gate voltage.

Fig. 4 demonstrates the comparison of subthreshold characteristic for VESIMOS and VESIMOS-DP device taken at VDS = 1.75V.

Breakdown Region

VDS=1.75V VDS=1.25V

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Fig. 4. Subthreshold characteristics of VESIMOS and VESIMOS-DP devices at VDS=1.75V and Si0.7Ge0.3.

The off-state leakage current depicted to be lower by at least two decades in VESIMOS-DP device. A significant increase in S value and VTH is visible in Fig. 5 for a VESIMOS-DP device when compared with VESIMOS. The subthreshold swing inclined from 17.8mV/dec to 19mV /dec and threshold voltage increase from 0.87V to 1.35V due to the presence of DP layer add another potential barrier for electron to get through from source to drain. Higher drive-on current is observed in VESIMOS-DP device which increased by a factor of 2 as compared to that only VESIMOS device. These results confirm that DP layer has significantly suppressed PBT effect by limiting the leakage current passing through drain region in bipolar mode.

IV. Conclusion The investigation on the prospective ideas of finding

viable solution of nanoelectronics device design by an assessment of incorporating vertical impact-ionization MOSFET (IMOS) with strained SiGe technology into a formation of an emerging device structure with elevated performance and reliable outcomes for future bio-based sensor application was successfully analyzed. Enhanced performance of vertical IMOS structure utilizing combined Strained SiGe + DP technology is studied based on process and device simulation tools. VESIMOS-DP shows excellent switching behavior with low S value of about 19mV/dec which is much lower compared to Conventional MOSFET (CMOS). This will eventually enhanced the switching behavior of the transistor and enhancing its electrical performance and response time. In addition, the vicinity of DP layer has been successfully suppressed the PBT effect by attaining high breakdown voltage. In many aspects, it is revealed that the incorporation of DP enhanced the electrical performance of VESIMOS for future development of biosensor nanoelectronic application.

Acknowledgment The authors would like to acknowledge the financial

support from FRGS fund (FRG253-TK-2-2013) of MOHE Malaysia. The author is thankful to the University Malaysia Sabah (UMS) for providing excellent research environment in which to complete this work.

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onI IncreasedVTH Increased

S Swing Increased

IOFF Decreased

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