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Comparative study of two LDOs for supplying a 2.5GHz rail-to-rail VCO

Cristian Raducan, István Kovács, Marius Neag

Technical University of Cluj-Napoca, 28 Memorandumului St., Cluj-Napoca, Romania E-mail: Marius.Neag@bel.utcluj.ro

Abstract—This paper presents a comparative study of two low dropout voltage regulators (LDO) for supplying a 2.5GHz rail-to-rail voltage controlled oscillator (VCO). The effect of the two LDOs noise on the phase noise of the VCO is presented while keeping the supply ripple the same. Both LDO structures are implemented by using the same error amplifier and the same pass transistor, but the classical LDO uses a large off chip decoupling capacitor while the capacitorless LDO employs a current amplifier which forms high bandwidth around the pass transistors to reduce the supply ripple. Post layout simulation results show a -88dBc/Hz and -83dBc/Hz VCO phase noise at 1MHz for the classical and capacitorless LDO. The LDOs and the VCO were designed in 0.18um CMOS process.

Keywords: capacitorless LDO, rail-to-rail VCO I. INTRODUCTION

The low-dropout regulator (LDO) is a linear voltage regulator which can operate even when the voltage across the series pass transistor drops to relatively low values – down to hundreds of mV. Nowadays integrated circuits usually comprise several LDOs, with the dual purpose of providing the necessary voltage levels and separating the supply lines of different blocks, thus preventing/reducing the noise coupling.

A standard LDO employs a large – therefore external – decoupling capacitor at its output, that acts as an energy reservoir for fast load transients [1]. However, systems comprising several such LDOs require a large number of pins, which is not always acceptable. Alternative LDO topologies have been developed, which do not require external decoupling caps. However, most of these “capacitor-less” designs have poor response to fast variations of the current and their power-supply rejection ratio (PSRR) rolls off dramatically with frequency. Several solutions to these shortcomings have been reported in the literature: a damping-factor-control compensation was employed in [2] while in [3] the settling time was improved by using a common-gate amplifier and a direct dynamic charging technique.

This paper presents a detailed comparison between two LDOs designed to supply a rail-to-rail Voltage-Controlled Oscillator (VCO) operating at 2.5GHz: one similar to the typical LDO structure described in [1], employing Miller compensation and a large external decoupling capacitor –

called here the classical LDO – while the second implementation – called here the capacitor-less LDO – has only a small internal capacitor but employs the compensation network proposed in [4] to improve its transient response to the large and fast variation of the load current demanded by the VCO. For a fair comparison, both LDOs use the same pass transistor and the same error amplifier.

Section II presents a detailed description of the two LDOs, including their circuit implementation proposed here, using a standard 0.18um CMOS process. The dynamic load the designed LDOs have to drive – a rail-o-rail VCO – is briefly discussed in Section III. Section IV presents the main simulation results; conclusions are drawn in the last Section.

II. DETAILED DESCRIPTION OF TWO LDOS , WITH AND

WITYHOUT EXTERNAL DECOUPLING CAPACITOR A. Classical LDO

The standard LDO structure shown in Fig.1 comprises a large PMOS pass transistor placed between the input and output, driven by an error amplifier implemented by an operational transconductance amplifier (OTA) enclosed in a negative feedback loop that also includes a resistive divider. A Miller-type frequency compensation is realized by the series RC-CC network: the pole associated with the OTA output - MOS gate node is pushed down to low frequency, while the pole associated with the output node is pushed up to high frequency; it also shifts to the left plane the parasitic zero caused by the direct signal path available through the compensation network, in order to increase the phase margin.

Figure 1: Schematic of classic LDO with Miller RcCc compensation

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Figure 2: The LDO topology proposed in reference [4]

The Gain-Bandwidth product (GBW) of this loop has usually a fairly low value – in the MHz/tens of MHz range; therefore, the loop cannot deal with fast variations of the output current. The transient response bottleneck is the gate capacitance of the pass transistor: for low dropout the pass transistor needs to be large, so its gate capacitance can get as large as several pF or even tens of pF, depending on the maximum current it has to handle; this limits dramatically the Slew-Rate (SR) of the error amplifier, whose current consumption must be kept as low as possible. Thus, only the large off-chip capacitor, Cext, placed at the LDO output can help reduce efficiently the output voltage ripple during fast load transients.

B. Capacitorless LDO The aim of these LDOs is to replace the external capacitor

with an integrable circuit that provides a fast path for abrupt load variations without increasing the GBW of the main loop. Fig. 2 presents the capacitor-less LDO topology proposed in [4]: it is similar to the conventional topology shown in Fig.1 except the RC-CC compensation there was replaced by Cf and a Current Amplifier. These two elements implement a differentiator, which provides both a fast transient detector path as well as internal ac compensation. They form an internal negative feedback loop with a much wider bandwidth than the main LDO loop.

In order for the LDO to respond fast enough to load variations a sensing mechanism with high bandwidth is needed; theoretically this can be achieved by a capacitor: Cf senses the changes in the output voltage through the current If. However, there are obvious drawbacks to doing so: first, connecting Cf between the gate and drain of the pass transistor would have an effect only if its capacitance is greater than the gate-drain capacitance, CGD. Second, a large Cf in parallel with CGD will create a wide feed forward path to the output, degrading the phase margin.

By using a current amplifier as shown in Fig. 2 both these problems are solved: the first by amplifying the capacitor seen at the PMOS gate and the second by blocking the feed forward signal path. The current If is now amplified to levels able to significantly improve the charging/discharging of the PMOS gate capacitance. An important feature of this arrangement is that both the LDO stability and its fast transient response are ensured even for relatively low values of the output capacitor, Cout. Therefore, it can be integrated.

Figure 3: Transistor level implementation of the capacitor-less LDO

C. Transistor-level implementation of the two LDOs Figure 3 presents the transistor-level implementation

proposed here for the capacitor-less LDO shown in Fig.2. The compensation circuitry is similar to the one proposed in [4] but with a different biasing; also, a folded-cascode OTA is used here for the error amplifier in order to improve the PSRR. Mf1 and Rf form the current-input voltage-output first stage of the compensation circuitry; both the inputs and output are low-impedance due to the feedback closed through Rf, which allows for the poles associated with these nodes to be pushed to high-frequency. Mf2 converts the voltage delivered by the first stage into current, which is delivered by the cascode Mc2 to the gate of the PMOS pass transistor. Mc1 and Mc2 help reduce the systematic offset at the output. Also, the two branches of the compensation circuit are biased by two matched cascoded current sources. This circuit was implemented in a standard 0.18um CMOS process. The resulting transistor sizes are summarized in Table I.

For comparison, a classical LDO, with the topology shown in Fig. 2, was also designed for same specifications and using the same error amplifier – as presented on the left-hand side of Fig. 3 – and the same-size PMOS pass transistor as the capacitor-less LDO proposed here. Fig. 4 shows the layout of both LDOs, including the on-chip capacitor Cout, of 100pF.

TABLE I. TRANSISTOR SIZES FOR THE SCHEMATIC SHOWN IN FIG. 3. Transistor name W(µm)/L(µm)

M1, M2 80/0.5 M3, M4 40/2 M5, M6 28/1

M7, M8, M9, M10, M11, M12 16/0.5 M13, M14, M15, M16 24/0.5

Mf1, Mf2 5/0.7 Mc1, Mc2 25/1

Mp 800.1/0.5

Figure 4: Layout of the classical and the capacitorless LDOs

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III. THE LOAD: A RAIL-TO-RAIL VCO A. VCO schematic

The purpose of the LDOs described here is to supply a rail-to-rail VCO operating at 2.5GHz. The VCO shown in Fig. 5.a comprises four delay-cells connected in a multiple feedback topology. Fig. 5.b presents the schematic of the delay cell: it is build around a quasi differential input stage formed by M1 and M2 as the input stage of the main oscillator loop; M7 and M8 form the inputs for the secondary oscillator loop, the cross coupled latch formed by M3 and M4; the oscillating frequency is controlled by VTUNE via M5 and M6 [5]. B. Contributors to the VCO Phase Noise

The VCO phase noise performance depends mainly on two factors: the intrinsic noise of the delay cell and the supply noise, that is noise present on the VCO power lines.

It is difficult to create an accurate noise model for a delay cell with rail-to-rail operation, as the transistors there go through all operating regions. A simple model for the noise power of the rail-to-rail VCO, based on the switching of the transistors noise current, is presented in equation (1).

2

41 (2 )NOISE

m

T kTRPT f RCπ

Δ=+

(1)

where T is the oscillation period, ΔT is the on-time of the transistors of the delay cell, fm is the offset frequency from the carrier and RC is the time constant of the first-order model of the delay cell [6]. The later term implies that the faster the ON/OFF switching of the main transistors is, the lower the noise power generated by the delay cell is.

The noise contribution of the delay cells within the VCO can be reduced by carefully sizing the transistors in that cell. In general, one has to increase the area and the transconductance of a MOS transistors in order to reduce its equivalent noise voltage, which is usually expressed as [7]:

2 8 1( )3

Fn

KkT dfdv f dfgm WL f

= + (2)

Unfortunately, this implies increasing the parasitic capaci-tances associated with the transistor and increasing its biasing current. A tradeoff between power consumption, oscillation frequency and phase noise performance results.

Quite often in practical circuits the main contributor to the VCO phase noise degradation is not the delay cell but the supply noise – more to the point, the LDO which drives the VCO supply line. One needs to consider both the electrical noise generated by the LDO and the effect of the supply voltage variations due to the abrupt changes in the current the LDO has to accommodate when driving a rail-to-rail VCO – called hereafter voltage supply ripple. In our case, the VCO supply current varies between (almost) zero and 50mA.

The classical LDO has the advantage of a simpler structure than the capacitor-less LDO – thus one can expect a lower noise at its output than the later – but its overall effect on the VCO phase noise may be significantly increased if the voltages ripple at its output are larger than in the capacitorless

Figure 5. a). Block diagram of the rail-to-rail ring VCO supplied by the

LDOs b). Schematic of the delay-cell used to implement the VCO

LDO case. In order to get a meaningful result we decided to concentrate on only one aspect, that is the electrical noise at the LDO output. Therefore, the LDOs were designed so that the voltage supply ripple have same amplitude in both cases.

IV. SIMULATION RESULTS All the results presented in this section were obtained by

running post-layout simulations using extracted RC coupled netlists of the two LDO implementations.

The main testbench is shown in Fig. 6: one of the two LDOs is enabled so that it supplies the rail-to-rail ring VCO, set to oscillate at 2.5GHz. When the Classical LDO is active the internal capacitor remains connected to its output but it is insignificant in comparison with the large external capacitor (100pF versus 100nF); when the capacitor-less LDO is activated the external capacitor, CEXT, has to be removed.

Fig. 7 shows that the voltage ripple caused by the large variation of the supply current drawn by the VCO is about the same for both LDO implementations: about 1.2mV.

Figure 6: Test setup for the LDOs

Figure 7: Voltage ripple on the VDD_VCO supply line when driven by the

classical LDO (left) and by the capacitor-less LDO (right) 191

Figure 8: Output noise spectra for the classical and the capacitor-less LDOs

TABLE II. MAIN NOISE CONTRIBUTORS

Classical LDO Capacitor-less LDO Device % of Total Device % of Total

M3 8.8 Mf2 22.4

M4 8.5 Mf1 22.3

M10 1.6 M3, M4 0.8

Fig. 8 presents the output noise spectra for the two LDOs; as expected, the additional circuitry of the capacitor-less LDO results in a larger noise; however, it should be noted that the spot noise at 100kHz is 15% smaller than that reported in [4]. Table II shows the main contributors to the input referred noise, integrated from 100Hz to 100KHz. As predicted by the analytical analysis, transistors Mf1 and Mf2 contribute the most to the LDO noise. Their flicker noise can be reduced by increasing their area; however, this would increase their parasitic capacitances, thus reducing the speed of the circuit. Fig. 9 shows the VCO phase noise for three supply cases: the classical LDO case is very close to the ideal supply one while using the capacitor-less LDO degrades the phase noise by less than 5dBc/Hz until 1MHz offset, but up to 10dBc/Hz at 10MHz. Table III summarizes the main simulation results.

V. CONCLUSIONS This paper presents a comparative study of two LDO

structures: a classical topology that relies on a large external capacitor for dealing with fast changes of the output current and a “capacitor-less” LDO, that employs a fast feedback network composed of a sensing capacitor and a current amplifier, that ensures the fast charge/discharge of the gate capacitance of the pass transistor during fast transients. For a fair comparison both LDOs were designed for same specifications, using the same pass transistor and the same folded-cascode OTA as the error amplifier.

The comparison focuses on the effect the LDOs have on the phase noise performance of a rail-to-rail VCO supplied by them. In general, the VCO phase noise is degraded by both the electrical noise generated by the LDO and the supply voltage variations due to abrupt changes in the output current provided by the LDO; here, the LDOs were designed so that the voltage supply ripple have same amplitude in both cases.

Post-layout simulation results shown that the capacitor-less LDO degrades the VCO phase noise more than the classical LDO but only by a relatively small amount: no more than

Figure 9: VCO phase noise when supplied by the capacitor-less LDO (top), the classical LDO (middle) and by an ideal LDO (bottom)

TABLE III. SUMMARY OF POST-LAYOUT SIMULATION RESULTS

Parameter Classical LDO

Capacitorless LDO [4]

Year Presented here Presented here 2007 CMOS (µm) 0.18 0.18 0.35 Supply Voltage (V) 3 - 5 2.8 - 5 3 Output Voltage (V) 1.8 1.8 2.8 Iout (mA) 50 50 50 Iquiescent (µA) 360 436 65 Response Time (µs) 15.6 0.83 15 Line regulation (mV/V) 10 0.48 Load regulation (mV/mA) 0.036 0.5 PSRR ( @ 1kHz ) -105dB -62dB -57dB Output noise (µV/√Hz) *@ 100Hz **@ 100kHz

1.1* 0.056**

3.9*

0.13** 4.6*

0.63**

Phase noise @ 1MHz (dBc/Hz) -88 -83 NA

Cload (pF) 100000 100 NA Die area (mm2) ~0.07 ~0.05 0.29

5dBc/Hz until 1MHz offset, going up to 10dBc/Hz at 10MHz. The capacitor-less LDO uses only a small (100pF) on-chip decoupling capacitor, while the classical LDO employs a large (100nF) external capacitor. Both LDOs were designed in a standard 0.18 um CMOS process.

REFERENCES

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[2] K. N. Leung, P. K. T. Mok, ''A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation'', IEEE Journal of Solid-State Circuits, vol. 38, no. 10, October 2003

[3] X. Ming, Q. Li, Z. Zhou and B. Zhang, ''An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control'', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 1, January 2012

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