Integrated Design of Efficient & Reliable Motor Drive and PFC Using Low Cost Microcontroller

with Embedded PGAs and CLABilal Akin

University of Texas at Dallas Electrical Engineering Department

Dallas, TX, USA Bilal.Akin@utdallas.edu

Manish Bhardwaj, Shamim Choudhury C2000 Systems & Applications Group

Texas Instruments Incorporated Houston, TX, USA

Abstract - Heating ventilation and air conditioning (HVAC) drives commonly utilize variable speed control to maximize efficiency and increasingly power factor correction (PFC) stage in the rectifier design to comply with regulations, such as IEC 61000-3-2, which limit the input current harmonics. Cycle by cycle control is desired for both the PFC stage and motor inverter. Closed loop control of these stages consumes the entire bandwidth available on a typical microcontroller leaving no bandwidth to implement fault diagnostics, housekeeping and host functions. This paper presents design of motor control and PFC using a single low cost microcontroller (MCU- TI TMS320F2805x) with embedded analog subsystem consisting of programmable gate arrays (PGA) to sense the shunt inverter currents, windowed comparators and DACs for programmable protection levels; and small footprint control law accelerator (CLA) to double the bandwidth. The integrated design reduces the number of components, reducing board size and build cost and enables on the fly changes which brings enhanced control possibilities for a cost sensitive market without compromising on cost.

I. INTRODUCTION A typical HVAC system consists of two inverters which are

used to control the two motors and a front end rectifier stage. Standards such as IEC 61000-3-2 limit the input current harmonics, and therefore a power factor correction stage is becoming increasingly common in recent HVAC systems [1-5]. PFC stage actively regulates the DC voltage of the inverter. A system with poor bus regulation during transients can saturate the FOC regulators and limit torque generation which yields unstable operation particularly for permanent magnet (PM) motors which are frequently less forgiving compared to induction motors (IM).

Rapidly developing technologies in the semiconductor field like the ones detailed in this paper enables manufacturers

add more feature to the products in addition to basic functions, such as fault diagnostics of motors and inverters. Today it is possible to implement both system control and diagnostics of multiple faults such as stator fault, magnet status, broken bars etc. in parallel by means of wider bandwidths [6,7].

Cost sensitive motor control applications utilize shunt current measurements to implement the current loop in the FOC algorithm. Opamps and resistors network are used to realize these shunt current sensing on the application board and the signal is then fed to the analog to digital converter (ADC) pin on the microcontroller. For safe operations, the inverter also needs to be protected for over current conditions which typically require two comparators to trip PWMs in the positive cycle and the negative cycle of the current, op-amps with voltage follower configuration to generate trip references. Fig 1 illustrates a motor control and PFC system using such a scheme with discrete components (Design for sensing circuitry associated with only one motor is shown). The board has mechanism of current sensing and protection for both low and high side current for individual phases of the inverter and for PFC current sensing. It is also noted that the protection voltages in this case is fixed at the board design time with the passive component selection, if a programmable threshold is desired this brings additional cost to the system. Also as the sensing is implemented through shunt resistors, there are significant spikes with ringing effects and noise riding on the measurements. Filtering schemes must then be used to prevent any false over current trips, this is typically done using a RC filter which can delay a trip detection depending on the time constant. The op-amps, comparators and filters used for such a design increase the number of components on board and the build cost, from Fig 1 it is seen that sensing and protection for one motor and PFC itself uses 4 high gain bandwidth opamps for current sensing, 3 opamps for reference generation and 7 comparators for trip generation in case of fault.

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Fig 1 Traditional Motor Control and PFC system using MCU with integrated ADC

Hence there is an obvious need to simplify the design for cost driven markets such as HVAC while keeping cost and board component count down.

In this paper a solution is presented using a new microcontroller, TMS320F2805x, which has a low footprint Control Law Accelerator (CLA), integrated programmable gain arrays (PGA) and protection features. The design of embedded PGA and it’s use in a motor drive application is explained along with the use of the novel windowed comparators with digital filter for fast and accurate protection. The programmable gain arrays can be used to change the gain of the current sensing in real time thus providing accurate current sensing for a wide input range that can improve control performance over wide range of loads. Also the paper briefly discusses how a multi core scheme can be used to implement both on a single controller, with bandwidth spare for host functions such as fault diagnostics on a low cost platform.

A prototype using the TMS320F2805x was designed with a 400V DC interleaved boost PFC topology followed by a 2.5 kW, 3-phase inverter. The inverter is capable of driving all 3-ph AC motors with and without a position sensor. The shunt current sense is directly fed to the ADC pin on the device thus simplifying design of the inverter stage, Fig 3. The results of the embedded PGAs is compared to a board on which sensing is realized using discrete components.

II. SYSTEM INTEGRATION AND IMPLEMENTATION

Control Law Accelerator:

The Control Law Accelerator (CLA) is an independent floating point unit that is present in addition to the main core on TMS320F2805x.

Fig 2 F2805x Architecture

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PWM-1

TMS320F2805x

CLA

CPU32 bit

PWM-1A

PWM-1B

PWM-2A

2H

3H

2L

3L

2H 3H

2L 3L

1

2

3

1H

1L

IPM

PWM-2B4

DC-Bus

3 PhaseAC Motor

15V

VacPFC-2PhIL

PWM-4B

PWM-4A

PhaseCurrent

Feedback

PWM-3A5

PWM-3B 6

BS1 BS3

BS2

Phase-LegCurrent Sense

Inverter Bus Voltage Feedback

Rectified AC Voltage

Feedback Vpfc Out feedback

Motor Drive Stage

PWM-2

PWM-3

PWM-4

PWM-1A/B

PWM-2A/B

PWM-3A/B

PWM-4A/B

AFE(PGA,Comp,DAC,Dfilt)

VLine

VN

Vref-DACOut

Iph-UIph-V

Iph-W

Ipfc

PhaseVoltage

Feedback

VdcBus

VLine

Comms Peripherals

Fig 3 Motor Control and PFC system using TMS320F2805x with integrated analog front end

The CLA is designed to offload the fast control algorithms task, thus freeing up bandwidth on the main CPU (C28x) core. The CLA has it’s own program and data bus as shown in Fig 2, and executes independently of the main core. The CLA interacts with the main core with use of message rams and has access to the control peripheral simultaneous to the main CPU, with it’s own program bus so there are no conflicts while both CPU and CLA access different peripherals.

Fig 4 PFC on CLA and Motor on the main CPU

Fig. 4 & 5 illustrates the sampling times, ISRs, tasks, execution of the algorithm of the PFC and motor control in CLA and the main core respectively. In the integrated system, two approaches can be used: One is in which only the PFC is offloaded to the CLA and the motor control is implemented on the main CPU. This is illustrated in the Fig 4.

Fig 5 PFC and motor on the CLA using time sliced approach for motor control

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Second, in which a time slice approach is used to offload both the motor FOC and PFC algorithms. Fig 5 illustrates the sampling times, ISRs, tasks, execution of the algorithm of the PFC and motor control on CLA and the main core respectively. The motor control task being the slower task and more complex is divided into five parts and each part executed on PFC task execution. This frees up the bandwidth on the main controller, which can now be used entirely for host, monitoring and safety features like fault diagnostics.

The CLA offers additional benefits such as reduced sample to output delay, reduced jitter in execution and improved support for multi frequency loops. This is made possible because the CLA is a task oriented instead of an interrupt service driven machine. In a pipelined CPU the ISR’s can be delayed by an “n” number of cycles if the CPU is executing branch type statements or is already in an ISR when the new ISR is received. However in a task based machine this is not a problem as the auxiliary core waits for the periodic task to trigger before it begins execution. Thus the combination of CLA and CPU enables reduced jitter execution of the tasks, while maintaining the performance benefits of a pipelined machine for the main processor.

III. ANALOG SUBSYSTEM

A. On-chip Opamps and Programmable Comparators

The high slew-rate on-chip opamps with programmable gain and offset features enables high performance PFC and motor control. Particularly for sensorless motor control, depending on the operating point, the sensed quantities might be very low which degrades the accuracy of control. By means of programmable opamps, one can change the gain on the fly to obtain better position information through the observers and higher performance.

The on-chip programmable gain opamps eliminate the opamps and passive components used for shunt current sense externally on the board thus reducing the total number of board components, and thus cost. Reduced numbers of components simplify design and inherently more reliable operation. Fig 6 illustrates the PGAs in the analog subsystem. The first set of internal switches shown in Fig 6 enable the user to observe opamp output and debug the system. On the other hand, the front-end ADC switches help to sense the best measurable two phase currents simultaneously without any latency which is critical for field oriented control.

Since the high PWM duty cycles limit the current sensing through the shunt resistors, this switching mechanism with three shunt resistors enable the optimal current measurement and maximum dc-bus utilization. The embedded comparators are used for over-current protection. Three 6-bit DACs are dedicated to adjust the threshold level for positive and negative cycles of the sensed currents. Once the fault is detected, all the PWMs can be tripped

Fig 6 Analog Subsystem with trip logic

B. Comparator Triggering & Filtering Logic

When the motor current is sensed through the shunt resistors, the spikes caused by the high frequency switching components trigger the protection circuit and shutdown the system unexpectedly. The programmable digital filter inside the analog subsystem eliminates this risk by adjusting the sampling window and associated threshold without degrading the signal sensing accuracy.

Fig 7 Components saving on the inverter stage on the

designed board

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Depending on the hardware dynamics, the user can adjust the filter counter pre-scalar to make sure that only the current pulse spikes are eliminated without suppressing the current information. One can use external filters instead of these digital filters; however, the analog filters can potentially force the system exhibit over-damped behavior which negatively affects the current sensing quality particularly above a certain duty cycle. Also external filters introduce a weak point to the system where additional noise content at various frequencies can penetrate to the current sensing circuits. As shown in Fig 1, 3, 6 & 7, several (external) components used in a typical motor inverter design can be eliminated by means of on-chip components. The experimental verifications show that the performance of the embedded analog and digital components yields very similar results with traditional designs. Also it is obvious that a design with less hardware components results in more robust solutions. Hence, all these embedded sub-systems help the manufacturers design lower cost yet more reliable products. Moreover, the flexible and programmable structure of these subsystems let the user customize the design and further optimize it.

IV. EXPERIMENTAL RESULTS The proposed PFC and motor control system integration is

experimentally confirmed using a prototype compatible with various product lines in TMSF320xx series which is shown in Fig 8. The details of the experimental setup are given in Table-I. The setup is designed to test PFC and 3-ph AC motor(s) with or without sensor. The setup shown in Fig 8 has an induction motor connected to the load to test the system under various operating points.

Fig 8 Experimental setup (a) programmable AC source (b) dyno

controller (c) motor-dyno setup (d) integrated PFC & motor inverter prototype

In order to prove the overall performance of the integrated

system, various tests were run under different conditions and some of those are reported here. In Fig 9, both high and low line results are given where ch2 & ch4 show input AC voltage and input currents respectively, and ch1 shows the motor phase current. The input power is around 450=W, Vbus=385V (a) PF=0.997, Vin=120Vrms (b) PF=0.994, Vin=220Vrms. The switching frequency is 200 kHz and 10 kHz at PFC and

motor inverter respectively. As shown in the Fig 9, the input current is in phase with the input voltage, power factor is higher than 0.99 and the waveforms are almost perfect sine.

During the experimental tests, it is observed that the current reconstruction using shunt resistors through on chip opamps can be achieved successfully. Also the induction motor was run at various operating points without sensor very successfully.

(a)

(b)

Fig 9 Input voltage (red), input current(pink) and motor phase current (blue). Test condition: Pin=450W, Vbus=385 Vdc, (a)

Vin=120Vrms (b) Vin=220Vrms

Table I-PFC and Motor Control Setup Specifications Input Voltage 90-264 Vrms Input Frequency 47-63 Hz Output Voltage (max) 400 Vdc PFC Switching Frequency 200 kHz PFC Loop update Frequency 100 kHz Motor(s) Control ISR Frequency 10 kHz Inverter(s) Switching Frequency 10 kHz System Clock Frequency 80 MHz ADC Resolution 12 Bits PWM Resolution 150 ps

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CONCLUSIONS In this paper, the integration of PFC and motor control

using a low cost microcontroller with on-chip analog / digital subsytems is discussed briefly and the advantages of such integration is highlighted. An alternative solution is summarized which employs the on-chip CLA to off-load the PFC algorithm thus freeing up bandwidth on the main MCU to perform diagnostics, monitoring, safety, housekeeping, communications etc. The device and system level integration strategy used in this study let the user employ only one microcontroller and also get rid of several active/passive components used for signal sensing, protection, filtering etc.; which reduces the overall cost and enhances the robustness drastically.

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