8
PULSED LASER ASSISTED CHEMICAL ETCH FOR ANALYTIC SURFACE PREPARATION Robert Chivas, Scott Silverman, Niru Dandekar Varioscale, Inc San Marcos, CA 92054 USA [email protected]; [email protected]; [email protected] Abstract— Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation for analytic investigations such as: Focused Ion Beam (FIB) circuit edit, Failure Analysis chemical processes (poly-Si etch), Backside SIMS and Optical techniques such as Photoemission Microscopy. PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser. Keywords- SIMS, poly-Si, analytic surface prep, chemical, laser, etch, backside I. INTRODUCTION In what has become an industry standard, Liebert [1] described the basic methodology used to perform backside failure analysis of integrated circuits. Without going in to too much background, this hierarchy can be viewed as being composed of two regions: 1) global backside thinning and surface preparation where the device is prepped to 50-100 μm of remaining material, but with highly accurate surface finish; and 2) local circuit inspection where the circuit element is exposed by preparation to within a few microns of remaining silicon to an active circuit layer. A major challenge to analytic surface preparation is bridging the technology gap between the two regions. Most often the same preparation techniques are applied to both the bulk and analytic preparation steps. Whether it is using a low selectivity (fast) wet etch, or removing electrical contacts and globally thinning silicon by grinding or lapping, the result ends up being a “workaround” instead of a true complete solution. When it comes to highly sensitive preparation requirements, bulk thinning methods involve multiple extra steps and their results can be improved upon. Opportunities to employ Pulsed Laser Assisted Chemical Etch (PLACE) surface preparation can be found in both preparation regimes. A. Global bulk silicon thinning Preliminary fault isolation (global thinning) is often accomplished with Photoemission Microscopy (PEM) and then finer analytic techniques are used once a region of interest is identified. Due to today’s increasingly complex IC structures (> 10 Metal Layers), the advent of 3-D gates (fin-FET), and die stacking, the best opportunity for failure analysis is from the backside of dies and packages. For the initial PEM inspection, remaining layer thickness needs only be ~ 50-100 μm, however, surface roughness and layer thickness uniformity are key challenges to address. In order to collect the faint photonic emissions from circuits, a Silicon Immersion Lens (SIL) is typically used. The challenge to using SILs is that the surface preparation must adhere to a stringent tolerance in terms of surface roughness, layer thickness to the circuit, and uniformity of the remaining layer. This is even more restrictive when HyperSILs are used. A PEM layer should be accurate to less than the depth of focus which is typically on the order of ~ 1 μm and surface roughness in the 10’s of nm scale. To date, PEM preparation requirements have allowed mechanical milling and polishing to suffice for now, but those methods are not ideal. Bulk removal methods are cumbersome, inexact, and induce surface (roughness) and subsurface (crystallinity) damage. They are also not compatible with packaged dies that may be bent due to stress and have live electrical connections. There are several ways to perform bulk silicon removal including precision milling, anisotropic plasma etching, wet chemical etching, and parallel lapping. Precision milling is best suited for removal of bulk silicon of bare dies. In packages, the corner material is hard to access due to the use of rounded drill bits. Dies are also stressed in packages which causes them to bend by as much as 2’ at the edges, making it difficult to ensure remaining layer uniformity. In general, final polishing must be done by hand, which is imprecise and leaves the surface wavy, distorting the PEM image. Alternatively, Anisotropic Plasma consisting of Ar and SF 6 is commonly used for etching Si. However, preferential etching can occur which causes distortions in the IR-PEM image. Anti- reflection Coating (ARC) makes images usable, but the image remains unclear towards the edges. Wet Chemical Etching is generally performed with choline hydroxide or tetramethyl ammonium hydroxide (TMAH) and typically used for fast and highly selective etching of Si compared to SiO2. Selectivity is critical for etching close to the buried oxide layer near poly-Si gates, but less so for PEM imaging at 50-100 μm. Therefore, the fastest etch recipe is often used for bulk removal where selectivity is not a concern. As Table 1 shows, even the fastest step of the wet etch is measured in nm/min. In addition, PEM performed after wet etching shows strong surface roughness along crystallographic planes and images are unclear. From a process standpoint, this 978-1-4577-1680-5/12/$26.00 ©2012 IEEE 2D.6.1

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Page 1: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

PULSED LASER ASSISTED CHEMICAL ETCH FOR ANALYTIC SURFACE PREPARATION

Robert Chivas, Scott Silverman, Niru Dandekar Varioscale, Inc

San Marcos, CA 92054 USA [email protected]; [email protected]; [email protected]

Abstract— Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation for analytic investigations such as: Focused Ion Beam (FIB) circuit edit, Failure Analysis chemical processes (poly-Si etch), Backside SIMS and Optical techniques such as Photoemission Microscopy. PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.

Keywords- SIMS, poly-Si, analytic surface prep, chemical, laser, etch, backside

I. INTRODUCTION

In what has become an industry standard, Liebert [1] described the basic methodology used to perform backside failure analysis of integrated circuits. Without going in to too much background, this hierarchy can be viewed as being composed of two regions: 1) global backside thinning and surface preparation where the device is prepped to 50-100 µm of remaining material, but with highly accurate surface finish; and 2) local circuit inspection where the circuit element is exposed by preparation to within a few microns of remaining silicon to an active circuit layer. A major challenge to analytic surface preparation is bridging the technology gap between the two regions. Most often the same preparation techniques are applied to both the bulk and analytic preparation steps. Whether it is using a low selectivity (fast) wet etch, or removing electrical contacts and globally thinning silicon by grinding or lapping, the result ends up being a “workaround” instead of a true complete solution. When it comes to highly sensitive preparation requirements, bulk thinning methods involve multiple extra steps and their results can be improved upon. Opportunities to employ Pulsed Laser Assisted Chemical Etch (PLACE) surface preparation can be found in both preparation regimes.

A. Global bulk silicon thinning

Preliminary fault isolation (global thinning) is often accomplished with Photoemission Microscopy (PEM) and then finer analytic techniques are used once a region of interest is identified. Due to today’s increasingly complex IC structures (> 10 Metal Layers), the advent of 3-D gates (fin-FET), and die stacking, the best opportunity for failure analysis is from the backside of dies and packages. For the initial PEM inspection, remaining layer thickness needs only be ~ 50-100 µm,

however, surface roughness and layer thickness uniformity are key challenges to address.

In order to collect the faint photonic emissions from circuits, a Silicon Immersion Lens (SIL) is typically used. The challenge to using SILs is that the surface preparation must adhere to a stringent tolerance in terms of surface roughness, layer thickness to the circuit, and uniformity of the remaining layer. This is even more restrictive when HyperSILs are used. A PEM layer should be accurate to less than the depth of focus which is typically on the order of ~ 1 µm and surface roughness in the 10’s of nm scale. To date, PEM preparation requirements have allowed mechanical milling and polishing to suffice for now, but those methods are not ideal. Bulk removal methods are cumbersome, inexact, and induce surface (roughness) and subsurface (crystallinity) damage. They are also not compatible with packaged dies that may be bent due to stress and have live electrical connections.

There are several ways to perform bulk silicon removal including precision milling, anisotropic plasma etching, wet chemical etching, and parallel lapping.

Precision milling is best suited for removal of bulk silicon of bare dies. In packages, the corner material is hard to access due to the use of rounded drill bits. Dies are also stressed in packages which causes them to bend by as much as 2’ at the edges, making it difficult to ensure remaining layer uniformity. In general, final polishing must be done by hand, which is imprecise and leaves the surface wavy, distorting the PEM image.

Alternatively, Anisotropic Plasma consisting of Ar and SF6 is commonly used for etching Si. However, preferential etching can occur which causes distortions in the IR-PEM image. Anti-reflection Coating (ARC) makes images usable, but the image remains unclear towards the edges.

Wet Chemical Etching is generally performed with choline hydroxide or tetramethyl ammonium hydroxide (TMAH) and typically used for fast and highly selective etching of Si compared to SiO2. Selectivity is critical for etching close to the buried oxide layer near poly-Si gates, but less so for PEM imaging at 50-100 µm. Therefore, the fastest etch recipe is often used for bulk removal where selectivity is not a concern. As Table 1 shows, even the fastest step of the wet etch is measured in nm/min. In addition, PEM performed after wet etching shows strong surface roughness along crystallographic planes and images are unclear. From a process standpoint, this

978-1-4577-1680-5/12/$26.00 ©2012 IEEE 2D.6.1

Page 2: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

method introduces additional steps and equipment for wet etching that could be avoided. Even after ARC, PEM images are coarse. Table 1 Etch rates of Choline hydroxide

Etch Temperature (‘C)

Si Etch Rate {nm/min}

SiO2 Etch Rate {nm/min}

Si to SiO2 Etch Selectivity

22 3.8 0.00036 10555 38 17.2 0.0025 6880 52 40.7 0.0074 5500 73 200 0.029 6896 87 344 0.055 6254 93 427 0.083 5144

To date, Parallel Lapping is still a highly effective and widely used method of surface preparation due to its simplicity and robustness. A significant challenge with lapping , however, is that when using this method on packaged dies, the electrical contacts must be cut. Extra processing steps for reconnecting the electrical contacts, not to mention time spent, must be performed if the die is to be used for PEM.

Once the preliminary failure investigation has been performed with an optical measurement and the fault location isolated, more in-depth and finer detailed, application specific, investigations are performed. All fine-detail analysis methods require further bulk Si removal (locally) to very thin remaining layer thicknesses without damaging the delicate structures under test (invasiveness).

B. Fine-detail inspection techniques

Backside Secondary Ion Mass Spectroscopy (SIMS), Focused Ion Beam milling (FIB), and poly silicon (poly-Si) etch are important techniques in Failure Analysis and Reliability Control along with Photoemission Microscopy (PEM).

Backside SIMS is a method for performing dynamic depth SIMS profiling on samples that have been polished from the reverse of the wafer up to the active device region. Surface depth and uniformity play a large role in the method’s success. One of the primary restrictions to effective use of Backside SIMS is the depth of analysis achievable. In many cases this is restricted to 10-20 μm due to surface roughening and other surface defects. [2] Applications include ultra-shallow dopant profiles [3] and analysis of alloy diffusion in ohmic contacts [4]

Poly-Si wet etch that is selective to SiO2 is used to reveal the gate oxide layer below the SiO2 buffer. Various methods have been investigated such as choline hydroxide [5] and TMAH for optimized performance. [6] High contrast, or etch selectivity, is paramount to ensure that the gate oxide is not completely consumed during the process. In most cases, there is a tradeoff between the etch rate and the selectivity as a function of temperature. Gate oxide layers are on the order of 10 nm thick, anisotropic surface preparations could result in gate damage if not well controlled. When approaching the gate oxide layer it is necessary to switch over to a highly selective

etch recipe which slows the process. Even with careful recipe selection, an initial or final polishing step is still required [4].

The method garnering most attention for performing the requisite thin layer preparation is Focused Ion Beam (FIB) milling. Both the Ga ion (XeF2 Gas Assisted Etching, GAE) and the newer Noble gas ion methods (He, Ne, Xe) are used. With FIB methods the invasiveness is an unresolved issue. Ga-ion beams cause subsurface implant damage, and a major limitation of plasma-FIB processes is subsurface trapping of gas bubbles [7]. FIB milling is a sputtering process and re-deposition of material is common. Much time and effort is spent on cleaning the re-deposited material with an added step using an Ar ion beam scan. Often XeF2 is added to assist with etching, however, since XeF2 spontaneously etches Si (even without the ion beam) control and uniformity are an issue.

It is also known that FIB milling causes the immediate surface to become amorphous and final surface roughness is limited. With plasma-FIB the He ion is too small and light for effective milling (slow, not enough removal power). Neon ion source is relatively new and still under investigation for large scale area (µm2) milling. All FIB processes require pre-thinning and substrate preparation, which alludes to the original complications of this field. In general, FIB works best performing nm scale tasks. It is not well suited to large scale removal of material.

C. PLACE solution In this work, we present a novel method of analytic surface

preparation that addresses the most common challenges of backside surface preparation.

Pulsed Laser Assisted Chemical Etching (PLACE) is a highly accurate and sensitive method of surface preparation that is robust and offers simpler implementation than current methods. There is no particle beam column, and the chamber only requires roughing level vacuum. All of the components are available off the shelf (OTS) including the lasers. Our process uses only nanosecond pulses, not femtosecond where the lasers are significantly more expensive. The etching is performed with small amounts of readily available high purity gas. The PLACE method is imminently scalable and is a modular process that can be used alone or in conjunction with other techniques.

Other advantages include purity of process, the fact that it’s a dry process, and that it can be done under vacuum. It’s also an expandable process, as new developments in laser assisted removal techniques provide a continuous spectrum of application space.

PLACE is minimally invasive and has high lateral resolution because the melt zone is tightly constrained to a thin disk melt zone that is determined by controlling the fluence of the laser energy. Surface layer depth is also highly controlled by in situ interference reflectance spectroscopy with accuracy ~ 1 µm.

Contrary to FIB and ablation methods, there is no re-deposition of material. PLACE is a vapor phase reaction. All etched material is chemically converted to a stable gas and

2D.6.2

Page 3: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

removed by N2 purging and pumping the chamber – there is no re-deposition of material that needs to be re-processed.

A unique advantage with PLACE is the annealing quality of the process. PLACE has demonstrated the ability to repair surface and subsurface damage. Crystal phase integrity is maintained on the surface and below with no subsurface defects, polycrystalline clustering, or amorphousness.

PLACE methods are planar on the scale of the spot size with no distortion even to the edge of the field of view. The process is inherently smooth and has surface quality on the order of nm RMS.

PLACE is additionally useful for etching when die sizes restrict the use of other methods such as grinding and lapping. The mechanical and electrical integrity of the device under test is maintained throughout the process. No extra steps, equipment, or time are required such as a wet lab, CNC tool, lapping machine, and etc.

Another advantage is the inherent purity of the PLACE process which can limit surface contamination. In practice, the purity is limited only by the implementation of the wafer handling, vacuum apparatus and the grade of the gas sources.

The PLACE method offers a universal analytic surface preparation technique that enables multiple fine-detail analysis techniques to be performed with minimal complexity, invasiveness, and disruption.

II. PLACE – OVERVIEW The PLACE process uses a high repetition rate nanosecond

pulsed laser to melt a localized, sub-micrometer layer of the wafer surface in the presence of a high purity, halogen gas (e.g. chlorine). When the silicon surface is molten it reacts with the halogen gas to form a stable gaseous byproduct (i.e. no re-deposition). Subsequent to each laser pulse, the silicon re-crystallizes. The depth of the melt can be precisely controlled by the laser fluence (energy per unit area) between melt and ablation threshold allowing annealing of subsurface damage. The removal rate is determined by the molten time at the surface and the molecular gas dynamics. Overall throughput depends on parameters such as laser repetition rate, laser spot size, vacuum system pump times, and wafer sample exchange time. PLACE is a vapor phase reaction comparable to RIE, it is not ablation.

PLACE promotes surface modification in two ways. First, the chemistry can be tuned to remove silicon material and its impurities from the surface. Cl2 and SF6 help volatilize a wide variety of materials. The second is through crystallinity and surface reconstruction. Not only does the PLACE method avoid damaging the surface structure, it has been shown to promote its repair.

Figure 1 Schematic of PLACE operating principles

Figure 1 illustrates the basic process. A visible (typically 532 nm), high average power (8-18W) laser is focused through a window in a vacuum chamber (Figure 1, inset) onto the silicon substrate. Each pulse from the laser melts a local region of the substrate and, in the presence of high-pressure (typically 400 Torr) chlorine backfilled chamber, reacts with an efficiency of the order unity per surface collision to form silicon dichloride. The dichloride then subsequently reacts in the vapor phase to form stable silicon tetrachloride gas. The reaction is limited by mass transport, but because of the microscopic volume, the laser-induced reaction permits an increase of many orders of magnitude in the diffusion-limited rate. By scanning the laser across the silicon surface, patterns can be etched layer by layer to form deep three dimensional structures for trenching to thin layers with fine dimensional control.

PLACE is a pyrolytic (compared to photolytic) process: heat, not photodisassociation, is used to drive the chemical reaction. In practice, the absorption depth of silicon at 532 nm initially limits heat absorption, then as the silicon melts, the absorption increases by two orders of magnitude confining the melt zone to a thin disc. By adjusting fluence, the depth of melt can be controlled to less than 100 nm up to 1000 nm. Even shallower melt depths may be achieved at 355 nm. Only silicon at the surface that is molten is substantially etched so there is no dependence on crystal orientation. The depth of etch is typically much less than the depth of melt and many orders of magnitude smaller than the melt diameter. The shape of the molten zone formed by pulsed laser illumination is a thin disc as shown in Figure 2 (left), as opposed to the very large (5 µm depth) hemispherical melt trench of the CW laser (right). Subsequent to each laser pulse, the silicon re-crystallizes.

Thin disk melt zone per pulse

(controllable 50 - 500 nm depth) SiCl4 (g)

532 nm laser, 30ns, 300kHz

Pyrolytic gas phase Reaction: Si(l) +Cl2 SiCl2(g) + Cl2(g) + SiCl4(g)

Silicon

2D.6.3

Page 4: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

Figure 2 Model of melt zone showing pulsed laser ((right) effects. The pulsed melt zone is highly constrain

The laser energy with PLACE is detimescale of nanoseconds. Initially, the energyfirst nanosecond depends primarily on the roabsorption coefficient. At UV wavelengthsconfined to a 40-50 nm layer whereas for NIRpenetrate greater than 1 µm before melting begTable 2 Absorption as function of wavelength and phy

Table 2 shows the absorption coefficien

temperature and molten silicon at UV, vwavelengths. Note that molten silicon is highlywavelengths. Once melting begins, photonalmost entirely by the liquid silicon. The transthis thin molten surface layer then is driven intto the high thermal gradient at the surface. interface travels downward from the surface afront, reaches a maximum depth depending oand fluence, and then retreats back to the surre-solidification front. During the entire rousurface remains molten and can support chemi

Absorption Coeff {cm-1}

Crystalline Silicon

1.12 E6 1.07 E6 9.00 E3 3.60 E3 50.00

Liquid Silicon 1.46 E6 1.25 E6 7.69 E5

(left) and CW laser ned to a thin disk.

elivered on the y absorbed in the oom temperature s the energy is R the energy can gins.

ysical state

nt for both room visible and NIR y absorbing at all ns are absorbed sport of heat from nto the silicon due

The liquid-solid as a fast “melt-in” on the pulse time rface as a slower und trip, the top cal reaction.

Figure 3 Solidification front velocity and m

Quantitatively, the silicon melt 30 ns to 100 ns pulses at 532 nm w0.8 J/cm2 and 3 J/cm2 respectively. Athreshold, as expected, drops to appr

In practice, the pulse time and with repetition rate. Whereas most to produce very short pulses (laser use high repetition rate with relativorder to generate relatively long pul

These factors as well as the fluenadjusting the optical spot size, can molten zone and the total molten timtime versus solidification velocity fnm wavelength. Note the solidificafrom 1 to 3 m/s as compared to the mshown).

An important advantage of usconfinement of the reaction zone inminimally invasive. When the dcontrolled by the laser fluence, the tzone) is established per pulse. In theis > 600’C in order to melt the siliczone the material stays at room temperature gradient. The surroundwhich enables annealing of subsurpossible problems associated with g

At the same time, we can controsetting the number of pulses per unof spot size, scan velocity and repusing diode pumped solid state (DPaverage power and 200 kHz repetitmolten zone can be scanned acrosThe energy per pulse is 45 µJ andAccording to the figure, the moltemolten depth is ~600 nm. In practrate at 400 Torr chlorine pressconditions is readily achievable. Amm/s, the dwell time for the 50 µwhich is the time for 100 pulses at100 nm of the silicon surface will rethe benefits of annealing subsurface

Wavelength{nm}33735553263310603085001060

meltzone as function of fluence

and ablation threshold for wavelength is approximately At UV wavelength the melt roximately 0.25 J/cm2. energy per pulse will vary pulsed lasers are optimized cavity fully saturated), we

vely low pump energies in ses (20 – 200 ns). nce, which can be varied by determine the depth of the

me. Figure 3 shows molten for different fluences at 690 ation front velocities range melt velocities ~ 20m/s (not

sing a pulsed laser is for n order for the process to be epth of melt is precisely total molten depth (reaction e melt zone the temperature con, but outside of the melt temperature due the high

ding material is unaffected, rface damage and mitigates lobal heating of the sample. ol etching at the surface by nit area with a combination petition rate. For example, PSS) pulsed laser with 9W tion rate, a 50 µm diameter ss the silicon at 100 mm/s. d the fluence is 2.3 J/cm2.

en time is ~300 ns and the tice, ~ 1 nm/pulse removal sure under these fluence At a scan velocity of 100 µm molten zone is 500 µs t 200 kHz. Thus to remove equire ~100 pulses whereas

e damage is likely to require

2D.6.4

Page 5: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

only a few pulses [8] The time to scan an areamm using these parameters is ~500 s. At the throughput is controlled by the repetitionadequate energy exists at higher levels) and thimade to etch faster by controlling that paramet

Figure 4 Process comparison of FIB with PLACE

As a benchmark, we can directly compare

etch efficiencies. Figure 4 has been compileddata on FIB [9] and our own internal results. Rcase is based on the Rayleigh criterion for resorepresented by the focused spot size (1/e2 wibeam for PLACE and the diameter of the ion FIB. The etch rate of Ga FIB (including XeF2augmented by increasing the beam current, twhere Coulomb repulsion effects broaddramatically with little improvement of etch racurve). A Xe Plasma FIB has the highest degwithout the saturation effect. The upper liprocess overlaps the lower limit of the PCurrently we operate in regimes where 103 readily achievable. By adjusting the fluence aPLACE method is scalable to ~ 105 – 106 ultimate upper limits have not been explored y

III. EXPERIMENTAL

A. Overview The process starts by inserting the silico

vacuum chamber that is evacuated and nitrremove primarily air and water. The baselinmTorr using a compact dry pump. Howevtechnical barriers for implementation to highAfter evacuation, a static, sub-atmospheric (eof high purity (VLSI grade) chlorine gas is chamber. Similarly, there are no practicacleanliness and purity of the gas delivery systeapparatus uses VCR4 all metal seal and bellowat the chamber which uses Viton O-rin

0.01

0.1

1

10

100

1000

10000

100000

10 100 1000 10

Rate

(um

3 /s)

Resolution (nm)

Process Comparison: Rate vs. Reso

FIBFIBFIBLACPLAPLA

a of 50 mm X 50 most basic level,

n rate (provided is recipe could be ter.

PLACE and FIB d from published Resolution in this olving two points idth) of the laser milling beam for

2 assisted) can be to an upper limit den the beam ate (knee bend in

gree of scalability imit of the FIB PLACE method. - 104 µm3/s are

appropriately, the µm3/s and the

yet.

on sample into a trogen purged to ne pressure is 50 ver, there are no h vacuum levels. e.g. 400 Torr) fill

delivered to the al limits to the em; currently the ws valves except

ngs. Next, laser

processing occurs through a chamscanned using a high speed deflecmirrors) and the whole chamber is cstage. The silicon remains stationaryno additional source of particle gprocessing is complete, the chlorinewith nitrogen, and then vented tcontamination is limited by wafer ha

HARDWARE All of the work was

apparatus. The components such aOff-The-Shelf (OTS). The opticschematically in Figure 5 and copulsed laser beam combined alonLaser assisted chemical etching (Lgives the option of removing largecoarser dimensional control. For pulsed laser was used exclusively.

Figure 5 Layout of PLACE system with C

Each laser delivers a verticalPockel’s cell is engaged that selepolarization state. By rotating the with a ½ wave plate, a polarizing bedeliver both beams along the same beams enter the Pockel’s cell whichthroughput or block it. The beam isimpinges the galvanometer mirrors Galvanometer mirrors scan both X a rectangular illumination area with The scan rate upper limit is > 200 area covered is > 3 mm2. The turlenses (5x, 10x, 20x) for beam spot that can be rotated in and out of thscalability for numerous new confighigh power etching (2x, larger spot sdetail work (50x, smaller spot delivered without distortion, etch across the entire etch region.

0000 100000

olution

B Ga 30keVB Ga XeF2B Plasma Xe 30KeVCE CWACE 1um depthACE 100nm depth

mber window. The laser is ction system (galvanometer carried by a precision XYZ y in the chamber so there is generation. When PLACE e is evacuated, cycle purged to atmosphere. Particulate andling.

performed on the same as lasers and optics are all cs design is represented

onsists of both a CW and ng the same optical path. LACE) using a CW laser r amounts of material with this work, however, the

CW laser combined.

lly polarized beam and a ectively passes a preferred

UV/VIS laser polarization eam splitting cube is used to optical path. The combined h is then activated to allow s shaped along its path and which control the scan rate. and Y directions providing no distortions to the edges. mm/s and the largest etch

rret houses 3 magnification size and trench size control

he beam line. This provides gurations such as large area size) and lower power, finer size). Since the beam is

uniformity is maintained

2D.6.5

Page 6: [IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Pulsed

The spectrum analyzer and viewing systemthe turret and access the chamber along the sathe laser. The spectrum analyzer (Axon) pfrequency stabilized laser light from 1260 – situ depth measurement is performed uspectroscopy in this configuration. The intsource light is imaged onto the analyzer as it top Si surface and the interface layer to the ICother contrasting material sch as SiO2, metal, pbandwidth sets the coherence and as long as is longer than the optical path length (~ 2x tinterference signal is recorded. This is attempting to etch from full wafer thickness long coherence tunable source exists for thocase, we use the short coherence source anmeasure from ~ 300 µm down to 1 µm.

B. Experiments performed In this work, we demonstrate the versatili

first etching a fully packaged integrated cthickness down to 2 µm remaining silicon preparation methods were used such as preclapping. We analyze the result for surfaceuniformity.

As mentioned previously, the chemical reaonly occurs with molten silicon in the reactiocontention that this makes the effectiveness of to crystal orientation. As an ancillary cofollowing surface and subsurface tests werSi(112) wafers.

In order to quantify the effect of PLACEfinish, a 488 nm Raman study was conducted first part evaluated the surface state after pulsea pristine surface to determine if any structuinduced by melting, etching, and re-solidificazone. The converse test was applied seintentionally damaged the wafer by polishing1.0 and 0.25 µm diamond grit. We verifiedamage with Raman and then observed the effthe damaged material.

A third study was performed to quantifsubsurface damage induced by micro lapping any unintended subsurface damage is inducedmethod. For this test, we analyzed the damagµm slurry. As with the Raman experiments, was applied on an Allied High Tech polishiminutes. The analysis was conducted using Hiray Diffraction (HD-XRD).

IV. RESULTS

A. PLACE on Die Package Figure 6 demonstrates the capabilities

method. The first image on the left is an overvIC under test. A large area trench (3.5 mm etched for access to the circuit elements beloimage, a smaller trench (200 µm x 200 µm) wto a remaining layer thickness of 2 µm, sim

m are aligned with ame beam path as provides tunable, 1360 nm. The in

using reflectance erference of the reflects from the

C (this can be any poly-Si, etc). The coherence length the thickness) an important when (775 µm), but a

ose cases. In this d can accurately

ity of PLACE by circuit from full

layer. No other cision milling or e roughness and

action of PLACE on zone. It is our f PLACE immune onsideration, the re performed on

E on the surface in two parts. The d laser etching of ural damage was ation in the melt

econd when we g with a slurry of ed initial surface fect of PLACE to

fy the extent of and determine if

d by the PLACE e caused by 0.25 the slurry polish

ing wheel for 30 igh Definition X-

of the PLACE view of the entire

x 5.5 mm) was ow. In the middle was etched down mulating analytic

surface preparation. The image onvisible light. It is possible to see cthin layer of remaining silicon offthat the membrane layer is very controlled in situ with a proprietartool and later confirmed with a (Wyko NT2000).

Figure 6 Camera images of PLACE perfor

Overall < 30 mW average lasminimal thermal loading of the wavelength was 532 nm, repetition per pulse), which produced a long ~HD). Using the 10x objective (NAfocused beam spot diameter of ~ 3 fluence is determined to be 2.5 J/cmand above melt threshold as descrwas maintained such that there wapass.

In the trench, better than 200 nm50 μm was observed (Figure 7). better than 500 nm with RMS surfac

Figure 7 Wyko white light interferomembrane trench.

Figure 8 is a typical measuremspectroscopy measurement device.maximum near 2 µm with no ambig

n the right was taken with ircuit elements through the

fering qualitative assurance thin. The etch depth was

ry reflectance spectroscopy white light interferometer

rmed on a small outline IC

er power was incident for packaged IC. The laser

rate was 200 kHz (0.15 µJ ~200 ns pulse (JDSU Q201-A = 0.23), this results in a

µm. From these values the m2, which is below ablaton ribed previously. Scan rate s < 100 nm etch depth per

m uniformity over 50 μm X Thickness uniformity was

ce roughness 40-50 nm.

ometry measurement of thin

ment from our reflectance . The measurement has a uity.

ACCURATE DEPTH CONTROL

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Figure 8 Reflectance Spectroscopy measurement of thi

B. Surface Characterization For these experiments, 3 inch silicon (1

procured with the highest available quality frosupplier (Virginia Semiconductor). The waZone (FZ) type, undoped, and had a haze freeprocess equipment consisted of a pulse lase(Explorer XP, Spectra Physics) that prodaverage power of 5 Watts. The pulse repadjustable from 40 KHz up to 300 KHz, and thvaried between 20 ns and 40 ns wherecorresponded with the lower repetition ratefocused in a 5 microns spot size (5x objectiveused with 532 nm, 35 ns, 300 kHz.

The PLACE process was applied with ind0.6 µJ energy. This created fluence leveexceeding the melt threshold for silicon while ablation, causing reaction with chlorine in the pThe pulse repetition rate of 300 KHz and therate at 40 mm /sec led to about 7.5 pulse hitlength along the scan. The individual lcompleted with 1 micron line space to covemillimeters of area. The PLACE targeted etchnm of the surface layer. The laser treated areawith the initial haze free finish of the CMP pwafers.

488 nm Raman was used to investigate sur488 nm, the penetration depth, ld , is < 0.7 µ521 cm-1 Raman shift as the figure of merit. was provided by an external analytical labLabs, Austin TX).

Raman shift of Si(112) wafers producedsignal comprising of a strong narrow peak aFWHM around 5 cm-1 (Figure 9). There scattering intensity in the spectral range(indicating amorphous phase) or broadeningvalue of the primary peak (indicating popolymorphic phases). The Raman shifts in wafers were nearly ideal and negative effprocessing were not detectable with this probe.

in layer ~ 2µm

12) wafers were om a commercial afers were Float e finish. The laser er model XP-532 duced maximum petition rate was he pulse duration

e shorter pulses e. The laser was , NA = 0.14) and

dividual pulses at els > 1.5 J/cm2 remaining below process chamber.

e laser beam scan ts over 1 micron ine scans were er several square hing about 20-40

as were compared produced Si(112)

rface damage. At µm. We used the The Raman data

boratory (Cerium

d a nearly ideal at 521 cm-1 with

was no excess e 450-490 cm-1 g of the FWHM olycrystalline or

the as-received fects of PLACE .

Figure 9 488 nm Raman of Si pre andchange to surface crystallinity

Alternatively, in Figure 10, 4performed on a damage induced wslurry). The broadened shoulder (4521 cm-1 represents a damaged surepresents data that was taken after One can see the second curve reverifying that surface damage is process.

Figure 10 488 nm Raman showing dammain peak) before PLACE and restored s

C. Subsurface Characterization

Figure 11 XRD of subsurface damage to S

XRD based on 3-axis high resoinvestigate the crystalline structurereceived. Diffraction signals collecseconds produced intensity plots forpeak.

In XRD, the Full-Width-at-corresponds to the tails of the rockthe maximum peak intensity (couBragg reflection peak. The FW1%Mextent of subsurface damage in

200 300 400 500

-200-100

0100200300400500600700800900

1000110012001300

Cou

nts

200 300 400 500

Raman shift / cm-

0

5000

10000

15000

20000

Cou

nts

0.01

0.1

1

10

100

1000

10000

-30 -10 10 30

ω (arcsec)

Si(112) Bragg(224) peak.

0

20

40

60

80

100

d post laser anneal showing no

488 nm Raman was also wafer (via 1.0 µm diamond 50-490 cm-1) of the peak at urface. The second curve pulsed laser chemical etch.

eturns to its original form repaired with the PLACE

maged surface (should on left of

surface structure after PLACE.

Si(112) and repair by PLACE

olution set up was used to e of the Si(112) wafers as cted in intervals of 0.6 arc r the symmetric (224) Bragg

1%-Maximum (FW1%M) king curve that are ~ 1% of unts) of the characteristic M show in greater detail the the reflection peak width

600 700 800

600 700 800

1

-9 -8 -7ω (arcsec)

1% tail Analysis

2D.6.7

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compared to the standard Full-Width-at-Half-Maximum (FWHM) curves, especially at shallow depths. FW1%M Bragg reflection peak broadening is used as the figure of merit for characterizing subsurface damage.

Table 3 highlights the results. The initially damaged wafer is marked as having 0 depth etch. The induced damage manifests as the broadening of the FW1%M to 16.5 arcsec. As the etch depth increases, the reflection peak FW1%M narrows back to its original breadth, 13.3 arcsec, and even shows slight improvement (within the limits of the measurement).

The HD-XRD shows that for 0.25 µm slurry polishing, a damage depth of 1.63 µm was induced. Since the FWHM values near 5 arc seconds were nearly identical to the reference Si (400) standard maintained in our laboratory, in the case of shallow subsurface damage such as this, the analysis is most telling at the (FW1%M) piece of the curve. As the laser etch gets progressively deeper, the FW1%M Bragg reflection peak progressively narrows.

The overlay of multiple XRD scans (Figure 11) shows that the damaged material is being removed and the result is a higher purity surface with proper crystal orientation. Table 3 Rocking Curve data for Si(112) repaired by PLACE method

CMP COTS Damaged PLACE

Depth (um) 0 0 0.16 0.45 0.69 1.34 1.63

FW1%M (sec) 13.3 16.5 14.8 14.2 14.6 13.6 12.5

V. CONCLUSION In conclusion, PLACE offers a novel method of surface

preparation that allows for well controlled etching of Si to ultra-thin layers with uniform depth profile and low surface roughness. PLACE has value as a universal analytic surface preparation tool and can be used to establish the ideal surface for PEM fault isolation. PLACE demonstrates versatility by continuing to prep for the fine dimension techniques such as Backside SIMS and poly-Si etch where a thin remaining surface, uniform surface depth and low roughness are critical

parameters. PLACE also demonstrates process advantages such as less processing equipment, steps, time, and minimized disruption to the effort. It is beyond the scope of this research, but by changing the chemistry, one PLACE tool can perform etching and laser assisted chemical vapor deposition (LCVD) with real-time depth measurement and control.

In this work we have demonstrated the ability to etch a thin membrane, 2 µm, in a trench from the original starting thickness of the IC package, without damaging the package, on one tool, with no wet equipment required. Dimensionality is well controlled with a proprietary in situ reflectance spectroscopy measurement tool accurate to < 1µm. We have established that the laser melting and re-solidification process does not induce crystallinity change; in fact, it promotes the healing of damaged surface structure. We have also analyzed subsurface damage induced by diamond slurry polishing and demonstrated the ability to etch and repair those surfaces as well.

Pulsed Laser Assisted Chemical Etch is promising as a robust universal method of analytic surface preparation at all phases of failure analysis testing.

VI. ACKNOWLEDGMENT The authors would like recognize Xiaolu Kou and Mark

Goorsky in the Department of Materials Science and Engineering, UCLA in Los Angeles CA, for the XRD data.

REFERENCES [1] Silke Liebert, Microelectronics Reliabiltiy 41 (2001) 1193-1201 [2] C Hongo, et al Applied Surface Science 203-204 (2003) 264-267 [3] G Sai Saravanan, et al. Proceedures of CS Mantech 2010, p323 [4] Valentina Korchy, www.engineers.org.il/_uploads [5] Evans Analytical Group, AN 418, May 7, 2007 [6] C De Nardi, et al. Proceedings ISTFA Nov 2005, p256-261 [7] Tan S, Livengood R, Hallstein R, Shima D, Greenzweig Y, Notte J,

McVey S, Prodeedings ISTFA 37, Nov 2011 p 40-45 [8] J. e. a. Yan, "Response of machining-damaged single-crystalline silicon

wafers to nanosecond pulsed laser irradiation," vol. 22, no. 392-395, 2007.

[9] Orsay Physics, EFUG Meeting, ESREF 2011, Bordeaux France

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