Electrical Load Emulator for Unbalanced Loads and

with Power Regeneration

Y. Srinivasa Rao∗

Department of Electronics Engineering

Sardar Patel Institute of Technology

Mumbai, India 400 058

Email: ysrao@spit.ac.in

Mukul Chandorkar

Department of Electrical Engineering

Indian Institute of Technology

Mumbai, India 400 076

Email: mukul@ee.iitb.ac.in

Abstract—The paper presents a method of emulating electricalloads using power electronic Voltage Source Inverters (VSIs). Theloads include machines such as induction motors and three phasediode rectifiers as well as larger electrical systems. The emulationof unbalanced four-wire loads has been achieved using a four-legVSI. The load emulator is effectively a dynamically controllablesource or sink which is capable of bidirectional power exchangewith either a grid or another power electronic converter system.Using load emulation, the feasibility of connecting a particularmachine to a grid or converter under various load conditionscan be examined without the need for any electromechanicalmachinery. The additional feature of the load emulation tech-nique described in the paper is the feedback of power absorbedby the emulator back to the grid. This feedback of power hasbeen termed as power regeneration and has been achieved byanother VSI in current controlled mode with the referencesgenerated using instantaneous p-q-r theory. The consistency ofthe experimental results with the simulation results proves theability of emulator and the proposed testing approach.

I. INTRODUCTION

Load emulation is the concept of controlling a power

electronic converter such as a Voltage Source Inverter (VSI) in

such a manner that its behavior resembles that of an electrical

load such as an induction machine. Real-time simulation

[1]–[6], rapid prototyping [7], [8], hardware-in-loop (HIL)

technologies [9]–[14] used to test control design have been

well reported in literature. In contrast, load emulation as

presented in this paper provides a platform where the behavior

of an electrical load can be emulated in hardware at real power

levels using a controllable VSI. The load emulator can provide

different load characteristics with which the control algorithms

and inverter design can be tested [15], [16]. Therefore, load

emulation offers a more flexible platform for testing inverters

in a laboratory environment.

The load emulator consists of a VSI with its output filter

that can draw or supply currents so that it behaves as the load

that is desired to be emulated. As shown in Fig. 1, an inductor-

capacitor-inductor (L-C-L) filter is chosen as the output filter

to remove the switching frequency harmonics generated by

the VSI. The method to design the L-C-L filter with respect

to the switching frequency of the VSI has been described.

The four-leg VSI has been chosen as the topology of the

emulator VSI since the loads to be emulated are four-wire

unbalanced loads. Moreover, since the VSI draws or supplies

idc

Lf

Ls

Cf

Vdc

n vsavsbvsc

Cdc

isa

Regen.

Converter

Fig. 1. Schematic diagram of four-leg emulator with LCL filter.

current from another source to emulate a load, another VSI

has been connected between the dc link of the load emulator

VSI and the ac grid to regulate the dc bus voltage of the

load emulator VSI. This auxiliary VSI has been termed as

the Regenerative Converter and is a bidirectional power flow

converter.

In a distribution system, the undesirable operation of loads

can adversely affect the source. This is particularly the case

when the source is another VSI. An example is that of a

faulty induction motor fed by a three phase VSI in V/f

control mode. For this purpose, the load emulator has been

made to emulate loads such as the faulty induction motor and

severely unbalanced loads. The results will show the excellent

performance of the load emulator in all the cases. The results

will also show the performance of the Regenerative Converter

and how power is exchanged between the ac grid and the dc

bus of the load emulator VSI.

The current control technique of both the load emulator VSI

and the regenerative converter has been described in [17]. In

this paper, the optimal control technique described in [17] has

been extended for the four-leg VSI. [17] also describes the

method of generating references for the currents to be drawn

by the load emulator VSIs. The Phase Locked Loop (PLL)

that is used in generating smooth sinusoidal templates of the

978-1-4673-0158-9/12/$31.00 ©2012 IEEE 320

+

if (s) is(s)sLf sLs

vs(s)

vf (s)

U(s)Vdc

1/sCf

Fig. 2. VSI with L-C-L filter.

(i)

(ii)

Fig. 3. Transfer function for an LCL filter.

grid voltages has been described in the [17]. Furthermore, the

model of the healthy induction motor and other loads such as

diode rectifiers has been described in [17].

II. DESIGN OF THE L-C-L FILTER

In this section, a procedure to design the LCL filter has

been discussed [18], [19]. The parameters of the LCL filter

have been designed with respect to the resonance frequency

of the filter using the transfer function approach in the splane. Detailed frequency responses of the LCL filter have

been presented in the later part of this section.

Fig. 2 shows the Laplace transform of the circuit with VSI

interfaced through an LCL filter to the ac grid. It is to be noted

that the resistances associated with the inductors Lf and Ls

have been ignored for simplicity. When compared with the

exact Bode plots, it will be observed that the deviations are

minimal. The expression for the resonant frequency of the LCL

filter can be written as

ω0 =

√

Lf + Ls

LfLsCf

(1)

The above expression for the resonant frequency provides

a criterion for designing the LCL filter parameters i.e. Lf ,

Ls and Cf . The gain of the transfer function will fall at a

-60 db/decade after the resonant frequency of ω0. In order to

produce a current is that is devoid of the switching frequency

harmonics that are generated by the VSI, the switching fre-

quency should be chosen sufficiently higher than the resonant

frequency ω0. The switching frequency of the VSIs in the

case of the load emulator is around 10 kHz. Therefore, to

provide adequate filtering capability, the resonant frequency

of the filter has been chosen to be 800 Hz. The filter capacitor

Cf being available only in discrete values is chosen to be

50 µF. The filter inductor Lf has been chosen to be 1 mH.

Therefore, from Eqn. (1), the desired value of Ls is obtained as

3.79 mH. The value of inductor closest to the desired value that

was available in the laboratory was 3 mH. Therefore, Ls has

been chosen to be 3 mH. This results in a resonant frequency

of 821 Hz which is acceptable. These designed values of LCL

filter parameters are used in the simulation and experimental

results.

The transfer function between the current injected by the

VSI into the ac grid and the control signal for a VSI interfaced

to the grid using an LCL filter is shown in Fig. 3. The

frequency response characteristics of the VSI with LCL filter

has a resonance peak at approximately 795 Hz. Moreover, the

gain of the transfer function is not sufficiently low at the range

of frequencies where the switching frequency component

occurs. Therefore, the objective of the controller will be to

increase the gain at lower frequencies to ensure that current

references are tracked with negligible error. Moreover, the

switching frequency of the VSI has to be chosen sufficiently

higher than the resonance frequency.

III. CONTROLLER DESIGN

The control system ensures that the emulator draws a

current is that is approximately equal to the desired reference.

The transient response of the system determines the tracking

accuracy between the demanded and actual current drawn

from the inverter under test. Here the control technique used

is a state feedback control strategy. The literature contains

several methods of controlling a VSI with LC filter. Many

of these are PI controller based. However, for such a multi-

variable dynamical system, control of more than one variable

simultaneously would yield better performance. The LQR is

a method of designing a state feedback controller that enables

the control signal to be affected by the errors in all state

variables simultaneously. The primary advantage of using such

a state feedback controller is the ease in implementation.

The final control implementation merely requires the errors

in the state variables to be multiplied by their respective gain

constants and the final products to be summed. This leads to

ease of implementation especially for load emulation where

the code execution time is required to be of the order of 10

µs.Fig. 4 shows the closed loop control scheme employed for

the VSI of Fig. 3. The state vector chosen is:

x = [is vf if ]T (2)

The state space equations are obtained by applying Kirchoff’s

Current Law and Kirchoff’s Voltage Law to Fig. 3:

x =

−rs/Ls −1/Ls 01/Cf 0 −1/Cf

0 1/Lf −rf/Lf

x

+

00

−Vdc/Lf

u +

1/Ls

00

vs (3)321

cr

+−

e

x

x uu yInverter

Hysteresis

switchingK

Fig. 4. Closed loop control scheme of the optimal feedback controller.

y = is = [1 0 0] x (4)

The output variable y is therefore the current is that is

injected into the grid. However, as stated in the previous

section both currents if and is are measured. The voltage vf

across the filter capacitor Cf also forms the state vector along

with if and is. However, its measurement has been excluded

(a description has been provided later in the section).

The objective of the VSI is to inject a current is that is

approximately equal to a desired reference isr. In the above

equation, u is the emulator inverter’s switching function and

ac grid voltage vs is considered to be a disturbance. The state

feedback controller is an optimal controller designed using the

Linear Quadratic Regulator (LQR) to achieve the objective.

For implementation using DSP, the controller is realized in

a discrete-time form. The continuous time state equations are

converted to standard state space discrete-time form.

x(n + 1) = Gx(n) + Huu(n) + Hww(n) (5)

y(n) = Cx(n) (6)

In this w(n) = vs(nTs) is a disturbance, and Ts is the sam-

pling time interval. The LQR seeks to minimize a performance

index,

J =1

2

∞∑

n=0

[

eT (n)Qe(n) + ucT (n)Ruc(n)

]

(7)

where e = xr−x and the T stands for the transpose of a vector.

Here (7), Q is a diagonal matrix that decides the importance

to be given to the state variables and R is the penalty which is

imposed on the controller. The dlqr function of the simulation

provides the state feedback matrix K,

uc(n) = K (xr(n) − x(n)) (8)

x(n + 1) = (G − HuK)x(n) + HuKxr(n) + Hww(n) (9)

Y (n) = Cx(n) (10)

To obtain the transfer function between the output variable

y and the reference state vector xr, the disturbance w(n)is neglected. Equations (9), (10) are the closed loop state

equations. The system parameters are chosen as Ls = 3 mH,

Rs = 0.01 Ω, Lf = 1 mH, Rf = 0.01 Ω, Cf = 50 µF. Thechoice of Q and R are:

Q =

50 0 00 0.05 00 0 0.01

;R = 65 (11)

where the weightage for is is chosen to be much larger than the

other states in the matrix Q. K = [0.6188 0.0404 0.0929]

with a sampling time of 20 µs. Since the control coefficient

for error in vf is extremely small [0.0404], it is possible to set

this constant at zero. In the case of the emulator presented in

this paper, it was found reasonable to neglect the value 0.04.

This lead to a reduction in the measurement requirement of

vf , and the controller functioned without measuring the filter

capacitor voltages.

The control signals ua, ub, uc for the three phases a, b, c aregenerated from the state feedback control strategy. However,

the fourth leg of the VSI is controlled by applying hysteresis

control to the following control signal:

un = −(ua + ub + uc) (12)

The hysteresis band was chosen such that the average switch-

ing frequency was about 5 kHz. The switching losses in the

emulator inverter at this switching frequency were well within

the maximum permissible losses.

IV. SIMULATION RESULTS

It is desired that the faulty induction motor be emulated

using Digital Signal Processor. This section will describe the

mathematical model that will be solved iteratively to emulate

the faulty induction motor. Fig. 5 shows an equivalent circuit

diagram of three phase induction motor with stator inter-turn

fault [20]–[22]. The model is represented using differential

equations (13) to (20). In this model, fault is not considered

symmetrical with other two phases of the stator. Eqns. (13)

to (18) shows three phase induction motor having stator inter-

turn fault in stationary q-d frame. Eqn. (19) shows the relation

between machine current with machine flux linkage, where

A is the inductance matrix. Eqn. (20) is the electromagnetic

torque equation.

θ r

Rs

Rsibs

ias

ics

N s

N s

iar

ibr

icr

N r

N r

N r

ifRfRsµ

N sµ

N s

Rs

N

N

Stator

Rotor

A

CB

A

C

B

i − ias f

R

R

Rr

r

r

Fig. 5. Induction motor with stator inter-turn fault.

322

d

dtλqs = vqs − Rsiqs +

2

3µRsif (13)

d

dtλds = vds − Rsids (14)

d

dtλqr = −Rriqr − ωrλdr (15)

d

dtλdr = −Rridr + ωrλqr (16)

d

dtλf = −µRsiqs + (µRs + Rf ) if (17)

d

dtωr =

P

2

(

Tem − TL

J

)

(18)

i = A−1λ (19)

where,

i =[

iqs ids iqr idr if]T

λ =[

λqs λds λqr λdr λf

]T

A =

Ls 0 M 0 −Lqs

0 Ls 0 M −Lds

M 0 Lr 0 −Lqr

0 M 0 Lr −Ldr

1.5Lqs 1.5Lds 1.5Lqr 1.5Ldr −Lff

and

Tem =3P

4M

(

isqsisdr − isdsi

sqr

)

−

3P

4Ldr

(

isqrif)

+3P

4Lqr (isdrif ) (20)

where λ is the flux linkage, i = current, v = voltage, Rs = stator

resistance, Rr = rotor resistance, Rf = external resistance to

limit the fault current, ωr = electrical angular speed, µ =Nf

Ns

is the extent of fault, if = fault current, M = 3/2 ·Lms, Ls

= Lls + 3/2 ·Lms, Lr = Llr + 3/2 ·Lms, Lqs = q-axis stator

inductance due to fault, Lds = d-axis stator inductance due to

fault, Lqr = q-axis rotor inductance due to fault, Ldr = d-axis

rotor inductance due to fault, Lff = self inductance of fault

loop.

TABLE IIM PARAMETERS WITH STATOR INTER-TURN FAULT

Rs = 4.9 Ω Rr = 8.1 Ω Rf = 2.64 Ω

Ls = 0.8416 H M = 0.8095 H Lqs = 0.0442 H

Lds = 0.0160 H Lqr = 0.0440 H Ldr = 0.0160 H

Lff = 0.0043 H J = 0.0967 kgm2 P = 4

µ = 0.0833 L − Lvg = 415 vrms Freq. = 50 Hz

Fig. 6 shows the simulation of faulty induction motor using

the two-step Adams-Bashforth integration method with a 20

µs time step. For simulations, the motor with parameters

mentioned in Table I is taken as a reference model. The peak

value of the stator current goes as high as 15 A peak to

peak while starting, which is approximately 8-10 times the

steady state value of full load. From the simulations results

of Fig. 6, it can be seen that unbalanced current references

isa ref , isb ref , isc ref can be tracked with negligible error.

The lower trace shows the tracking performance of a-phase

current. The results of transient response and stability of the

system are shown in [17].

0 0.1 0.2

-10

-5

0

5

10

0

-10

0

10

(i)

(ii)

isa refisb ref isc ref

isa

Time (s)A

A

Fig. 6. Simulation of faulty induction motor with current controller.

V. EXPERIMENTAL RESULTS

A three-phase experimental setup has been built to verify

the accuracy of the proposed system. In this setup the power

circuit is rated at 30 A, 415 V input/output line to line

voltages and 750 V dc bus. Various linear and nonlinear

current references, representing different load characteristics,

are emulated experimentally.

A Digital Signal Processor (DSP), Field Programmable Gate

Array (FPGA) digital hardware system has been designed

to implement load emulation experimentally. In order to get

flexible I/O interface and data acquisition, this system has three

analog to digital converters and a Xilinx XC3S200 FPGA.

Three AD7864-AS2 analog to digital converters are interfaced

to sensor unit for data acquisition of voltage and currents.

Texas Instruments TMS320VC33 DSP is used as a processor

to simulate the load model and generate the current references

with a 75 MHz clock. FPGA act as a pulse width modulator

and control the power switches of the converter using 20 MHz

clock reference.

A. Induction Motor with stator inter-turn fault

Fig. 7 shows experimental emulated results of a faulty

motor’s load model a-phase start up current. The upper trace

shows the output voltage vsa of source VSI. The fundamental

frequency of the source VSI is 50 Hz. The middle trace shows

reference currents isa ref , isb ref , isc ref of faulty induction

motor model. The lowest trace shows tracking performance

of source VSI a-phase reference current isa ref and measured

current isa. Fig. 8 shows experimental results of faulty IM load

model for VSI in constant v/f control mode. The upper trace

shows the unbalanced variable frequency current references

and the lower trace shows the reference and the measured

currents in a-phase. These results verify the simulation results

of Fig. 6 and demonstrate that this control system can be used

to test the inverters even for the faulty motor load models.

323

0 0.05

-200

0

200

0 0.1 0.2

-10

0

10

0 0.1 0.2

-10

0

10

(i)

(ii)

(iii)

isa,sb,sc ref

isa refisa

vsa

VA

A

Time (s)

Fig. 7. Experimental results: emulation of faulty induction motor with sourceVSI.

0 0.5 1

-6

-4

-2

0

2

4

6

0 0.1 0.2 0.3 0.4 0.5

-5

0

5

(i)

(ii)

isa ref

isa ref

isb refisc ref

isa

AA

Time (s)

Fig. 8. Experimental results: faulty IM for v/f control source VSI.

B. Severely unbalanced load

This section deals with the emulation of electrical loads

drawing unbalanced currents such that the sum of the phase

currents is not zero. The emulation of such loads needs a

four-leg inverter. Fig. 9 shows experimental results of four-

leg emulator for two phase load current references. Reference

phase currents are isa = 8 A, isb = 8 A, (peak to peak) and

isc = 0. The upper trace of Fig. 9 shows the emulator phase

currents and the lower trace shows neutral current controlled

by the fourth leg of emulator. The peak to peak neutral current

in is 8 A.

C. Unbalanced leading/lagging power factor load

Fig. 10 shows experimental results of four-leg emulator,

emulating unbalanced leading power factor load current ref-

erences. For experimentation the reference currents are isa =

10 A, isb = 8 A, and isc = 6 A (peak to peak). Figure shows

the a-phase current with a leading power factor of 0.7. Theupper trace also shows the resultant neutral current controlled

by the fourth leg of emulator and the lower trace shows the

tracking performance of a-phase current.

0 0.05 0.1-10

0

10

0 0.05 0.1-10

0

10

0 0.05 0.1-10

-5

0

5

10

0 0.05 0.1-10

-5

0

5

10

(i)

(iii)

(ii)

(iv)

in

isa

isb

isc

AA

AA

Time (s)

Fig. 9. Experimental results: four-leg emulator for two phase currentreferences (isc = 0).

0 0.05 0.1

-50

0

50

0

-10

0

10

(i)

(ii)

isa ref

isa

isavsain

AV,A

Time (s)

Fig. 10. Experimental results: four-leg emulator for leading power factorload.

0 0.05 0.1

-50

0

50

0 0.05 0.1-50

0

50

(i)

(ii)

isa vsain

errorsignal(isa ref − isa)

AV,A

Time (s)

Fig. 11. Experimental results: lagging power factor load emulation.

The upper trace of Fig. 11 shows experimental results of

a-phase current for a lagging power factor of 0.2. The current

references are chosen as isa = 10 A, isb = 8 A, and isc = 6

A (peak to peak). The lower trace shows the tracking error

324

0 0.05 0.1-20

-10

0

10

20

0 0.05 0.1-20

-10

0

10

20

0 0.05 0.1

-20-100

1020

0 0.05 0.1-30-20-100

102030

(i)

(ii)

(iii)

(iv)

isa

isb

isc

in

AA

AA

Time (s)

Fig. 12. Experimental results: four-leg emulator for nonlinear unbalancedload.

between reference and measured a-phase source currents.

D. Unbalanced nonlinear load

Fig. 12 shows the experimental waveforms of four-leg

emulator for three single phase diode bridge rectifiers with

neutral connected and unbalanced load model. Figure shows

unbalanced current references isa = 16 A, isb = 20 A, and

isc = 22 A (peak). The lowest trace shows the fourth leg

current in. From the results, it can be observed that the

controller constantly trace the reference currents of nonlinear

unbalanced active loads. The tracking performance of the

controller remains same even during the periods when the

reference remains zero.

VI. POWER REGENERATION

The regenerative converter serves as the utility end of the

emulator. This feature permits the load emulator system to

return the power taken by the emulated “load” back to the

utility. It does this by maintaining closed-loop control of the

common dc bus voltage, as shown in Fig. 13. The regenerative

converter essentially controls the dc bus voltage to be equal

to a reference, Vdc ref . Fig. 13 shows the control scheme for

the regenerative converter. The compensation and the power

exchange is based on instantaneous p-q-r power theory [23],

[24]. Therefore, in addition to the bidirectional active power

exchange the regenerative converter can also can be used for

general power quality conditioning such as a multifunctional

compensator.

In the p-q-r theory, the instantaneous active power exists

only along the p-axis. The instantaneous powers along the qand r axes are imaginary or reactive powers and are denoted

as qq and qr, respectively. The relation between instantaneous

power and instantaneous load currents in the p-q-r reference

frame is given as:

pqq

qr

=

epip−epirepiq

(21)

+

pcc3-phasesource

transformer e(a,b,c)

Regen.

converter

3-phase

Powerreference

gate pulsescurrent

controllerPWM

modulator

abc to 0αβ0αβ to pqr

pqr to 0αβ0αβ to abc ic

ic ref

Pref load

Vdc link

Vdc ref

idc

PI

Pdclink

Cdc

Fig. 13. The dc bus voltage regulation control system.

where, ep and [ip iq ir] are the Point of Common Coupling

voltage and converter currents in p-q-r reference frame, re-

spectively.

The power reference Pref load for the converter is set based

on the power calculated from the emulated load model. The

term Pref load is then added to the reference active power

Pdclink which is required to regulate the dc bus voltage. The

relation between dc link voltage, dc bus capacitor and the dc

bus power is given as:

Vdc =Pc dc loss + Pdclink

Cdc · ∆Vdc · fripple

(22)

In this expression, ∆Vdc is the permissible ripple on dc link

voltage and fripple is the minimum ripple frequency. For a

specified dc link voltage and with the given permissible ripple

and minimum ripple frequency, the dc link capacitance re-

quired is directly proportional to the p-axis active power drawnby the converter. The numerator of the above expression is the

total instantaneous p-axis power drawn by the compensator.

The term Pc dc loss is the average active power required to

meet the losses in the converter. The term Pdclink is the

average active power corresponding to the power exchange

across the dc bus.

The converter reference currents for the PWM current

controller are calculated in p-q-r reference frame from the

combined reference power by using reverse transformations

as mentioned in [25]. The output of the current controller is

then given to the PWM modulator to get the desired gating

pulses for the converter. In the dc bus regulation loop the actual

dc bus voltage is measured and compared with the reference

Vdc ref . A PI controller is used to compensate the error [26].

Fig. 14, 15 shows the experimental results of bidirectional

active power exchange. Fig. 14 shows the transient ac grid

voltages ea, eb, ec and currents isa, isb, isc seen from the

regenerative converter PCC. The regenerative converter ini-

tially acts as a normal compensator for reactive power and

harmonics; then the emulator is switched on intermediately.

This results in the loading of the common dc bus. At this

325

25V/div 4A/div

50V/div

ea

eb

ec

isa

isb

isc

vdc

(i)

(ii)

(iii)

(iv)

Fig. 14. Experimental results: positive active power transfer by regenerativeconverter.

(iv)

(iii)

(ii)

(i)

Fig. 15. Experimental results: negative active power transfer by regenerativeconverter.

instance, the emulator inverter draws the active power from

the dc bus and transfers it to the ac grid. The regenerative

converter tries to maintain the dc bus voltage by drawing the

active power from the ac grid through an isolation transformer.

Fig. 15 shows the steady state waveform of the voltages

and currents of the regenerative converter. Here the emulator

inverter draws active power from the ac grid and transfers it to

the dc bus. The dc bus would rise if the regenerative converter

is not switched on. The regenerative converter regulates the

common dc bus while transferring the additional average active

power from the dc bus to its ac grid, performing regenerative

power transfer. The 180 degree out of phase line currents with

reference to utility voltages are seen from the Fig. 15. This

demonstrates the negative active power transferred from the

common dc bus.

VII. CONCLUSIONS

This paper has focused on the emulation of unbalanced four

wire loads that are very common in a low voltage distribution

system. Moreover, the regenerative technique employed to

supply the power absorbed by the emulator VSI back to

the grid enables the emulation of high power loads. The

results show the emulation of a variety of loads such as the

faulty induction motor, severely unbalanced loads and neutral

connected unbalanced diode rectifier loads. The performance

of the emulator in drawing currents close to the desired

currents has been shown through experimental results. The

smooth waveforms of the output current are the result of the

good design of the LCL filter.

The capacity of the emulator is limited by the power rating

and bandwidth of the system. A minimum real-time step of 20

µs has been achieved using this platform. This time resolution

is sufficient to simulate the dynamic behavior of most power

electronics control systems and electrical load models.

ACKNOWLEDGMENT

The author∗ is thankful to the Power electronics and power

systems (PEPS) group of IIT-Bombay, India and Sardar Patel

Institute of Technology, Andheri-W, Mumbai for providing the

necessary facilities for carrying out this work.

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