Abstract--In this paper we describe the implementation of a DVB-T2 transmitter on a commercially-available hardware platform. The implementation leverages on the Software-Defined Radio (SDR) characteristics of the platform to attain on-the fly reconfigurability. The paper focuses on the two most computationally intensive blocks of the transmitter: the LDPC encoder and the IFFT processor.

I. INTRODUCTION DVB-T2 [3][4] is a second-generation digital terrestrial

transmission system for television broadcasting. In order to achieve a throughput close to theoretical channel capacity, DVB-T2, while inheriting from DVB-T the OFDM with guard interval modulation scheme – which provides a fundamentally resilient transmission system for the terrestrial channel – extends the range of Inverse Fast Fourier Transform (IFFT) sizes for OFDM and adds new technologies to improve performance. These technologies include forward-error-correction mechanisms (LDPC codes) taken from the DVB-S2 standard, a 256-QAM constellation, a concept called "rotated constellation", and an optional mechanism for transmit diversity based upon the Alamouti scheme [1].

In this paper we describe how to implement a DVB-T2 transmitter with the aim of demonstrating the advantages of a Software-Defined Radio (SDR) approach. Given the complexity of the standard, we focus our description on the two most important building blocks: the LDPC encoder and the IFFT processor (see Fig. 1). The design of these computationally intensive blocks is more critical than in conventional DVB-T because many more modes are defined, both in terms of code rates and of IFFT size (see [1] and Table I). Our SDR implementation matches this flexibility in term of modes and is reconfigurable on the fly, i.e., without downloading any new code to the transmitter. A further contribution of this paper is to show how an SDR approach leads not only to on-the-fly reconfigurability, but also to the

* Supported by the University of Padova under Project CPDA099949.

possibility of reprogramming the system (off-line, in this case) for other transmission standards like, e.g., DVB-H or ISDB-T.

A specific platform, integrating an RF front-end (suitable for the TV bands) and specifically aimed at SDR applications, has been selected to implement our design [7]. As it is the case for most SDR platforms, the architecture of the board includes several different computing cores: a general-purpose processor (GPP), a digital signal processor (DSP), and an FPGA. The DSP and the GPP are made available through a TI TMS320DM6446 "DaVinci" System-On-Chip (SoC). This chip is then connected with an FPGA device, namely a Xilinx Virtex-4 SX35. Fig. 2 sketches the available connections among the main board components.

II. STATE OF DVB-T2 ADOPTION World first DVB-T2 transmission took place in Guldford,

UK, in 2008. After field trials in 2009, consumer equipments are starting to be available this year; UK is pioneering the commercial service since the second quarter of 2010 [6]. As far as enabling technologies are concerned, the first modulator IPs for FPGAs are on the market since April 2010 [5]. Chips for the demodulation are also beginning to be available [8] for inclusion in TVs and set-top boxes. All these solutions (both ASIC- and FPGA-based) are proprietary; as a consequence, we could not obtain implementation metrics for them and accurately compare them with our own.

III. DEVELOPMENT After careful considerations, the mapping of the transmitter

functions to the selected hardware has concentrated the stream manipulation, signaling, orchestration and scheduling of the

SDR Implementation of a DVB-T2 Transmitter: the Core Building Blocks

Carlo FANTOZZI*, Lorenzo VANGELISTA, Senior Member, IEEE,Daniele VOGRIG, Member, IEEE, and Ottavio CAMPANA

Fig. 1. Schematic representation of the DVB-T2 modulation process for a single data stream. The most computationally intensive operations are marked in dark grey.

Input processing

BCH encoding

LDPC encoding

Bit interleaving and demuxing

Gray mapping

Constellation rotation

Cell & time interleaving

Frame building

MISO processing

Pilot insertion

IFFT

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GI and P1 symbol insertion

DAC

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andTABLE I

DVB-T AND DVB-T2: COMPARISON OF MODES DVB-T DVB-T2 FEC Convolutional coding

plus Reed-Solomon LDPC plus BCH

Modulation QPSK, 16QAM, 64QAM

QPSK, 16QAM, 64QAM, 256QAM

Guard Interval 1/4, 1/8, 1/16, 1/32 1/4, 19/256, 1/8, 9/128, 1/16, 1/32, 1/128

IFFT points 2048, 8192 2048, 4096, 8192, 16384, 32768

Modes available in DVB-T2 but not in DVB-T are marked in bold.

2011 IEEE International Conference on Consumer Electronics (ICCE)

978-1-4244-8712-7/11/$26.00©2011 IEEE 391

different tasks into the DaVinci chip, leaving the most computationally intensive tasks to the FPGA.

One of the first challenges we had to tackle was the communication between the DaVinci and the FPGA subsystems. The challenge was motivated by the very high throughput required (61.17 Mbps in the worst case). As it can be seen from Fig. 2, four different communication channels are available: a Serial Peripheral Interface (SPI), an External Memory Interface (EMIF), a proprietary interface called VLINQ, and the channel provided by the so-called Video Processing Subsystem (VPSS). SPI cannot be used because it does not provide enough bandwidth. VLINQ and EMIF were tested and discarded because they proved to be too slow and unreliable when applied on our board. In the end, we decided to use the VPSS, which has been designed to handle video streams but can be adapted to the transmission of other kinds of data and guarantees a maximum throughput of 150 MBps.

Getting then to the core of our description, we implemented the reconfigurable LDPC encoder and IFFT processor on the FPGA. For the LDPC encoder, we adopted the structure proposed by Richardson and Urbanke [2]; the overall architecture is sketched in Fig. 3. LDPC tables are stored in 13 ROMs (one for each data rate required by the DVB-T2 standard) and two dual-port RAMs, one for parity computation and one devoted to output generation. A dedicated control unit creates the address and enables signals for ROMs and RAMs in order to implement the correct functionality. In the first

step, the input data is stored in the first RAM and directly output. Then, the control unit runs the parity generation according to the encoding process [2]. In the final step, the output generator makes the last parity check, the results are produced and, simultaneously, the first RAM is re-initialized for the next encoding process. In order to sustain the worst-

case data rate, we decided to implement two encoders in a ping-pong structure.

For the IFFT processor, we opted for a pipelined architecture based on a radix-2 butterfly with streaming I/O for continuous data processing. This faster architecture trades FPGA resources for speed, but it is fully compatible with the constraints imposed by our device. Using this structure, we implemented a processor that is run-time reconfigurable up to 32768 points. In order to avoid internal overflow, we adopted a rounding structure and an internal data width of 20 bits (10 bits for the real part and 10 for the imaginary part). The structure of the pipeline is optimized to work at the same clock frequency of the LDPC encoder.

IV. RESULTS The implementation has been validated by comparing its

output to the one of a simulator written in Matlab and C++, and no mismatch has been found. On the FPGA, the maximum operating frequency is 110 MHz. The LDPC encoder takes, in the worst case, 2.7 ms for the entire encoding process. For the IFFT, its high parallelization allows a computation latency of 597 μs, in the worst-case scenario (32768 points). The LDPC encoder and IFFT processor together occupy less than 50% of the hardware resources available on the FPGA.

V. CONCLUSIONS Despite the fact that the DVB-T2 standard poses higher

challenges than DVB-T in terms of computational complexity, our work shows that the transmitter can be implemented on commercially-available SDR platforms in a way that ensures on-the-fly reconfigurability.

Our future work will consist in completing the transmitter with all the stream manipulation, signaling and scheduling functions mandated by the DVB-T2 standard, so as to obtain a complete implementation on the chosen SDR board.

REFERENCES [1] S. M. Alamouti, "A simple transmit diversity technique for wireless

communications," IEEE Journal on Selected Areas in Communications, vol. 16, no. 8, pp. 1451–1458, Oct. 1998.

[2] T. J. Richardson; R. L. Urbanke, "Efficient encoding of low-density parity-check codes," IEEE Transactions on Information Theory, vol. 47, n.2, pp. 638–656, Feb. 2001.

[3] L. Vangelista, N. Benvenuto, S. Tomasin, C. Nokes, J. Stott, A. Filippi, M. Vlot, V. Mignone, A. Morello, "Key technologies for next-generation terrestrial digital television standard DVB-T2," IEEE Communications Magazine, vol. 47, n. 10, pp. 146–153, Oct. 2009.

[4] Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2), ETSI EN 302 755 V1.1.1, Sep. 2009.

[5] Commsonic licensable DVB-T2 modulator core, www.commsonic.com/products/TDvbT2Modulator.htm.

[6] Freeview HD offering, www.freeview.co.uk/HD/. [7] Lyrtech Small Form Factor Software-Defined Radio Board,

www.lyrtech.com/Products/SFF_SDR_development_platforms.php. [8] Sony CXD2820R DVB-T2, DVB-T and DVB-C demodulator chip,

www.sony.net/Products/SC-HP/cx_news/vol60/np_cxd2820r.html.

Fig. 2. Connections available between GPP, DSP and FPGA.

GPP (ARM)

DSP

FPGA

Shared RAM

SPI

VLINQ

EMIF

VPSS

Fig. 3. The LDPC Encoder.

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