FPGA Based High Precision Torque and Flux Estimator of Direct Torque Control Drives

Tole Sutikno, Nik Rumzi Nik Idris, Aiman Zakwan Jidin, Mohd Zaki Daud

Department of Energy Conversion, Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM) email: thsutikno@gmail.com, nikrumzi@ieee.org

Abstract- This paper presents an improved FPGA-based torque and stator flux estimators for direct torque control (DTC) induction motor drives, which permit very fast calculations. The improvements are performed by 1) using two’s complement fixed-point format approach to minimize calculation errors and the hardware resources usage in all operations, 2) calculating the discrete integration operation of stator flux using backward Euler approach, 3) modifying the non-restoring method to calculate complicated square root operation of stator flux, 4) introducing a new sector judgment method, and 5) reducing the sampling frequency down to 5μs. To avoid saturation due to DC offset present in the sensed currents, the LP Filter is applied. The simulation results of DTC model in MATLAB/Simulink, which performed double-precision calculations, are used as references to digital computations executed in FPGA implementation. The Hardware-in-the-loop (HIL) method is used to verify the minimal error between MATLAB/Simulink simulation and the experimental results, and thus the well functionality of the implemented estimators.

I. INTRODUCTION

Direct Torque control (DTC) was first introduced by Takahashi (1986) [1] and Depenbrock (1988) [2] as an alternative for controlling induction machines. It has simple structure with fast torque response. Furthermore, it does not require PWM pulse generator, coordinate transformation, position encoder as well as current regulators [3-5].

The DTC algorithm is frequently implemented by serial calculations based on a Microcontroller or Digital Signal Processor (DSP) [3-4, 6]. These hardware are truly software-based platform and is not suitable for an implementation that require high-speed computation. As a solution, FPGA is proposed to perform very fast executions [5, 7]. Moreover, the high sampling frequency in FPGA allows the minimization of torque ripple [8-10].

Unfortunately, it is not easy to implement DTC in FPGA device, especially in performing the torque and flux estimation Complex digital computations are involved, such as binary multiplications, integral operation and also a square root calculation targeted for FPGA implementation; the difficulties of which have been addressed in several researches [11-15].

According to [1-2], sampling time is the crucial part of torque and flux estimation in DTC. Toh [12] has implemented all parts of the DTC in FPGA hardware except for torque and flux estimator whereby it was estimated using the DSP; as a result, the sampling time was reduced to 55μs. On the other hand, Monmasson [5] has developed the implementation of

DTC in FPGA hardware. However since it was implemented using a Xilinx System Generator fixed-point toolbox, the sampling time is limited to 50μs. Ferreira [13] also has difficulty in increasing the sampling frequency, and he only succeeded in reducing the sampling time to 25μs. Other work include [16] with a sampling time of 25μs, and [14, 17] of 150 μs and 100μs respectively.

The main contribution of the research presented in this paper is the new design of the torque and flux estimator for DTC implementation in FPGA, with a sampling time reduced to 5μs. In the design, new implementation architecture, improved digital properties, new square root algorithm and new sector identification method is introduced. They are implemented by using two’s complement fixed-point representation with variable words’ sizes. The design is prepared for fast computation, and therefore there is no need of using CORDIC algorithm [5, 15], soft-core CPU [16], as well as transformation from Cartesian to polar coordinates [18]. By using the proposed method, a simple control structure of DTC as introduced in [1] can be retained. The implementation technique is verified experimentally.

II. DIRECT TORQUE CONTROL DRIVES

Fig. 1 represents the scheme of a DTC drive. The estimated flux magnitude and torque are compared with their references values. Torque and flux comparators consisted of three and two-level hysteresis comparators respectively. The sector judgment is used to evaluate the position of the stator flux vector in DQ coordinates.

The switching table produces the switching status according to the outputs of torque and flux comparators and the sector judgment. These switching status are connected to the inverter, which is connected to the motor. They are also used as the inputs to torque and flux estimator.

Fig. 1. DTC scheme

2011 IEEE Applied Power Electronics Colloquium (IAPEC)

978-1-4577-0008-8/11/$26.00 ©2011 IEEE 122

In order to estimate the stator flux and thetorque, several variables need to be determistator currents from the motor Ia and Ib, are DQ coordinates, which are used in DTC algor

€

ID = Ia

)I2I(33I baQ +=

At the same time, by using the switching st

Sc) produced by the switching table, the statocomponents are determined:

)SSS2(3

VV cbadc

D −−=

)SS(V33V cbdcQ −=

Then, using the calculated Id, Iq, Vd and V

of the stator flux in DQ coordinates are perfor

sDSDDD T)IRV(old

−+= ϕϕ

sQSQQQ T)IRV(old

−+= ϕϕ

Finally, equation (7) calculates flux magn

square root calculation, whereas the electromestimated in equation (8).

€

ϕ s = ϕD2 + ϕQ

2

)II(P43T QDDQ ϕϕ −=

Fig.

e electromagnetic ined. Firstly, the transformed into

rithm, as follows:

(1)

(2)

tatus (Sa, Sb and or voltages in DQ

(3)

(4)

Vq, the estimation rmed as follows:

(5)

(6)

nitude by using a magnetic torque is

(7)

(8)

III. PROPOSED METHOD TO IMESTIMA

The algorithm of torque and fluxin an architecture consisted of six Fig. 2. This architecture has six inpand Ib), 12-bit high voltage DCswitching status Sa, Sb and Sc. Atoutputs: the estimation values of

sector . The sampling time is seby the ADC used.

Fig. 2 Block Diagram of torque

A. Torque and Flux Estimator ArchAll the equations which modell

implemented in a two-stage-pipresented in Fig. 3. Several maperformed in parallel. At the first voltages in DQ-coordinates are cathose results can be used to estimatestage. The resulted currents and fluflux magnitude and the torque estimA 62-bit non-restoring square root compute the flux magnitude.

As a matter of fact, [13] proposedarchitecture should be implemenseparating the computation of stafrom the estimation of the stator can be considered as an immediate

3. The architecture of torque and flux estimators

MPROVE TORQUE AND FLUX TOR

x estimation is implemented main blocks, as shown in

puts: two 21-bit currents (Ia C-supply (Vdc) and three t the end, it produces three torque (T), flux ( sϕ ) and

et to 5 µs, which is limited

e and flux estimators

hitecture ed the motor behavior are ipelined architecture, as

athematical operations are stage, stator currents and

lculated in parallel so that e the stator flux in the same x are used to determine the mation in the second stage. is implemented in order to

d that three-stage-pipelined nted in this module, by ator currents and voltages flux. However, the former calculation and thus, those

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calculations can be merged into one singconsequence, the latency of the estimator is µs to 10 µs.

B. The Digital Properties To achieve a good implementation,

properties need to be considered when estimator. Adopted binary format, quantizatiotime are among those key factors.

1). Binary format representation In this implementation, two’s complem

representation is used in all operations, exceproot calculation. In this particular case, unsirepresentation is applied, since its operand analways positive. The major advantage ocomplement fixed-point representation for reait adheres to the same basic arithmetic princiThe representation makes the system bimplement and capable of easily handling arithmetic that does not require examining operands to determine whether to add or subtr

Recent DTC implementation as in [5, 1632-bit format where some bits might be left ubit format is not appropriate to achieimplementation [13, 16]. Therefore, varapproach [13] is adopted for this implementthe redundant bits can be eliminated by truncminimize the hardware resources usage. In aimplementation, extended word-size more thmagnitude of flux and square root operation is

2). Quantization The determination of word size is one of th

FPGA implementation. On one hand, insuffibits used may reduce the precision or causeerror, which can unstabilize the whole systehand, larger words used may increase the harfor the implementation.

Since two’s complement fixed-point formaimplementation, at least 2 things that needFirstly, the size of the integer must be proavoid the problem of overflow. Secondly, thfractional bits used must be sufficient in ordercalculation error. For example, due to the facurrents Ia and Ib are varied from -10A to 10are necessary for the integer bits. While 16 fracan result in a very good precision, since thebit is very small (≃15 µA).

One of the critical parts in this architecture estimation, where the integration is performedcan easily produce errors if the sampling properly scaled; in this case, Ts = 5 µs = 0.021 bits are necessary at the minimum to repr

gle stage. As a reduced from 15

several digital designing this

on and sampling

ment fixed-point pt for the square igned fixed-point nd its results are of using two’s al numbers is that iples as integers.

both simpler to higher precision the signs of the

ract [14, 19]. 6] generally used unused, while 16-eve good DTC riable word-size tation and so, all cating process to

additional, in this han 32-bit for the s used.

he critical parts in ficient number of e the calculation em. On the other rdware area used

at is used for the d to be verified. operly chosen to he number of the r to minimize the act that the input 0A, at least 5 bits actional bits used e step change per

is the stator flux d. This operation time Ts is not

000005 s. In fact, resent Ts. In this

case, Ts = 0.00000476837 s (0.0However, 27-bit representation isprecision and thus, Ts (0.000000000000000001010011111

Fig. 4 shows the estimated torqustate. From this figure, it can be seefor 21-bit Ts is impreciseMATLAB/Simulink double precisioideal case. In fact, the number of boperation in order to avoid calculaThis will result in the rising of Therefore, truncation process mexcessive increase of the number of

In the example of Iq calculation, ais multiplied by 2, the result shouldbits plus 16 fractional bits). Nevertbits to avoid overflow which maddition operation. Next, when the a

by 331 , which is coded in 1.18 bi

in 8.34 bits, but it is truncated to 6.1

3). Sampling time The sampling time Ts is limited

Therefore all the operations invoperformed within this sampling timeIt should be noted that the use of himportant in DTC implementatiminimizing the torque ripple. The simplementation is normally much l

Fig. 5. The example

Fig. 4. The torque estimation during steady

Matlab double precision; (B) Estimated tEstimated torque for Ts

000000000000000001010)2. s chose to have a better

= 0.00000499934 s 1)2. ue taken during the steady n that the torque estimation , when compared to on estimation, which is the bits is increasing after each ation errors or imprecision. f the hardware area used.

must be performed avoid f bits used

as shown in Fig. 5, when Ib d be in 6.16 bits (6 integer theless, it is stored in 7.16

may happened during the addition result is multiplied

its, Iq should be represented 16 bits.

to 5 µs by the ADC used. olved in this model were e. high sampling frequency is ion, for the purpose of ampling time used for DSP arger than Ts, which is not

of Iq calculation

state. (A) Estimated torque for torque for Ts in 27 bits; (C) in 21 bits.

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less than 50 µs. Therefore, it is reduced by athis FPGA implementation and thus, lower produced, as shown in Fig. 6.

C. Backward Euler Approach The discrete backward Euler

)n(u.T.k)1n(y)n(y +−= . It is implementation in FPGA hardware than the foTrapezoidal method that required the regisprevious value of )1n(u − function. The integration method is also capable of maintastability in the large step size. Thereforbackward Euler integration method is chosenquadrature flux ( Dϕ and Qϕ ).

D. LP Filter In the stator flux estimator ((5) and (6)), R

stator resistance, while Ts is the implementime. These equations correspond to the iBackward Euler Method. In [20-21], it was shshould be added to the integrator inimplementation to avoid integration drift prooffset present in the sensed currents. Thus, (6) become:

1)(T)IRV(( sDSDDD old−−+= ωϕϕ

1)(T)IRV(( sQSQQQ old−−+= ωϕϕ

Choosing an appropriate cut-off frequency

is very important to optimize steady state odepends on the operating frequency. By sfrequency closer to the operating frequency,the estimated stator flux can be reduced. Hintroduce phase and magnitude errors. Thethese errors will not be discussed in this paper

E. Non-restoring Square Root Algorithm

The stator flux ( sϕ ) in DTC drive is calc

Fig. 6. The effect sampling time to torque r(A) Estimated torque for Ts=5µs; (B) Estimated torqu

a factor of 10 for torque ripple is

formula issimpler for

orward Euler and ster to store the backward Euler

aining the system re, the discrete

n to calculate the

s is the estimated ntation sampling integration using hown that a filter n the practical oblem due to DC equation (5) and

)Tsc −ω (9)

)Tsc −ω (10)

for the LP Filter operation, which setting a cut-off the dc offset in However, it will e introduction of r.

culated from the

square root of quadrature flux mastator flux ( sϕ ), the non-restoringproposed in [22] is modified q=quotient and r=remainder):

1r0 −= )bits2( 2

n +

€

q0 = 0 )bits1( 2n +

For i=0 to n-1 do: If 0ri ≥ then

( DDr4r 2n(1)i2n(i1i += −−−+

else

( DDr4r (1)i2n(i1i += −−+

If 0r 1i ≥+

1q2q i1i +=+

else i1i q2q =+

The final result of the square root i

0), coded in 2n bits.

F. New Sector Identification The present work has created a s

sectors of voltage vector based

DDQ 3,3, ϕϕϕ − and 0 refer to

from [23]. With the comparison, it sector of voltage vector comparedthrough arc tan of angle, three sta

QD ,ϕϕ or determination of angle

[15].

Table 1. The proposed simpler ide

Sector Vector Angle Qϕ > 0

I (00, 600) 1 II (600, 1200) 1 III (1200, 1800) 1 IV (1800, 2400) 0 V (2400, 3000) 0 VI (3000, 3600) 0

1: satisfy, 0: not

The proposed method is a single staperformed in parallel without calcufast computation and hence incorrecan be reduced.

II. EXPERIMENThe validation of designed torque

ripple ue for Ts=50µs.

agnitude. To calculate the g square root algorithm as

as below (D=radicand,

) )1qi4(2)i +−−

) )3qi4(2)i2n( ++−−

s equal to qn( 2n -1 down to

impler method to judge the on comparison between

Table 1, which is modified

is simpler to determine the d to conventional method ages comparison based on using CORDIC algorithm

entification of the sectors

Qϕ >

D3ϕ

Qϕ > D3ϕ−

0 1 1 1 1 0 1 0 0 0 0 1

satisfy

age with three comparisons ulation of angle; so it is a ect voltage vector selection

NT SETUP e and flux comparators was

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performed based on Hardware-in-the-Loop (HDTC model in MATLAB/Simulink was simthe same data Ia, Ib, Sa, Sb, and Sc used for thecopied from MATLAB workspace to VHDinputs for the targeted FPGA. The VHDsimulated in ModelSim-Altera before being implemented in FPGA. The test design flowFig. 7.

Fig. 7. Top-down test design flow

In the implementation of DTC based on F

many digital properties that need to be conbinary format representation (data typesampling time and word length (size). Ininaccuracies due to these digital problems canthe estimation. For example, the torque ripplefrom 2N-m to 0.2N-m corresponding to a chatime from 50µs to 5µs, as shown Fig. 6. In digital properties have been considered in the

It is shown in that the calculation of torquebe performed with high precision and smallThe new architecture utilized the backward LP Filter-based estimator, modified non-restoalgorithm and new sector identification, essential elements of high performance DTFurthermore, the design is simple and flexiblsource code can be easily modified. Fotruncation process can be adjusted to avoid exin the hardware resource of FPGA, but its sufficient.

III. RESULTS AND DISCUSSION

The experiments were conducted on

HIL) method. The mulated and then, e simulation were DL codes, as the DL codes were synthesized and

w is presented in

FPGA, there are nsidered, such as e), quantization, n fact, error or n seriously affect e can be reduced ange in sampling this paper, these implementation.

e and flux are can l sampling time. Euler approach,

oring square root which are the

TC motor drives. e and the VHDL

or example, the xcessive increase accuracy is still

N Altera APEX

EP20K200EFC484-2x, and used 2implementation. The tests were pwas operated in steady state condobserved on the oscilloscope. Foresults were compared with simulation results. Fig. 8 presents tand Fig. 10 shows the MATLAB/Simulink simulations anThe results show that experimentawith the simulation in Simulink, double-precision computation.

(a)

(b)

(c)

(d)

Fig. 8. The inputs test. (a) the stator curren

Fig. 9. The comparison between MATL

experimental result for tor

093 logic elements for the erformed when the motor ition, and the results were r validation purposes, the the MATLAB/Simulink

the input test, while Fig. 9 comparisons between

nd the experimental results. al results are in agreement

where it is conducted in

nts Ia & Ib; (b) Sa; (c) Sb; (d) Sc.

LAB/Simulink simulation and rque estimation.

126

Fig. 10 The comparison between MATLAB/Simulink simulation and the experimental result for flux locus.

IV. CONCLUSION FPGA is suitable for high-performance DTC

implementation owing to its high speed processing. The sampling time for the stator flux and torque estimation is extremely small, which cannot be obtained using DSP or fast microcontroller. The choice of word sizes, the binary format and the sampling time used are very important in order to achieve good implementation of the estimators. To get simpler implementation and fast computation, the backward Euler approach to calculate the discrete integration operation of stator flux, the modified non-restoring method to calculate complicated square root operation of stator flux and a new sector judgment method were introduced. The design, which was coded in synthesizable VHDL for the implementation on Altera APEX20K200EFC484-2x device has produced very precise estimations with minimal error and was verified with MATLAB/Simulink double-precision simulation.

ACKNOWLEDGMENT

The authors would like to thank Universiti Teknologi Malaysia for providing the funding for the research.

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