Abstract—The vertical MOSFET is considered as an alternative to nanoscale device structure, due to relaxed-dependence on lithography and easier double gate realization. In this paper, the influence of body doping concentration variation in vertical MOSFET developed using oblique-rotating implantation (ORI) method is investigated. For this purpose, two-dimensional process simulation was made using TCAD tools for several Nsub, namely 1, 4, 7 ad 10.1018 cm-3, respectively. The electrical characteristic and short channel effect i.e. DIBL and subthreshold swing, for different body doping were deliberated. The result also suggests the required change in the pillar design in maintaining the gate channel.

I. INTRODUCTION he recent development of nanometer-scale electronic devices shows higher complexity of design, added with complicated lithography system and very expensive

investments. With the limitation of conventional MOSFET processing in continued downscaling of feature size, vertical MOSFET was emerged as an alternative to it, as well as other innovative structures. Vertical MOSFET takes its name from the current direction that flows vertically from drain to source. It has been named as a promising candidate for its relaxed lithography in channel definition, while maintaining standard processing compatibility [1, 2]. Moreover, as the active area are located at the side of the silicon pillar, it is easier to get double or even surrounding gate construction in vertical structure than in planar, thus enhancing the current drive. The simple implementation of

Manuscript received April 15, 2009. This work was supported in part by

Malaysia’s Ministry of Science, Technology and Innovation (MOSTI), under E-Science Project.

M. A. Riyadi is with the Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai Johor Malaysia. His permanent address is: the Electrical Engineering Dept, Diponegoro University, Tembalang, Semarang, 50271, Indonesia (e-mail: munawar.riyadi@ ieee.org).

Z. A. F. M. Napiah was with faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor Malaysia. He is currently with the Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, 76109, Durian Tunggal, Melaka, Malaysia (email: zaf5297@yahoo.com).

J. E. Suseno is with the Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai Johor Malaysia, currently on leave from the Physics Dept., Diponegoro University, Semarang, 50271, Indonesia (e-mail: jatmikoendro@ gmail.com)

I. Saad is with the School of Electrical Engineering & IT, Universiti Malaysia Sabah, 88999 Kota Kinabalu, Sabah, Malaysia (e-mail: ismail_saad@ums.my).

R. Ismail is with the Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai Johor Malaysia (phone: 60-7-55-35280; e-mail: razali@fke.utm.my).

self aligned double gate in vertical structure is another advantage in process compared with the planar.

Until recently, many researchers have investigated a number of vertical structures for tens of nanometre size. Several fabrication techniques have been proposed, either by layer epitaxy[3-6], solid diffusion[7, 8] or ion implantation methods[9-12]. So far, several problems still persist, such as the compatibility to CMOS standard processing, high parasitic components and short channel effect. Epitaxy method seems to be an easier way to define the channel region, but it faces difficulties for CMOS processing for different epitaxy type in N- and PMOS. The solid diffusion technique makes use of complicated additional sacrificial layers with thermal budget concern. Conventional implantation method allows the CMOS compatible processing; however sharp channel forming at the pillar was limited by either the silicon pillar height itself or by the nitride spacer thickness which is applied as a mask for sidewall region. Moreover, the short channel effects (SCEs) such as threshold voltage (VT) roll-off, drain induced barrier lowering (DIBL) and ION/IOFF roll-off are critical at shorter Lg which determine the device performance, and lack of SCE control could prevent further scaling of the device.

Parasitic overlap capacitance problem is commonly found in vertical MOSFET structure. Subsequently this parasitic effect is minimized by several techniques such as by incorporating dielectric pocket[13, 14], fillet oxidation (FILOX)[12] technique or by introducing ORI method[15]. The ORI method has shown a better shape of source region in the bottom, with the drain-to-source current flowing in pure vertical direction, rather than with non-ORI or generic implantation technique which produces L-shaped channel (Fig. 1). Moreover, combined with FILOX technique, it was convincingly improving the channel scaling which ensures the vertical current direction and corner effect reduction in the silicon pillar[15, 16].

This paper is the continuation of previous work in characterizing the ORI method-based vertical MOSFET. This paper will focus on the body doping influence of the electrical characteristic of the device, and the related design consequences that may required in different substrate concentration. It is predicted that the body doping will influence the threshold voltage value, as it happens in conventional MOSFET, but the structure changes or the performance in short channel region is not yet elaborated extensively for vertical MOSFET, especially with the ORI method for the fabrication. Moreover, the understanding on the practical design consideration will be of benefit for further application based on this device.

Body doping influence in vertical MOSFET design Munawar A Riyadi, Student Member, IEEE, Zul Atfyi F. M. Napiah, Student Member, IEEE, Jatmiko E Suseno, Student Member, IEEE, Ismail Saad, Student Member, IEEE, and Razali Ismail, Member,

IEEE

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II. DEVICE FABRICATION WITH BODY DOPING VARIATION

Fig. 1. The cross section of vertical MOSFET with ORI method (a) and with generic implantation technique (b).

In investigating the body doping effect, a vertical MOSFET structure fabrication with ORI method (Fig. 1(a)) was simulated using Athena. Substrates with different concentration (Nsub = 1, 4, 7 and 10 x 1018 cm-3, respectively) were selected in order to understand the body doping effect. The pillar was formed by dry etching of the substrate which was selectively covered by nitride as etch mask, with the width of nitride equals to the pillar thickness tsi. In addition, the channel length definition is affected by the selection of the height of pillar, and also by the body doping.

Stress relief oxide was thermally grown over all silicon surface, followed by active area definition by the deposition and anisotropic etch of nitride layer. Later, a thermal oxidation process was held to produce FILOX. The self-aligned source and drain region was constructed by arsenic implantation (6.1015 cm2, 150 keV) using Oblique Rotating Implantation (ORI) method. After etching of nitride spacers and stress relief oxide underneath, a 3-nm silicon oxide layer was grown on the sidewall of pillar as a gate dielectric. Later, polysilicon with in-situ doping (As, 1019 cm-3) was deposited and patterned using dry etch to form double gate structure. After deposition of LTO for isolation, rapid thermal annealing (RTA, 11000C, 10 s) was carried out for dopant activation. Aluminum was used as metal contact at source and drain.

The body doping influence on the pillar’s height design exists, as shown in Fig. 2 (taken for Lg = 50nm). The pillar’s height, formed by silicon etching, contributes to the channel length (extracted from junction-to-junction length), due to the region unoccupied by the junction created after implantation (and thermal activation). The shorter pillar’s height contributes to the smaller the tendency of the channel length, vice versa. The substrate concentration have an impact on the junction of drain on the top of pillar, thus in order to create same channel length, the pillar’s height has to be adjusted for different body doping. It is shown from Fig. 2 that the pillar’s height tends to increase while body doping is reduced. It is also revealed that the pillar thickness variation only give small impact on the pillar’s height definition.

Fig. 2. Pillar height as a function of body doping variation (for Lg = 50nm (square),70nm (triangle) and 100 nm (diamond, tsi = 45 nm))

The drain junction, and source as well, is influenced by the substrate concentration. If an n-type device with certain pillar height is doped with certain p-type impurities, the junction created will be larger in lower substrate concentration, thus the channel length created will be shorter, following the equation:

Lg = hsi – (Xjd + α. Xjs) (1)

Where Xjd and Xjs are the drain and source junction, respectively, and α is a coefficient representing a factor of junction extension in the sidewall of pillar. The parameters of Xjd , Xjs and α are a function of body doping.

Moreover, the lateral extension junction (in x-axis direction) is also related closely to the body doping. In certain pillar thickness tsi, the source junction in either side will eventually meet if the lateral junction is growing larger than half the tsi, which will make the channel region “floating”. The floating body is another concern in ORI-based double gate vertical MOSFET, as discussed extensively in other paper[16].

Fig. 3. The threshold voltage shifting of vertical MOSFET as the result of the variation of body doping (tsi = 45 nm, Lg = 100 nm, Vds = 0.1V)

III. ELECTRICAL CHARACTERISTIC The electrical characteristics of the device were obtained

by simulating the final structure using SILVACO's ATLAS

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software package. The electrical performance of the device was taken for various substrate concentrations at several channel length. The short channel effect, especially on the threshold voltage was also studied.

The most remarkable effect of the body doping is that its higher concentration increases the threshold voltage of the device, as suggested by the Id-Vg curve (Fig. 3). This phenomena has been suggested previously in [17] for conventional MOSFET, and also applies in this vertical MOSFET.

It is notable that for device with Nsub = 1.1018 cm-3, the threshold voltage almost go into negative value (Vt = 0.06 V for Lg = 100 nm, tsi = 45 nm, Vds = 0.1V), while negative value of Vt is unwanted in many applications, as it will go into ON state in the absence of stimulus (Vg = 0V), or that it requires negative potential to make it off. In this case, the body doping choice should be fitted with the requirement of the threshold voltage and the application. In other hand, a too high threshold voltage implies higher voltage to switch it on, therefore a power consumption issue will prevail. Moreover, substrate with specific (or added) body doping is sometimes needed when a threshold voltage adjustment is required.

Fig. 4. Drain current of vertical MOSFET in logarithmic scale as a fuction of gate voltage and body doping

Another body doping effect is revealed in the subthreshold region. The subthreshold region of the drain current (Fig. 4) shows the tendency of steeper slope for lower body doping and the decreasing level in the higher concentration. The steep slope (or lower swing value, in mV/decade) is required as it shows better capability in switching between on and off state. The effect on threshold voltage, subthreshold swing and power consumption is a thread-off which requires some more consideration in design.

The body doping influence is prevalent in short channel effect for ORI base vertical MOSFET, particularly for relatively large tsi. Fig. 5 shows the subthreshold swing variation in the short channel. The lower body doping produces lower swing value, and for Nsub = 1.1018 cm-3, the swing (66.7 mV/dec) is close to ideal (i.e. 60 mV/dec), while for higher concentration, it produces higher swing. However, when the channel length is considerably small, the reduction

of swing is less than that of longer channel length. This can be explained by the formation of fully depleted

device in lower body doping, especially for Nsub = 1.1018 cm-3, while for Nsub = 1.1019 cm-3 the device is in partial depletion. The fully depletion allows the carrier to move easily along all channel region, thus enabling the faster switching operation, and eventually lower swing value (steeper slope, in the Id-Vg logarithmic graph). While in partial depletion, only part of the channel is depleted, thus it has the isolated region as a path of leakage.

Fig. 5. Subthreshold swing for short channel in various body doping

Fig. 6. Threshold voltage variation on the body doping effect

The threshold voltage roll-off is more evident in higher body doping, as shown in Fig. 6. As mentioned previously, the threshold voltage is reduced for lower body doping. The channel length variation shows that the short channel effect is bigger in higher body doping, due to the partial depletion in the channel region. The non-uniform density and contour of the channel region as the result of junction extension in ORI-based vertical MOSFET provides more deviation on threshold roll-off, which is different for the case of tightly shaped, uniform channel in double gate MOSFET[18].

The body doping variation in channel region produce thread-off performance: lower doping shows better subthreshold swing and better short channel effect immunity, but it suffers from higher off-current. In other hand, higher doping eventually prevents the negative value

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of threshold voltage in the cost of larger roll-off and potential DIBL. Moreover, the higher substrate concentration is likely to reduce the carrier mobility of the device, in addition to the variation of doping caused by the fabrication variation. However, the variation of body doping can be combined further with the design of pillar thickness to obtain optimized result, especially in the case of fully depleted device.

IV. CONCLUSION The simulation of body doping variation in ORI-based

vertical MOSFET reveals important issues. The variation of body doping affects the pillar design in vertical MOSFET, thus this concern should be addressed accordingly. The higher body doping produces higher threshold voltage, either in long or short channel, as expected from its depletion formation. In addition, the short channel effect is mor prominent in higher body doping, especially when the device run in partially depletion. The depletion phenomena in the channel region along with its shape are believed to provide the variation of the subthreshold characteristic. The subthreshold swing is getting closer to ideal value when the doping is lower, but the off-current raises the applicability issue for the device. For the design aspect, the thread-off should be carefully taken to exploit the benefits of lower body substrate while avoiding the low threshold voltage and high leakage.

ACKNOWLEDGMENT The authors express their gratitude towards Research

Management Centre – UTM for their help in the preparation of this work, and Malaysia’s Ministry of Science and Innovation (MOSTI) for funding the research.

REFERENCES [1] E. Gili, V. D. Kunz, T. Uchino, M. M. A. Hakim, C. H. de Groot, P.

Ashburn, and S. Hall, "Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance," IEEE Transaction on Electron Devices, vol. 53, pp. 1080-1087, 2006.

[2] S. Hall, D. Donaghy, O. Buiu, E. Gili, T. Uchino, V. D. Kunz, C. H. de Groot, and P. Ashburn, "Recent developments in deca-nanometer vertical MOSFETs," Microelectronic Engineering, vol. 72, pp. 230-235, 2004.

[3] J. Moers, D. Klaes, A. Tonnesmann, L. Vescan, S. Wickenhauser, T. Grabolla, M. Marso, P. Kordos, and H. Luth, "Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth," Solid-State Electronics, vol. 43, pp. 529-535, 1999.

[4] L. Risch, W. H. Krautschneider, F. Hofmann, H. Schafer, T. Aeugle, and W. Rosner, "Vertical MOS transistors with 70 nm channel length," IEEE Transactions on Electron Devices, vol. 43, pp. 1495-1498, 1996.

[5] C. Fink, K. G. Anil, W. Hansch, S. Sedlmaier, J. Schulze, and I. Eisele, "MBE-grown vertical power-MOSFETs with 100-nm channel length," Thin Solid Films, vol. 380, pp. 207-210, 2000.

[6] D. Behammer, L. Vescan, R. Loo, J. Moers, A. Muck, H. Luth, and T. Grabolla, "Selectively grown vertical Si-p MOS transistor with short channel-lengths," Electronics Letters, vol. 32, 1996.

[7] J. M. Hergenrother, S. H. Oh, T. Nigam, D. Monroe, F. P. Klemens, and A. Kornblit, "The vertical replacement-gate (VRG) MOSFET," Solid State Electronics, vol. 46, pp. 939-950, 2002.

[8] H. Liu, J. K. O. Sin, P. Xuan, and J. Bokor, "Characterization of the ultrathin vertical channel CMOS technology," IEEE Transactions on Electron Devices, vol. 51, pp. 106-112, 2004.

[9] K. Mori, A. K. Duong, and W. F. Richardson, "Sub-100-nm vertical MOSFET with threshold voltage adjustment," IEEE Transactions on Electron Devices, vol. 49, pp. 61-66, 2002.

[10] T. Schulz, W. Rosner, L. Risch, A. Korbel, and U. Langmann, "Short-channel vertical sidewall MOSFETs," IEEE Transactions on Electron Devices, vol. 48, pp. 1783-1788, 2001.

[11] H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, "A novel spacer process for sub-10-nm-thick vertical MOS and its integration with planar MOS device," IEEE Transactions on Nanotechnology, vol. 5, pp. 554-563, Sep 2006.

[12] E. Gili, V. D. Kunz, C. H. de Groot, T. Uchino, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, and P. L. F. Hemment, "Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance," Solid State Electronics, vol. 48, pp. 511-519, 2004.

[13] S. K. Jayanarayanan, S. Dey, J. P. Donnelly, and S. K. Banerjee, "A novel 50nm vertical MOSFET with a dielectric pocket," Solid State Electronics, vol. 50, pp. 897-900, 2006.

[14] D. Donaghy, S. Hall, C. H. de Groot, V. D. Kunz, and P. Ashburn, "Design of 50-nm vertical MOSFET incorporating a dielectric pocket," IEEE Transactions on Electron Devices, vol. 51, pp. 158-161, 2004.

[15] I. Saad and R. Ismail, "Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method," Microelectronics Journal, vol. 39, pp. 1538-1541, 2008.

[16] M. Riyadi, I. Saad, and R. Ismail, "Silicon Pillar Thickness Effect on Vertical Double Gate MOSFET (VDGM) with Oblique Rotating Implantation (ORI) Method," in Proceeding of IEEE International Conference on Semiconductor Electronics (ICSE) 2008, Johor Bahru, Malaysia, 2008.

[17] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and Hon-Sum Philip Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proceedings of the IEEE, vol. 89, pp. 259-288, 2001.

[18] H. X. Lu, W. Y. Lu, and Y. Taur, "Effect of body doping on double-gate MOSFET characteristics," Semiconductor Science and Technology, vol. 23, p. 015006, Jan 2008.

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