Modeling of Temperature Variations in MOSFET Mismatch for Circuit Simulations

Muhamad Amri Ismail1,2, Iskhandar Md Nasir1, Razali Ismail2 1MIMOS Berhad, Technology Park Malaysia, 57000 Kuala Lumpur, MALAYSIA

2 Universiti Teknologi Malaysia, 81300 Skudai, Johor, MALAYSIA amris@mimos.my, iskhand@mimos.my, razali@fke.utm.my

Abstract Temperature effect is one of the critical factors in

manufacturing variability which could affect the designed circuit. This paper presents a MOSFET mismatch model with the consideration of temperature variations using physical based SPICE model parameters. The model development includes the mismatch measurement at different temperatures and enhancement of standard device model card. Mismatch temperature coefficients with respect to threshold voltage and carrier mobility are used to improve the prediction of mismatch model. The comparison between measured and Monte Carlo simulated data is presented for the verification purpose. The model is applied into the circuit design example to show the significant of the extracted mismatch temperature coefficients.

1. Introduction MOSFET mismatch effect has gained a lot of attentions

from circuit designers and even to the wafer fabrication personal as it could seriously contributed to the circuit yield. Although the issue of random mismatch is initially associated with the precision analog design, continuous CMOS technologies down scaling has made it significant even to the digital circuit applications [1]. With the ever increases of the uncertainties in the fabrication process control, the availability of statistical model that could quantify the mismatch effects is essential. An accurate mismatch model could be used in order to predict the circuit yield as well as for design optimization purpose.

Beside the process and voltage variations, temperature is another effect that needs to be under controlled. Since the critical electrical parameters are fundamentally sensitive to the temperature changes, most of the standard compact models available in the semiconductor industries are readily supplied with the temperature coefficients [2]. These compact models could be used to simulate macroscopic inter-die process variations by providing the corner case models in term of process, voltage and temperature variations. On the other hand, mismatch model is actually the extended version of the standard compact model in order to predict the microscopic intra-die process variations. A lot of literatures presented the mismatch model development for circuit simulation, but most of them are only concentrated on the electrical and process parameter variations.

It has been recognized that MOSFET mismatch is a function of gate area as given by Pelgrom’s model for long channel transistors [3]. Mismatch coefficients related to the threshold voltage and current factor parameters are presented to be inversely proportional to the transistor area. A mismatch model with SPICE implementation was first

developed by Michael et al, in [4]. This model based on BSIM1 model which considers the variance of 17 parameters with their correlation to the statistical algorithm such as principle component analysis (PCA) and sigma-space analysis. The advancement of CMOS process in fabricating small geometry devices has encourages the model development considering the short channel effects. The earlier works was extended by Lovett et al to include the term effective channel length and width for mismatch transistor in submicron device [5]. It has been observed that the measurement data would not scattered on the straight line slope of the inverse square root of active area plot for submicron process and below. Beside that, mismatch model based on physical process parameter presented by Drennan instead of typically electrical parameter basis [6].

A common feature in the previously presented models is the consideration of mismatch analysis in term of electrical and process variations. Some literatures show that there is only slight effect of temperature variations in term of the device mismatch itself [6], but there are also reports suggested that the mismatch temperature analysis is actually significant in circuit design [7]. Temperature changes would give the impact on the transconductance variations especially for low supply voltage designs. This make the modeling of mismatch effect corresponds to temperature variations is essential to provide an accurate input to the circuit designers. Mismatch model without the related temperature coefficients will leads to unnecessarily over size design or even wrong design optimizations.

In this paper, we propose a MOSFET mismatch model suitable for Monte Carlo circuit simulation at different temperatures. The proposed model improves the random mismatch prediction by considering the device parameters that are sensitive to the temperature changes. The rest of the paper is organized as follows. In Section 2, the development of MOSFET mismatch model with the inclusion of mismatch temperature coefficients is explained. Section 3 describes the experiment part while the measured versus simulated results are presented in Section 4. Section 5 concludes the paper.

2. Mismatch Model Development Pelgrom’s model is used as a reference in the

development of the proposed mismatch model. The model defines MOSFET mismatch as a function of transistor’s gate area given by

LW

AV TV

T

(1)

for threshold voltage variations, where ΔVT is the Vth difference between two identical transistors while AVT is

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threshold voltage mismatch coefficient [3]. Let P is the model parameter with added mismatch, we simplified the model for mismatch given by

P = P0 + Pmm (2)

where P0 is model parameter without mismatch and Pmm is the actual mismatch value of model parameter. Mismatch parameters are assumed to be scattered as Gaussian distribution so that the statistical data is in predictable manner where mean (μ) and standard deviation (σ) values could be generated. Beside that, the mean value is assumed to be as small as possible to make sure that only the random mismatch effect is analyzed rather than systematic mismatch. For those reasons, only standard deviation value is used in the mismatch model equation for circuit simulation. Considering (1) in relating the area dependence with mismatch, we presented the equations used for the mismatch formulation in SPICE circuit as follows

Pmm = agauss(0, σ( par ),3) (3)

kparlLkparwW

kpar)par(

(4)

where σ(par) is the standard deviation of mismatch distribution, kpar is the basic mismatch factor of the model parameter while kparw and kparl are the mismatch dependence on width and length respectively. The term agauss in (3) represents the use of absolute variation in SPICE Gaussian distribution function while the variables in brackets are respectively for mean value, absolute variation value and sigma level. Parameters kparw and kparl are important in describing the matching performance related to the effective channel width and length respectively especially for deep submicron technologies.

Modeling the effect of temperature changes on process variability requires the understanding of transistor’s electrical parameters correlation with temperature value. Temperature dependence of critical parameters such as threshold voltage (Vth) and mobility (μ) are given by

Vth(T) = Vth(T0) – κ(T – T0) (5) μ(T) = μ(T0)(T/T0)

-m (6)

where T is temperature, T0 is room temperature, κ is threshold voltage temperature coefficient and m is mobility temperature coefficient [8]. Mobility parameter is important because it has a strong correlation with the drain current parameter as given by general drain current equation. Based on (5) and (6), it can be concluded that threshold voltage and drain current have a negative dependence on temperature changes. On the other word, the performance of both parameters degraded as the temperatures increased.

The objective of this paper is to come out with a complete set of mismatch model parameters that is suitable for actual circuit simulations with respect to temperature effect. The key idea in this mismatch model development is by

accurately performed the temperature model parameter extraction from the normal device and followed with the extraction of mismatch temperature coefficients for the mismatch device. In order to generate the temperature coefficient for normal and mismatch devices, they need to be measured at room and different temperatures. Figure 1 shows the simplified flow diagram of mismatch modeling with temperature variations.

The flow starts with the requirement of having a few good wafers which normally passed the standard PCM test with more than 90% yield for the measurement. Compact model that is conducive to simulation environment such as BSIM3v3 is required in this work. Typical BSIM3v3 model parameters are extracted from the measured I-V and C-V curves. Beside its acceptability as the first industry standard model, physical based BSIM3v3 model also contains the parameters related to temperature changes which are critical for inter-die process variations [2].

Figure 1: Flow diagram of mismatch modeling with temperature variations

From the generation of typical compact model, the flow continues with generation of mismatch model that is suitable for Monte Carlo simulation. In order to extract enhanced BSIM3v3 model with mismatch effects, the mean and standard deviation values are derived from the parametric mismatch measurement data. BSIM3v3 parameters such as

Silicon wafer

Measurement at room T

Measurement at different T

Typical compact model

Enhanced model with mismatch

Model with temperature coefficients

Mismatch temperature coefficients

Yes

No

Model released

Good agreement?

VTH0 and U0 respectively for threshold voltage and drain current mismatches are applied into (2), (3) and (4). Beside that physical phenomenon parameters such as DIBL effect and subthreshold swing parameters could also be used to improve the mismatch prediction in subthreshold regime. Mismatch model at room temperature is verified by the small discrepancy between mismatch measurement and Monte Carlo simulation results.

After the measurement and modeling for single and pair devices at room temperature are done, the next step is the device measurement at different temperatures such as at 75 and 125 °C. The temperature coefficients for BSIM3v3 model are extracted from I-V curves measurement at different temperatures. In order to accurately model the mismatch dependence on temperature changes, the linear temperature coefficient is incorporated into the mismatch equation given as follows

σΔP(T) = σΔP(Tref) + TCM(T – Tref) (7)

where σΔP is similar to σ(par) in (4) and T is the temperature value used for simulation. Room temperature is used as a reference temperature or Tref while TCM is the linear temperature coefficient for mismatch effect. Considering (5) and (6), TCM related to threshold voltage and carrier mobility parameters are used in the proposed mismatch model.

3. Experiment The wafers used in this work were fabricated using 0.35

um technology of analog mixed signal CMOS process from MIMOS Wafer Fab. In addition to the standard transistor layout, special test structures that could minimize the systematic gradient effects across the wafer are used for the mismatch measurement. The layout contains two separated drain nodes with common gate, source and bulk. The transistor pairs were placed side-by-side within the range of 10 um distance. Matched transistors were laid-out in the same direction to cancel the effect of photolithographic misalignment which is the main contribution of the gradient effects. The symmetrical structures also contain dummy poly line connected to ground which would reduced the etch rate variations.

Electrical parameters such as threshold voltage (Vth), saturation current (Idsat) and subthreshold leakage current (Ioff) are measured from the provided matched transistor’s structures. In addition to typically room temperature measurement, those electrical parameters are also measured at different temperatures namely 75 and 125 °C. The measurements are performed on NMOS device using Agilent 4073UX parametric test system. In order to remove the instrument error induced by the test system, we have used special measurement technique by applying 5 SMUs measurement simultaneously. There are 10 different combinations of the transistor’s channel length and width involved to analyze the mismatch dependence on gate area. Four wafers from two lots are used during the measurement where each wafer consists of 130 sites. Statistical data screening is done to select only the reliable samples where

outliers are removed by restricting the huge measurement data within the control limit of five-sigma (5-σ).

0.0

2.0

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0 0.2 0.4 0.6 0.8 1 1.2 1.4

1/sqrt(Area) [1/um]

Std

dev

of

del

ta V

th

[m

V]

Measured

This work

Figure 2: Mismatch model vs. measured data for Vth

0

0.4

0.8

1.2

1.6

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0 0.2 0.4 0.6 0.8 1 1.2 1.4

1/sqrt(Area) [1/um]

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dev

of

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ta I

dsat

[

%]

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Figure 3: Mismatch model vs. measured data for Idsat

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[

%]

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Figure 4: Mismatch model vs. measured data for Ioff

4. Result and Discussion We used the output from HSPICE simulation and

compared with measurement data for the mismatch model verification. The simulated data are obtained by running a Monte Carlo simulation 520 times with respect to the actual number of measured mismatch data. Pelgrom’s plot that presents the mismatch dependence on gate area is used for

the verification at room temperature device. Figure 2, Figure 3 and Figure 4 show the comparison between measured and simulated data respectively for Vth, Idsat and Ioff. Those figures demonstrate that the accuracy of the extracted mismatch model is supported by the close value between measured and simulated mismatch data.

The comparison between Gaussian distribution plots of measured and simulated mismatch data at different temperatures for Vth from transistor with L=0.35 um and W=10 um are shown in Figure 5.

(a)

(b)

(c)

Figure 5: Measured vs. simulated data of Vth mismatch at different temperatures for short device; (a) T=27 °C, (b) T=75 °C and (c) T=125 °C

The plots show that there is a good agreement between measured and simulated data where the errors between them are generally less than 10%. Figure 5 also shows that there is a small reduction of Vth mismatch standard deviation value from low to high temperatures. This is to suggest that there are some slight improvements of mismatch effects as the device temperature increases. The small difference for mismatch dependence on temperature changes leads to the difficulties in analyzing it in normal Pelgrom’s plot. Therefore mismatch parameters are plotted as a function of device channel length (L) for W=10 um in order to clearly

capture the temperature effects as shown in Figure 6, Figure 7 and Figure 8 correspondingly for Vth, Idsat and Ioff. The results show closely fitting between simulated to measured data to suggest that the mismatch temperature coefficients could cater various dimensions used in the designed layout. It is also observed that short device would produces more improvement of mismatch value as the temperature ramped up compared to large device.

0

1

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0 2 4 6 8 10 12

Channel length, L [um]

Std

dev

of

del

ta V

th

[m

V]

Meas 27Meas 75Meas 125Simu 25Simu 75Simu 125

Figure 6: Simulated vs. measured data at different T for Vth mismatch

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dsa

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%]

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Figure 7: Simulated vs. measured data at different T for Idsat mismatch

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Channel length, L [um]

Std

dev

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ta I

off

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]

Meas 27Meas 75Meas 125Simu 25Simu 75Simu 125

Figure 8: Simulated vs. measured data at different T for Ioff mismatch

In order to capture the significance of the extracted temperature mismatch coefficients in circuit analysis we need to apply the model into the circuit design example and try to predict related yield. Figure 9 shows the circuit diagram for CMOS differential amplifier with 5 transistors involved where random input offset voltage (Vos) can be used to examine the mismatch effects on the circuit. By only considered the identical NMOS transistors of M1 and M2 that formed the differential pair block, the random Vos is simulated by performing Monte Carlo statistical simulations. Any deviations between the transistor pair will produce different Vos parameters thus affected other design specifications. The simulation results from 1000 Monte Carlo runs for Vos at room and different temperatures are shown in Figure 10 where the numbers of sample (N) are plotted versus the Vos values.

Figure 9: CMOS differential amplifier

Figure 10(a) plots the simulated result at room temperature where random Vos value is about 4.9 mV for 1-σ. From the distribution plot at room temperature we would predict that 68.3% of Vos are within -9.1 mV to 0.7 mV range while 95.5% of Vos are within -18.9 mV to 10.5 mV range. From the device mismatch modeling and analysis at different temperatures, we would expect that Vos parameter will reduce with the temperature increases. Figure 10(b) is the simulated data at 125 °C for mismatch model without the temperature coefficients while Figure 10(c) shows the simulated data using the presented model. It is clearly observed that the model without temperature coefficients is unable to accurately predict the mismatch effect at high temperature. The standard deviation value of Figure 10(b) is higher than Figure 10(a) which is against our expectation. On the other hand, the presented mismatch model is able to characterize the small reduction of the mismatch values. The availability of mismatch model suitable for circuit simulation at any temperature conditions would give the additional solution to the circuit designers for faster and more accurate analysis of speed-power-accuracy trade-off rather than traditionally hand-calculation analysis.

(a)

(b)

(c)

Figure 10: Simulated Vos results at different temperatures; (a) T=27 °C, (b) T=125 °C without temperature model and (c) T=125 °C with temperature model

5. Conclusion In this paper, we presented a MOSFET mismatch model

to accurately predict the mismatch dependence on temperature variations. This work considers the threshold voltage and carrier mobility parameters in developing linear temperature mismatch coefficients that are vital for the circuit simulation at different temperatures. Favorably good agreement between mismatch measurement and Monte Carlo simulation results verified the accuracy of the presented model. The circuit design application demonstrated that mismatch model without the temperature coefficients would leads to wrong circuit simulation thus affect the design yield.

6. References [1] R. Heald and P. Wang, “Variability in Sub-100nm

SRAM Design”, Proc. of the IEEE International Conference on Computer Aided Design, ICCAD 2004, 7-11 November 2004, pp. 347-352.

[2] C. Hu and Y. Cheng, MOSFET Modeling and BSIM3 User’s Guide, Springer, Massachusetts, 1999.

[3] M. J. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors”,

IEEE J. Solid-State Circuits, Vol. 24, No. 5, Oct. 1989, pp. 1433-1440.

[4] C. Michael and M. Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits”, IEEE J. Solid-State Circuits, Vol. 27, No. 2, Feb. 1992, pp. 154-166.

[5] S. J. Lovett, M. Welten, A. Mathewson and B. Mason, “Optimizing MOS Transistor Mismatch”, IEEE J. Solid-State Circuits, Vol. 33, No. 1, Jan. 1998, pp. 147-150.

[6] P. G. Drennan, “Integrated Circuit Device Mismatch Modeling and Characterization for Analog Circuit”, Ph. D. Dissertation, Arizona State University, May 1999.

[7] Y. Lu and R. H. Yao, “Low-voltage Constant-gm rail-to-rail CMOS Operational Amplifier Input Stage”, J. Solid-State Electronics, Vol. 52, No. 6, June 2008, pp. 957-961.

[8] A. Bellaouar, A. Fridi, M. I. Elmasry and K. Itoh, “Supply Voltage Scaling for Temperature Insensitive CMOS Circuit Operation”, IEEE Trans. on Circuits and Systems, Vol. 45, No. 3, March 1998, pp. 415-417.