Abstract— A simple 4 quadrant analog multiplier using bulk

NMOS transistors is presented in the paper. All the NMOS transistors in the circuit operate in saturation region. The complete circuit contains only 4 NMOS transistors as active devices. The proposed circuit has very good linearity, low THD, large input range and bandwidth. The input dynamic range of the circuit is ±VDD. The THD in the output waveform is smaller than 0.3% when the inputs are sine waves of peak-to-peak voltage 2.VDD. When input sine waves are of peak-to-peak voltage VDD, the THD is less than 0.14%. The 3dB bandwidth of the circuit is over 600MHz. The circuit also has good noise performance compared to other similar works, due to less number of devices used. Quiescent Power consumption of the overall circuit is only 214μWatts.

Index Terms—Analog Multiplier, Four Quadrant

I. INTRODUCTION

The analog multiplier circuit is a very useful building block and can be applied to any analog signal processing circuits like filters, frequency doublers, modulators etc. It is thus increasingly important to have such circuits at low power and low voltages. However, in the process of scaling down transistors to reduce power and voltage, the devices become increasingly susceptible to nonlinear effects[1],[2], thus greatly limiting their input range. Multipliers have been built around various topologies using Bipolar, CMOS[3],[4] and Bi-CMOS [5],[6] based circuits.

This paper proposes a 4-quadrant voltage mode analog multiplier based on the famous quarter square algebraic identity[7]. To improve the input dynamic range, THD and linearity, a simple technique is used at the input. This is nothing but a capacitive divider based voltage adder/scaling circuit. The circuit requires the input voltages in both true form and inverted form. i.e. V1,V2 and -V1,-V2 , where V1 and V2 are the inputs to be multiplied.

Manuscript received on January 14, 2008. The author is presently working

in AMD India Design center as a design engineer. The author has done his masters in Electronics from REC(NIT) Calicut in the year 2003-2005. This work is purely a personal work of the author and the author has not used any AMD resources for the simulation and preparation of the paper.

II. QUARTER SQUARE ALGEBRAIC IDENTITY

The Quarter-Square algebraic identity [7] is a commonly used method for a multiplier implementation. This can be expressed in three steps.

1.Take the sum and difference of the two inputs. 2.Take the square of both the sum and the difference

obtained in step 1. 3.Find the difference between the squares in step2.

Thus the output can be expressed as Vout = [(V1+V2)2 – (V1-V2)2] = 4.V1.V2 (1)

III. PRINCIPLES OF OPERATION

A. Capacitive divider based adder and subtractor The circuit shown in Fig.1 is the one I have used in this

paper. The circuit is basically an adder circuit which gives the output equal to (V1+V2)/6. This is easily obtained using the superposition theorem.

All voltages indicated are with respect to the ground. The output voltage is the scaled sum of the inputs V1 and V2. In the complete multiplier circuit proposed, the Vo in the adder circuit mentioned is given directly to the gate of one of the NMOS devices.

In Fig.1 the value of C is to be chosen such that the loading due to the gate capacitance of NMOS is minimal. In the proposed multiplier circuit, the dimensions of all of the MOS transistors are W=2μm, L=1μm and the process technology used is 0.25 micron. The reason for choosing a comparatively large value for W and L with respect to the minimum feature size of the technology is to get better matching between the devices. In the saturation region, the gate capacitance of each NMOS is calculated to be around 13fF. So I have chosen C=130fF, 10 times the gate capacitance Cg.

The reason behind choosing a capacitor divider is the simple fact that, in CMOS process, getting matching capacitive ratios with high degree of accuracy is easier than getting the same with resistive dividers. Also the variations of capacitor ratios with temperature variations are negligible. [8],[9].

One potential issue with the capacitive divider is the initialization of the Vo node. There should be some start up

A Simple 4 Quadrant NMOS Analog Multiplier with input range equal to ±VDD and very low

THD Soman Purushothaman, Design Engineer II, AMD India Design Center

Email: somswyd@yahoo.com

134978-1-4244-2030-8/08/$25.00 ©2008 IEEE.

circuit for initialization of Vo node of each of the capacitive dividers to ground potential to ensure that all NMOS are in saturation in the specified input voltage range.

B. The Multiplier Core In the circuit shown in Fig.2, Vx = (V1 - V2)/6 and

Vy=(V1 + V2)/6. These are generated using the capacitive divider/adder circuit explained in section III A (Fig.1). The scaling factor of 1/6 is used to ensure that the Vgs of all of the NMOS transistors never goes below the threshold voltage VTHN. This coupled with the selection of R1 and R2 ensures that all the MOS transistors will always be in the saturation region when the input voltages are in the range ±1V. This is the main reason for achieving large input range (100% of the supply voltage), linearity and very low THD for the overall circuit. The non-linear terms gets cancelled by the matching M1-M2 and M3-M4 pairs.

From Fig.3 Id1 = (1/2).μn.Cox .(W/L)1[Vgs1 – VTHN ]2 (2) Id2 = (1/2).μn.Cox .(W/L)2[Vgs2 – VTHN ]2 Id3 = (1/2).μn.Cox .(W/L)3[Vgs3 – VTHN ]2 Id4 = (1/2).μn.Cox .(W/L)4[Vgs4 – VTHN ]2

Where, Vgs1 = Vx - VSS ; Vgs2= -Vx - VSS (3)

Vgs3 = Vy – VSS ; Vgs4= -Vy – VSS

As the change in Vds of all NMOS transistors are less, the channel length modulation effect is neglected.

Now, the expression for Vout can be written as

Vout = [VDD – (Id1 + Id2).R1 ] – [VDD – (Id3 + Id4)R2] (4)

By using the set of equations (2)-(4) and taking the W/L ratios of all transistors as equal and setting R1=R2=R, Vout = 2.(1/2).μn.Cox .(W/L).R. [(Vy)

2 - (Vx)2 )] (5)

From Fig.1 , equations for Vx , -Vx , Vy and –Vy can be written as,

Vx = (V1 – V2 )/6 Vy = (V1 + V2 )/6

Then Vout = R.(1/9).( μn.Cox .(W/L) ) V1.V2 (6)

The values of R1=R2=R can be designed based on the

following equation, considering ⏐V1(max) ⏐ and ⏐V2(max) ⏐ are equal to 1V. VDD–R.{(1/2).μn.Cox.(W/L)1[Vgs1–VTHN]2 + (1/2).μn.Cox.(W/L)2[Vgs2 – VTHN ]2 } > { (2/6) - VTHN }

(7) Where,

Vgs1 = (2/6) +1 and Vgs2 = -(2/6)+1

IV. THE COMPLETE MULTIPLIER CIRCUIT

The complete circuit of the proposed analog multiplier is shown in Fig. 3. It is nothing but the multiplier core combined with a set of capacitive dividers/adders shown in Fig. 1, with the inputs applied properly. The input signals to the circuit should be in both in normal and inverted form. That is V1, V2, -V1, -V2.

V. NONLINEARITY EFECTS

The multiplication function results from the assumption

of a perfect square-law MOS characteristic and fully matched devices. Any variation from this condition will produce harmonic components in the output response. Linearity error results from mobility reduction, channel-length modulation etc. The body bias effect is absent here as the bulk of all the MOS transistors are connected to the sources, i.e. VSS.

The accuracy of the output also depends on the matching of the passive components. Matching of the R and C values depends on the quality of the process used.

VI. SIMULATION RESULTS

The proposed multiplier circuit of Fig.3 has been

simulated with SPICE using the IBM 0.25-micron CMOS process with VTHN = 0.588V. The W/L ratios of the 4 MOSFETs M1-M4 are equal to 2μ/1μ. The values of resistors R1 and R2 are designed based on equation (7), and are equal to 12Kohms. The value of the gate capacitance of each of the MOSFETs is estimated to be around 13fF. So in the capacitive divider, the value of C is chosen as 130fF, to minimize the loading. That is C1= C2 = C5 = C6 = C9 = C10 = C13 = C14 =130fF and C3 = C4 = C7 = C8 = C11 = C12 = C15 =C16 = 260fF. The supply voltage used is VDD = +1V and VSS = -1V.

The DC transfer-characteristics of the circuit with V1 and V2 as the two inputs are shown in Fig 4. In the simulation netlist the node number associated with the Vout are 15(+) and 16(-). The Vout = V15 – V16 swings between –335mV and +335mV for the input range of ±1V. In the simulation, V2 is varied from –1V to 1V with a 0.2V step.

The Quiescent Power consumption of the overall circuit is only 214μWatts.

Fig. 5 shows the frequency response of the circuit when it is used as a frequency doubler. The simulation is done with a sine wave of 1V peak value given as both V1 and V2 to the circuit. The 3dB bandwidth is about 600MHz. Note that the Bandwidth could have been increased if smaller W and L values had been chosen.

Fig.6 shows the simulated output spectrum of the multiplier circuit in frequency doubler configuration (V1=V2=Vin) with a 1V peak sine wave of 1MHz frequency given as the input signal. The output component at 2MHz is having the highest magnitude as expected. The harmonic frequency components are at least 3 orders of magnitude less than the fundamental. The spectrum is prepared from the Fourier analysis [11] using the SPICE.

Fig.7 shows the variation of THD (%) of the output waveform with different V1 and V2 values. The simulation is

135

done at 1MHz. The Total Harmonic Distortion (THD) is obtained from a Fourier analysis of the transient response of a single tone sinusoid input [11].

The output noise is plotted in Fig. 8 with input frequency varying from 100Hz to about 1GHz. The Y-axis is in Volts/√Hz. For frequencies above 2KHz, output noise is less than 2 micro Volts/√Hz. The circuit has excellent noise performance and can be attributed to the very less count of devices used in the circuit, compared to other similar works. The simulation is done with the input sine wave value of 1V (peak) in the frequency doubler configuration of the circuit.

Fig. 9 shows an application of the multiplier as an amplitude modulator. The simulation is performed with 1V peak sinusoidal inputs, V1 at 10 MHz and V2 at 500KHz.

Table 1 COMPARISON OF THIS WORK WITH PREVIOUS WORKS

Fig. 1. Capacitive divider based adder circuit.

VII. CONCLUSION

A simple 4 quadrant analog multiplier using the Quarter-Square algebraic identity and capacitive voltage adders/dividers is presented here. Use of the capacitive voltage adder/dividers resulted in getting a very low THD and 100% input dynamic range. The use of capacitive adders/dividers greatly reduces mismatch effects also, as getting precise capacitive ratios is easier in CMOS manufacturing processes.

With a power supply of ±1V, the output THD is less than 0.3% with inputs being a 1MHz sine wave of 2 volts peak-to-peak amplitude. The bandwidth of the circuit is remarkably large compared to many previous works. Table 1 summarizes a comparison of this work with similar prior work on four-quadrant multipliers.

Fig. 2. The multiplier core.

Factor This work Ref 12 Ref 13 Ref 14 Ref 15 Ref 16 Ref 17 Ref 18 Supply ±1V +1.5V ±1.5V +1.5V +1.2V ±2.5V +1.8V +1.5V

I/p Range ±1V (100%) ±400mV

±1.5V ±400mV ±250mV ±1V ±400mV

±400mV

THD % at 1MHz input

≤ 0.3

≤ 1.0

≤ 0.7

≤ 0.25

≤ 1.1

0.85

≤ 1 at

25KHz

0.8 at 100KHz and

Vin=0.4V(p-p) Bandwidth 600MHz 95MHz 194MHz 34MHz 2.2MHz 120MHz 10MHz 1000MHz

Power 214μW

46.4μW Not Available

Not Available

2.76mW 3.6mW 200μW 45μW

Resistors 2 2 2 2 6 - 2 -

C1=C

C2=C C3=2C

C4=2C

V1

V2 Vo = (V1 + V2)/6 Vx -Vx

R1

-Vy

R2

Vy

+ Vout -

VSS

M1 M2 M3 M4

VDD

136

Fig. 3. The complete multiplier circuit.

Fig. 4. DC Transfer characteristics.

Fig. 5. Frequency response of the circuit.

V1

V2 -V2

-V1

Vy -Vy

R2

-Vx

R1

Vx

- Vout +

VDD

VSS

M3 M4 M1 M2

C1

C2 C3

C4

C5

C6 C7

C9

C8

C10 C11

C13

C12

C14 C15

C16

137

Fig. 6. Simulated output spectrum of the multiplier in frequency doubler configuration of the circuit.

Fig. 7. Variation of output THD (%) with different V1 and V2 values.

Fig. 8. Output noise voltage.

Fig. 9. Amplitude modulated waveform generated using the multiplier.

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