WAFER LEVEL ENCAPSULATION TECHNOLOGY FOR MEMS DEVICES USING AN HF-PERMEABLE PECVD SIOC CAPPING LAYER

G.J.A.M. Verheijden1, G.E.J. Koops1, K.L. Phan2 and J.T.M. van Beek2 1NXP-TSMC Research Center, Leuven, Belgium

2NXP-TSMC Research Center, Eindhoven, The Netherlands

ABSTRACT In this paper, a novel technology for the

encapsulation of MEMS devices using a porous capping material is presented. The capping material consists of a low temperature PECVD layer of SiOC and is shown to be permeable to HF-vapor and H2O and therefore allows for removal of a SiO2 sacrificial layer. Furthermore, it is demonstrated that a cavity defined underneath the capping layer can be evacuated to allow for high-Q operation of a MEMS resonator. Finally, it is shown that a sealing layer can be deposited on top of the capping layer without contaminating the cavity. 1. INTRODUCTION

Current state-of-the-art MEMS packaging technology makes use of a discrete cap or cap-wafer that is placed over the MEMS device [1]. These wafer-to-wafer or chip-to-wafer processes are expensive and result in a MEMS package that is often much more bulky than the MEMS device itself. An alternative method for the encapsulation of MEMS devices is to make use of thin films that are deposited and etched on a wafer level. A micro-cavity is created around the MEMS device using surface micro-machining. Ideally, this process should also be compatible to back-end processing of mainstream CMOS, thereby allowing for the integration of driver and readout electronics. One of the most critical process steps for the fabrication of the cavity is the sealing of the release holes by a capping layer without contaminating the cavity. This critical step can be avoided if a layer is used which is permeable to the sacrificial etchant, but impermeable to the material that constitutes the sealing layer. These requirements are met using a porous capping layer. However, porous layers that have been used so far have several disadvantages like high deposition temperatures or a high electrical conductivity [2-4]. We propose to use the low-k material BD (Black-Diamond®) from Applied Materials™ as permeable layer. This material is porous as deposited, uses BEOL compatible process temperatures and, moreover, is an insulator 2. EXPERIMENTAL Concept process route

Figure 1 shows the concept process route. The capping route starts with the completion of the surface-micro machined device with a sacrificial spacer layer (SiO2) remaining on the wafer. Additional the sacrificial layer (SiO2) is deposited and patterned in such a way that only SiO2 is present where the cavities have to be created. This step is followed by the deposition of the supporting

cap layer to avoid collapsing of larger cavities. In this shell, release holes (etching channels) are patterned, followed by a deposition of a BD-layer for pre-sealing the cavity. Through the BD-layer the sacrificial SiO2 layer is removed by vapor-HF, releasing the mechanical micro structures. As a last step the release channels are sealed by the deposition of a hermetic seal-layer.

Figure 1: Schematic drawing of the process route for encapsulating a MEMS device using a permeable BD layer. a) The completion of the surface-micro machined device (resonator); b) A sacrificial layer is deposited and patterned; c) The packaging cap (support) layer is deposited for the formation of the encapsulation shell and the release holes are patterned; d) Deposition of the permeable (BD) layer; e) Removal of the sacrificial layer (through the releasing holes) to release the mechanical micro structures; f) The etching release holes are sealed by a seal-layer

(a)

(b)

(c)

(d)

(e)

(f) SiliconOxide Supporting-layer

BD (Porous layer) Hermetic seal-layer

978-1-4244-1793-3/08/$25.00 ©2008 IEEE MEMS 2008, Tucson, AZ, USA, January 13-17, 2008798

Black Diamond For the integration of MEMS devices with a

standard CMOS flow, a packaging technology compatible with the back-end of line (BEOL) processing is preferred. Introduction of a cap before the BEOL processes would result in unacceptable step-height variations over the devices, prohibiting the use of advanced lithography. A limiting factor for BEOL processes is the temperature budget. No processes can be tolerated that use temperatures above ~400°C. This limits severely the choice of capping and sealing materials. A further advantage of low-temperature processing is that materials with good electrical conductivity but low melting temperatures, such as aluminum and gold, can be encapsulated. This is especially beneficial when the use of BD is applied to the encapsulation of MEMS switches.

In state of the art BEOL processes, porous low-k materials are used to decrease the RC-delay between the metal lines. One of these low-k materials is Black Diamond® (BD) from Applied Materials™. BD is a PECVD SiOC material deposited at a temperature of 350°C and has a porosity of 7%. This low deposition temperature has the advantage that it allows the integration of the capping process on standard CMOS wafers after the complete CMOS processing. Another advantage of BD is that it is an insulator, which helps to keep the parasitic capacitance between the MEMS device and cap layer low. This parasitic capacitance can have a serious detrimental effect on the performance of MEMS devices. Moreover, the etch selectivity of BD over SiO2 in HF-Vapor is very high which allows long sacrificial etch times.

Permeability of BD for HF-Vapor Figure 2 shows the pore size distribution over the volume of porosity (dV/dR) of BD measured by ellipsometric porosimetry measurement. The principle feature of this method is its utilization of the change of the optical characteristics of the porous film during vapor adsorption and desorption to determine the mass of adsorptive condensed/adsorbed in pores [5]. The plotted curve is the desorption-curve of toluene (C6H5CH3). This plot shows that most of the pores in BD are larger than the diameter of HF and water (2.8 Å and smaller). Moreover the diameter of C6H5CH3 (6 Å) is larger than HF and H2O, so if any absorption is measured this means that both HF and H2O also can be transported through BD and will be able to remove (etch) the underlying oxide. Figure 3 shows a cross-section SEM picture of a release hole pre-sealed with a BD layer, after releasing the cavity with HF-vapor. This shows that the BD has a sufficient porosity for removing the sacrificial SiO2 with HF-vapor.

Figure 2: The pore size distribution of BD measured by Ellipsometric Porosimetry measurement. The plotted curve is the desorption-curve

Figure 3: Cross-section SEM picture of a release hole with a pre-seal BD layer after releasing the cavity with HF-vapor.

0

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Pore Radius (nm)

Film thickness = 375 nm Refractive index = 1.4143

Porosity = 7%

dV/d

R

Oxide

BD

Air HF-vapor

799

Selectivity of BD towards HF-vapor For testing the selectivity of BD towards HF-

vapor a sample is prepared with a cavity and a 100nm thick BD-layer as pre-seal. This sample is etched in HF-vapor for 280 minutes at 35°C. This is enough for releasing a resonator that needs an under-etch of approximately 5µm. Figure 4 shows on the left side a cross-section SEM picture of the release hole before the release etch. It can be seen that the BD layer at the bottom has a thickness of only ~40nm. On the right side, a tilted cross-section SEM picture of a release hole after a vapor-HF release etch of 280 minutes, it can be seen that there is still BD left on the bottom of the release hole. This means that the etch rate of BD in vapor-HF is much less than 0.14 nm/min. For thermal oxide the etch rate for the same conditions is ~15 nm/min.

Figure 4: (a) A cross-section SEM picture of a release hole with a 100nm thick pre-seal BD layer before release etch. (b) A tilted cross-sectional SEM picture of a release hole with a 100nm thick pre-seal BD after an vapor-HF release etch of 280 minutes. Impermeability of BD

After pre-sealing the cavity with a BD layer and etching the sacrificial oxide, the porous BD layer has to be capped with a sealing layer in order to create a hermetic seal to protect the MEMS devices from environmental impurities. During this process it is of paramount importance that the interior of the cavity and the MEMS device itself remain clean and no extra impurities are being introduced by this sealing process. Figure 5 shows a cross-section SEM picture of a pre-sealed release hole with BD after the release etch and the deposition of the seal-layer. No contamination inside the cavity can be seen. This means that it is possible to make release etch-channels directly above the device structure. This can significantly decrease the release etch time compared to processes where the release holes are located far from the device structure to avoid contamination of the MEMS device.

Figure 5:Cross-section SEM picture of a release hole with a pre-seal BD layer after releasing the cavity and depositing a seal layer Reducing the pressure inside the cavity In most MEMS applications the Q-factor determines to a large extend the device performance. For example, in MEMS oscillators, the Q-factor of the resonator needs to be as large as possible in order to have a low phase noise The Q-factor is limited by loss mechanisms leading to energy leakage from the resonator to the outside world. Normally, several loss mechanisms, such anchor loss, material loss, and air damping loss play a role and the Q-factor can be written as in equation 1, where Estored=Ekinetic+ Espring is the energy stored in the resonator and the terms in the denominator are the different loss contributions per periodic cycle.

...+++=

airmaterialanchor

stored

EEEEQ (1)

In practice, the Q-factor of a MEMS resonator is limited by air damping at atmospheric pressures. As a consequence, the Q-factor can be increased by decreasing the ambient pressure. This is the case until the pressure becomes so low that other loss mechanisms become dominant over Eair. So it is important that the cavity can be evacuated before the cavity is sealed.

The frequency response and quality factor of a pre-sealed resonator as a function of pressure is measured. The resonator itself is depicted in Figure 6. This resonator is mechanically exited by a DC bias voltage and a small AC voltage. The movement of the resonator causes a change in mechanical strain leading to a change of resistance of the resonator arms induced by the piezo-resistive effect. The change in resistance results in an ac current ires when the resonator is biased with a dc current Ibias [6].

BD

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oxide air air

Support layer

BDSeal layer

No impurities deposited inside

the cavity

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Figure 6: Top View SEM picture of the measured piezo-resistive resonator.

Figure 7 shows the resonator's admittance, Ym as a function of frequency and the extracted quality factor of this resonator in a pre-sealed cavity (after step E in figure 1) at atmospheric pressure and in a vacuum chamber at 6mTorr.

Figure 7: Frequency responses and quality factors of a resonator in a pre-sealed cavity (after step E in figure 1) at atmosphere and in a vacuum chamber at 6 mTorr We see a clear increase in Q-factor at lower pressures due to the lowering of the air-damping. Moreover, it shows that decreasing the ambient pressure causes a drop in the resonance frequency. This decrease of the resonance frequency is caused by the piezo-resistive measuring current, which slightly heats the device. At lower pressures the thermal conductivity of the resonator with the out-side world decreases causing an increase in resonator temperature (Pirani-effect). Since an increase in temperature lowers the Young’s modulus YSi of Si

according to equation 2, the resonance frequency is also lowered [7].

CTTYSi °=∆×−×= − 30)105.671(106.165 69 (2) Both the increase in Q-factor and the decrease in frequency when lowering the pressure show that our fabricated pre-sealed cavity can be evacuated by pumping the gases present in the cavity through the BD layer. 3. CONCLUSIONS

In this paper we have shown a wafer-level encapsulation technique that uses an HF-permeable BD-layer deposited at low temperatures. It is shown that BD has enough porosity for the HF and H2O to fully etch the sacrifial oxide. Moreover the etch-rate of BD itself in HF-vapor is very low, less than 0.14nm/min. This BD layer is used as an intermediate layer between the sealing layer and the sacrificial layer. The sealing layer can therefore be deposited on top of the BD layer without introducing residues inside the cavity or on top of the MEMS device. By measuring the Q-factor and Pirani-effect of a capped resonator as a function of pressure, we have shown that the pre-sealed cavity can be evacuated to low operating pressures

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