Study on Board Level Drop Reliability of Wafer Level Chip Scale Packagewith Leadfree Solder

Zhang Xueren', Zhu Wenhui, Poh Edith and Tan Hien BoonPackaging Analysis & Design Center, United Test and Assembly Center, Ltd.

5 Serangoon North Ave 5, Singapore 554916'Corresponding author: xr_zhanggsg.utacgroup.com, DID: (65) 65511465

Abstract However, its board level reliability is a great concern after

Wafer level chip scale package (WLCSP) is a promisin board assembly for real application '4]. Unlike FBGA with a

p BT substrate as interposer, WLCSP i.e. silicon chip directlypackaging technology to accommodate the demand for small, asebe nPBbad ne eprtr aitoportable handheld electronic. This bare-die bumped package is assemb ledo PCr or. Under .teer viaion.. ..... (~~~~thermal cycle) large GTE mismatch between silicon andable to offer significant area savings, improve package .y '.able to offer significant area savings, improve packae rPCB material will cause cracks in solder interconnection.electrical parasitics and power dissipation performance oversubstrate-based BGA packages. However, its board level eWhile under mechanical or dynamic loadng e.g. drop impactreiailt eseial mehnia performance undershoc usually seen in handheld electronics, difference of stiffnessreimaciityispagrecatlyconcrnfhandheld lectrfor nics

undersbetween silicon and PCB will also lead to cracking in solderinterconnection. This is one of the reasons that WLCSPIn this paper, daisy chained WLCSP packages with application is still limited to small chip size. As the conversion

leadfree solder bumps have been assembled on customer from SnPb to Pb free solder, the concern on thermal cycling isboards, and board level drop test has been carried out on a eased in a certain extent, as leadfree solder alloy e.g.JEDEC compatible drop tester. First failure is found at 42 SnAg4.OCuO.5 (SAC405) shows good thermal cyclingdrops among 36 samples. All the electrical failure found is performance. But with this leadfree alloy, the dropcaused by the breakage of Cu trace under critical corner ball at performance is reduced as the premature interfacial cracking isPCB side. To understand the failure mechanism and built up seen at solder/metal interface during drop impact. Thusthe life prediction model for WLCSP, finite element WLCSP under shock impact is a great concern for applicationsimulation has been carried out by explicit dynamic softwareANSYS/LS-Dyna. Strain-rate dependent elastoplastic model hheld eleronics.

for solder isdeveloped vi nano-indentation test an There are several types of bump structures for WLCSP.simusolderisdevelopedvianano-indentation.Higest in.nd Fig. 1 shows 2 typical structures, i.e. direct bump on Al padimplemented to the simulation.Highestinterfacepeeling (BoP) and bump on Cu redistribution layer (RDL). It isstress iS found at one of the corner and between solder anadstres isfoudatoneof te cmer nd etwen slderandimportant to understand the drop performance for the differentPCB Cu pad, which is exactly correlated with failure location imp tunest

from the test results. This failure mode is different from those bump structures.results for WLCSP open publications, where failure mostlyhappened at component side. From simulation analysis, it isunderstood that the maximum stress located at PCB side ismainly due to the Cu trace connected to the Cu pad alongboard length direction. Recommendation on Cu tracealignment has been proposed to improve PCB designaccordingly. Bump structure effect has also been simulated,and it is shown that RDL design with soft dielectric a) BoPpassivation layer is very helpful for the drop reliabilityperformance improvement ofWLCSP.

1. IntroductionWLCSP is a promising packaging technology to

accommodate the demand for small, portable handheldelectronic. This bare-die bumped package is able to offersignificant area savings, improve package electrical parasitics b) RDLand power dissipation performance over substrate-based BGApackages. As the packages are processes at wafer level until Fig. 1. Bump structures for WLCSP: BoP vs. RDLsingulation, the manufacturing efficiency is quite high and

thus low costcan be achived for volumeproductio .Wt The current project is to establish both the drop test andthese advantages, the application of wafer level packages has siuaincpbltefo. iepthWCS akgs asgrown very rapidly, especially in portable consumer products chie XLS akgswt A45sle up ilb

suha*adpoe n Dsec ttsiso LS assembled on customer boards, and board level drop test beusage in Nokia product has shown a volume growth of almost care u naJDCcmaibedo etr oehrwt300 times from year 2001 to 2007, and it is estimated the .. .. .vouewl dobl fro year 200 to......201 failure analysis and finite element simulation.

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C Test board wth componerts aced down

2. Drop Test Setup and Test VehiclesTypical setup of board level drop tester is shown in Fig. 2,

which is compatible to JEDEC drop test standard JESD22- Ic111111ionIsInB 111. WLCSP packages are mounted on test board, which is I nconnected to fixture and drop table with four corner screws,Test board is mounted with component side down, as shownin Fig. 3. Between board and base plate, standoff is added toallow board bending. The drop table or block is dropped from Fig. 3. Drop table with board mounteda certain height along the two guiding rods onto a rigid basecovered with one layer of specific felt. One accelerometer ismounted on top of base plate to measure the impact pulse.Event detector is used to detect the drop impact failure. Thethreshold resistance of event detector is set to 1500Q.

Following customer's request, our test method used in thistrial is very near JEDEC specification, only board design hasbeen modified, together with pulse width, where 1 Oms wasused, as compared to JEDEC of 0.5ms. Thus the impact pulseis with 150OG peak acceleration and l.Oms time duration (See 3.

Fig. 4). The tolerances of both peak acceleration and timeduration are within 10%. Good repeatability is assured for alltesting.

Fig. 5 illustrates the drop test board and component used. OXEach board has 12 components mounted. The test component Fig. 4. Impact pulseis a daisy-chained WLCSP device, with dimensions of3.9mmx4.1mm. Solder bump material is SAC405, and thereare 76 bumps in a depopulated non-symmetric array in a finepitch of 0.4mm and diameter of 0.25mm. PCB is routedaccordingly with daisy-chain device to form a close loop forfailure monitoring. Daisy-chain included 64 bumps out of total76 bumps, while bumps in the centre of the device areexcluded in the daisy-chain.

Components are assembled on Side A of test board (i.e. a) Board with 12 componentswithout micro-via in pad) with solder paste printing. Paste isSenju SAC305 with no-clean flux. Die shear test on trialsamples and X-ray check on all assembled board have been I I ItIdone to assure high quality f SMT (Fig. 6). t _ ..

b) Daisy-chained deviceFig. 5. Test Board and component

Fig. 2. JEDEC compatible board level drop testerFig. 6. X-Ray on the component after SMT

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3. Drop test results & data analysis 1 21 Cross section planesDrop test has been carried out for total 9 boards, with in---

situ resistance monitoring of the 12 individual devices on each 3aboard throughout entire drop testing by event detector. Drop t ,,test continued to 300 drop cycles, or when central units 5, 6,7*& 8 (shown in Fig. 4) have failed. Number of drop to failure I S~has been recorded and analyzed statistically. Fig. 7 shows the4Weibull analysis on data collected from units 5, 6, 7 & 8.

Re Wtll++ 7 - www.RehsSiftzomrFig.8. Cross-section planes

1C.-~ ~ J / g'I -~~

<~~~~~~~~~~~~~~~~~~ ~~~~~~~300pm EHT=1000 kV SigraIA SE2 Dat -22Feb2008Mag 25X WD_ 15m Photo No. 7888 Tim 1751

Fig. 9. Solder joint along the cross-section planeFi.7 ebl-Uo fdopts eut

The Weibull plot is a 3-parameters Weibull analysis, where W N N R & fI Kthe 3 parameters are f3=0.80, fl=80.50 and y=40.38respectively, with a correlation coefficient of p=0.97. y valueindicates the probability of failure before 40 drops isnegligible. This is considered as very good drop performancefor this WLCSP product.

Thorough failure analysis is done on selected devices tounderstand the failure mechanism. Since no precise faultisolation can be done on the individual bump in the daisychain, cross-sectioning was done on the peripheral rows ofbumps on each device. Outmost rows of bumps are expectedto be highly stressed regions during drop impact, thus therespective planes are selected for cross-section (See Fig. 8).No cracks were found on all solder joints sectioned alongPlanes 1,2 and 3 (See Fig. 9).

Figures 10 and 11I show the cross-section pictures alongPlane 4 for the critical ball from units 5 and 6 respectively. Itcan be seen that the copper trace under the critical (rightMcorner) bump is broken near the bottom right side of the Cpe rcbump. And cracking is also observed between the solder andEMCu trace interface. Electrical failure is due to the severed

rate hardening of the bulk solder is one of the 3 factors todetermine the cracking behavior of solder interconnections. Itis important to get the rate-dependent elastoplastic soldermaterial models and implemented into drop test dynamicsimulation[5]. This is done with nano-indentation test on thecorresponding bulk solder material. From nano-indentationtest, modulus and yielding stress at each loading rate can be

-mx11I11l0 01obtained. After yielding, Fig. 12 shows the typical stress-strain curves at different strain rate for SAC4O5. Perfectplasticity is assumed after yielding.

|1OOp EHT 10.00kV gnalASE2 D Mar 2008 0 1/secMag 200X WD- 17mm oPhtotNo 8115 Tirne:`1008 /sec

tn 5/sec *

Strain

Fig. 12. Typical rate-dependent material model for SAC

Simple elastic material model has been applied on otherconstituents, e.g. die, passivation, PCB etc. exceptelastoplastic properties are used for Cu.

Input G method [6,7] is used to apply the impact load to1Opm EHT = 1000 kV SignalA= SE2 Date :1 Mar2008

Mag= 1.50KX WD j17mm PhotoNo =8116 T 1008 the PCB board, i.e. the impact pulse recorded in Fig. 4 is

Fig. 11. Cross-section picture for the critical ball of unit 6 directly applied on the 4 screw supports of the board.

From Figures 4 and 5, it can be seen that the solder ballAnyway, this failure mode from board side is different layout is not fully symmetric. Thus a full model is necessary

from those published results for WLCSP, where failure mostly to simulate the full package behavior. However, this will leadhappened at component side [1-3]. It is stated in Reference to a very large dynamic model which is less efficient and time[2] that the cracking occurs predominantly at the components consuming. As the simulation purpose is to understand theside reaction layer is due to three factors: higher normal failure mechanism and predict the behavior of critical balls instresses in the component side, brittleness of the reaction the package, a quick full model is done to identify the quarterlayer(s) and the strain-rate hardening of the bulk solder which the critical balls fall in. Then further work will beinterconnections. focused on that quarter.

In next section, finite element simulation will be carried out Fig. 13 shows the peeling stress distribution in the fullto understand the different failure mechanism seen in the solder ball layout during drop/impact process. It is shown thatcurrent test, followed by some parametric study for further the solder ball with the maximum stress is exactly correlateddesign improvement. to the critical ball with cracking failure. Thus the

corresponding quarter with minimum bumps is taken for4. Drop Test Simulation further simulation (See Fig. 14).

Simulation is a proven efficient tool in IC packaging fordesign analysis and optimization, as well as root causeanalysis, comparing with actual drop test, which is expensive,time-consuming, and requires much more manpower inmeasurement and failure analysis. Current there are quite afew of publications on drop test simulation, but less is seen on ^ ~ w ^ fi ^WLCSP packages especially with RDL type of bump ^ _ fi_structure. X *4.1 Material model X

Currently from open publications, many drop test* -simulation work iS done basedl on the elastic properties of Critical Ballsolder material due to lack of suitable material Echaracterization data. As mentioned in last section, the strain- Fig. 13. Solder ball full layout and stress distribution

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Principal stress distribution is shown on the same graph,

Die which indicates that a maximum stress developed near thejoint of Cu trace to pad, which is exactly the location whereCu breakage is seen (Figures 10 & 1).

~~j~1~PCB

-79. 82 -26. 114 27.592 81.298 135.004

Fig. 14. 1/4 model of PCB and the package-52. 967 738831 54 445 108. 151 161. 857Fig. 14. 1/4model of PCB and the package Fig. 16. Peeling stress in solder bumps for the normalmodel without Cu trace

A assi'vation _C

a)BoP b)RDL

Fig. 15. Bump model: BoP vs. RDL

-65.764 17.397 100.558 183.719 266.881

Fig. 15 shows the simplified bump model for the -24.184 58.978 142.139 225.3 308.46simulation. It can be seen from Fig. 15 b) that the passivation Fig. 17. Principal stress distribution in Cu pad on PCB with alayer between Cu and silicon is built in to simulate the stress Cu trace connected to critical bumpbuffering effect for current WLCSP. As a comparison, directbump on pad is also modeled as shown in Fig. 15 a). Figure 18 shows the peeling stress distribution in solder4.3 Simulation results from 1/4 model bumps for the modified model with Cu trace included. What is

For the first round of simulation, normal circle Cu pad in different from Fig. 16 is that both top inner corner and bottomPCB is modeled. Peeling stress distribution is shown in Fig. outer corner of the ball is highly stressed, stress at bottom16, with zoom-in of the stress in the critical all. It can be seen corner is even a bit higher than that at top. By comparing thethat maximum stress located at top inner corer of the ball, stress at bottom side of critical ball from Fig. 16 to that fromand is much higher than the stress at bottom interface. While Fig. 18, it is estimated that the stress increase about 40% with

. . . ~~~~~~~theintroducition of Cui trace aligned along, board lengthfrom Figures 10&11, it iS shown the cracking happened at th inrdcon fCurae lged lngbrdeghbottom outer corner of the ball. It seems no obvious direction. With the combination ofmaximum peelingstress icorrelation between test and simulation results. solder interface (causing solder/pad interface delamination)After~~ .rechcFiue.-1 ti oicdta hrsaC and maximum principal stress inside the Cu trace (causingtrcrotn ou alon PC*eghdrcin As th bendin trace breackage), this bottom outer corner area iS highly

along PCB length direction after drop impact is the main cause possible to see failure, which is exactly what we found afterfor~.sode falue it isncssr o aetisC raeit drop test. Thus, current simulation model has captured the

main behavior of the test vehicle. A critical design rule forsimulation model. Fig. 17 shows the Cu padl pattern on PC C otn sreomne,ie vidainn utaewith a Cu trace connected to the pad under the critical bump. '

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along PCB length direction to avoid extra PCB related failure developed via nano-indentation test and implemented to themode to when evaluate drop performance of components. simulation. Highest normal interface stress is found at one of

the corner and between solder and PCB Cu pad, which isexactly correlated with the test results. Recommendation onCu trace alignment has been proposed to improve PCB designaccordingly. Simulation has also been carried out to compareBoP and RDL bump structures, and it is recommend thatproper RDL design with soft passivation material is the key toimprove the drop performance ofWLCSP packages.AcknowledgmentsThe authors would like to thank our customer for strongsupport rendered during this project. Thanks also to UTACR&D management for their guidance and support.Appreciation also to Liew Boon Pek, Au Keng Yuen, BooNan Shing and Kriangsak Sae Le for the assembly andYudikarta Haryanto for the FA support. Nano-indentation testis collaborated with Prof. John H.L. Pang from NanyangTechnological University.References

X...................

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Devices", Proc Electronic Components and TechnologyNormalized Conf FL, May-June, 2005, pp. 660-664

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BoP n AlpIad I Loading Condition", Proc. 57th Electronic Components

RDL (PIa1)E=600MPa 0.730 27% and Technology Conf, Nevada, May, 2007, pp. 528-535Passivation 6. Poh E.S.W., Zhu W.H., Zhang X.R., etc. "Lead-free Solder

Material Characterization For ThemomechanicalRDL (Pl2) E=2300MPa 0.598 40.2% Modeling", Proc. 9th EuroSimE, Freiburg, Gemany, April

It is seen from Table 1 that for RDL structure with passivation 2008, pp. 627-634layer as stress buffer between solder and silicon, the peeling 7. Luan J., Tee T.Y., Goh K.Y., etc., "Drop Impact Life

in solder top surface r s 2Prediction Model for LF BGA Packages and Modules",stress In solder top surface reduces 27/ as compared to BoP Proc 6th EuroSimE Berlin April 2005 pp. 559-565structure, and this stress is further reduced up to 400O if a ' ' 'ppsofter passivation is used. This RDL design and dielectric 8 Tee TY Luan J.E. Pek . etc. "Advanced Experimentalmaterial selection is very important for both board levelTOCOB and drop test performance-ofWLCSP packages. Responses during Drop Impact," Proc 54th Electronic

Components and Technology Conf; Nevada, June 2004,Conclusions pp. 1088-1l094

Board level drop test has been done for WLCSP packages 9. Zhu W.H., Xu L., Pang J.H.L., etc. "Drop Reliability Studywith SAC405 solder bumps. Drop number to failure meets the of PBGA Assemblies with SAC305, SAClO5 andreliability requirement. All the failure found is the breakage of SACl105-Ni Solder Ball on Cu-OSP and ENIG SurfaceCu trace under critical corner ball at PCB side. Finish", Proc 58th Electronic Components and Technology

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