Analysis and Design of Common-Gate Low-Noise Amplifier for Wideband Applications

Jouni Kaukovuori, Mikko Kaltiokallio, and Jussi Ryynänen Helsinki University of Technology, Electronic Circuit Design Laboratory / SMARAD2

P.O. Box 3000, 02015-HUT, Espoo, Finland jkaukovu@ecdl.hut.fi

Abstract—The design of a common-gate LNA for the wideband applications is discussed in this paper. First, the effect of the different components in matching network is analyzed in detail. This is followed by the design of a wideband input matching and output signal current for the input stage. A design example is given to demonstrate the effectiveness of the presented theory.

I. INTRODUCTION A common-gate (CG) LNA is widely used in wireless

communications [1-5]. The main drawback of the CG LNA is the minimum noise figure (NF), which typically is more than 3 dB. Therefore, the NF is slightly higher compared to an inductively degenerated common-source (IDCS) LNA, which limits the usage of the CG LNA. However, the drawback of a typical IDCS LNA is restricted input matching capabilities, which limit its usage in wideband solutions [6]. To overcome that problem, input matching network including several on-chip inductors have been designed [7]. As a result, the noise of an IDCS LNA tends to increase. The CG input stage, however, offers rather simple input matching realization. The input resistance at the MOSFET source is inversely proportional to the transconductance gm and the resulting impedance match is wideband. Due to the simple input matching circuit, the NF difference between wideband CG and IDCS LNAs becomes smaller than in narrowband systems. Therefore, CG LNA is a viable option for applications requiring wide operational bands, for example UWB [1][4].

Usually, the performance of the CG LNA is analyzed at the center frequency only and the operation as a function of frequency is neglected. In this paper the wideband CG LNA design taking into account the effect of the input matching network is analyzed in detail. The matching network plays critical role when the input matching and output signal current should cover wide bandwidths (BW). First, the basics of CG LNA are shortly discussed. Then, the optimal design of an input interface, which consists of series and parallel resonators, is derived. Finally, a design example, which utilizes the presented theory, is given.

II. BASICS OF COMMON-GATE LNA The desired input impedance of a CG input stage is

achieved by adjusting the bias current, aspect ratio, and overdrive voltage such that 1/gm is close to the termination impedance Z0. Typically, single-ended Z0 is 50 Ω, and therefore the gm of approximately 20 mS is required. The CG stage does not suffer from the Miller effect, and thus an adequate reverse isolation can be achieved with a single transistor stage. Therefore, the input matching network and load can be designed separately, although a feedback can be used to adjust the input impedance and frequency transfer function simultaneously [2].

Large impedance towards the signal ground is needed to steer the signal into the input transistor source. This can be achieved with a current source Ibias shown in Fig. 1a. That topology is not typically utilized in the LNA because the current source Ibias increases the noise. A significantly better noise performance is achieved by using a source inductor LS shown in Fig 1b. The LS forms a parallel LC resonator with the parasitic capacitance Cpar associated to the source node of the M1. When the on-wafer measurements are not applicable, the source node typically needs to be connected either to package or PCB by using a bond wire inductance Lin shown in Fig 1c. The Lin is resonated at the wanted frequency with a dc blocking capacitor Cin, which can be either an on-chip or an external component. The following analysis concentrates on CG topologies shown in figures 1b and 1c.

Figure 1. Common-gate LNA input interfaces: a) current source, b) parallel LC-resonator, and c) series and parallel LC-resonators.

This work was supported in part by Nokia Research Center, NokiaFoundation, and the Finnish Funding Agency for Technology andInnovation.

1-4244-1342-7/07/$25.00 ©2007 IEEE 64

III. ANALYSIS OF CG LNA The CG-LNA is analyzed with a circuit shown in Fig. 2.

The transistor M1 is replaced with a simple small-signal model consisting of gate-source capacitor Cgs and transconductance gm. The gm includes also the substrate transconductance gmb, i.e. the effective transconductance gm,eff of a CG stage is gm,eff = gm + gmb. For simplicity, the gm,eff is marked with a gm only in all figures and equations. The capacitor Cpar includes the parasitic capacitances at the source node, i.e. source-body junction capacitance of M1, substrate capacitance of LS, and capacitance caused by the bonding pads and on-chip metal wiring. Furthermore, the value of the source inductor LS can be decreased by adding an additional shunt capacitor CS as is shown in Fig 2. Therefore, all the capacitance at the source node can be included to a single source capacitor CT used in the following calculations:

T gs par SC C C C= + + . (1)

The source inductance LS resonates with the capacitance CT at the frequency of

01

S TL Cω = . (2)

The Q-value of an ideal lossless parallel resonator is infinite, but its characteristic impedance is expressed as

SLC

T

LZC

= . (3)

By combining (2) and (3), the ZLC can be given as

00

1LC S

T

Z LC

ωω

= = . (4)

Figure 2. Small-signal model used in analysis.

A. Input Matching Bandwidth The input impedance Zin of a CG input stage shown in Fig.

1b can be calculated as

21S

inS m S T

sLZsL g s L C

=+ +

. (5)

Assuming a perfect input matching (gm=1/Z0) at ω0, the corner frequencies, where the input matching S11 of (5) equals to typical –10 dB target, can be calculated as

2011 10 2

99 2 1 13S dB rel

rel

ZZ

ωω =−

= + ± +

. (6)

In (6), Zrel is the relative characteristic impedance of the LC source resonator scaled with respect to Z0, i.e.

0

LCrel

ZZZ

= . (7)

The bandwidth, where S11 is better than –10 dB, is achieved by subtracting the two frequencies given by (6). The result is scaled with respect to center frequency ω0 giving the relative input matching bandwidth BWrel,S11:

10, 11

0

23

dBrel S rel

BWBW Zω

−= = . (8)

Because the center frequency ω0 and source impedance Z0 are fixed, the relative bandwidth can be widened by increasing the ZLC value. According to (4), the maximum value of ZLC is achieved when the value of CT is minimized, i.e. the additional shunt capacitor CS is omitted and the value of LS is increased such that the resonator is tuned at the wanted frequency.

B. Effect of series LC resonator The input inductance value Lin is scaled with respect to LS

with a design parameter p such that Lin=LS/p. To maximize the S11 performance, the series resonator should be tuned at the same frequency with the source parallel resonator. Therefore Cin=pCP is needed. The Zin of the circuit shown in Fig. 2 is

2

2

11

S T Sin

T S m S T

s L C sLZspC sL g s L C

+= ++ +

, (9)

which reduces to 1/gm at center frequency ω0. The frequencies, where the –10 dB S11 limit of is achieved, are

( )010 1 2 1 2 2 32

2 3dB F F F F F Fωω− = + ± + + , (10)

where ( )2 2 2

1 4 2 4 3 43 12; 9 16 ; 4 9 2F F F F p F F p= − + = + = − + , (11)

and

22

4rel

rel

p ZFZ

−=

. (12)

In Fig. 3 the relative input matching bandwidth is shown as a function of p with several Zrel values.

Figure 3. Relative S11 BW as a function of resonator design parameter p

with several source resonator relative impedance Zrel values.

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The maximum BWrel,S11 is achieved, when

22 relp Z= , (13)

and then

( ), 11,max1 73 3 0.966rel S rel relBW Z Z= − ≈ ⋅ . (14)

In Fig. 4 the BWrel,S11 is shown as a function of Zrel. Solid line shows the effect of the source parallel resonator only (8). With a dashed line is shown the performance of the whole matching circuit with several series resonator design parameter p values (10). For example, if both the input and source resonators have equal component values (p=1), the BWrel,S11 is approximately 0.8 when Zrel is 1. To achieve wider BWrel,S11, the Zrel of the source resonator should be increased. In addition, the design parameter p should be chosen appropriately not to limit the overall BWrel,S11. The Zrel increases proportionally to the source inductor value. Because the optimal value for p depends quadratically on Zrel, the value of input inductor Lin is inversely proportional to the value of LS. The choice of optimal Zrel and p values is not unambiguous when BWrel,S11 is known. For example, the minimum and maximum inductor values are typically limited by the design kit and by the used semiconductor package.

Figure 4. Relative S11 BW as a function of source resonator relative

impedance Zrel with several resonator design parameter p values.

C. Output signal current A typical figure-of-merit for narrowband LNAs is the

voltage gain, which is defined as a ratio of output and input voltage signals. However, LNAs have perfect input matching only at a specific frequency area. Therefore, for wideband LNAs, a more suitable merit is the insertion gain defined as the ratio of the output signal voltage to half of the voltage of the source driving the LNA input [5]. The output voltage at load impedance ZL is Vout= IoutZL, where Iout is the output signal current of the input stage. If the drain-source resistor rds of CG input device is large enough compared to ZL, i.e. rds>10ZL, the output current is equal to the drain current of M1 and the effective load impedance is defined by ZL only. A wideband LNA typically uses a shunt-peak load, which can offer several GHz bandwidth [8]. To design a proper LNA, also the drain current must have sufficient bandwidth not to limit the overall output voltage signal bandwidth.

The CG stage transforms the voltage signal VS sensed at the source node to the drain current. At a resonance frequency

ω0, the output current Iout=gmVS=gmVin, where Vin is the voltage signal fed to the LNA input. Both the input and source resonators, however, affect the Iout as a function of frequency. Therefore, such corner frequencies are calculated, where the output signal current is decreased by 3 dB compared to the signal current at the resonance frequency. When the –3 dB corner frequencies are scaled with respect to ω0, the following expression is obtained:

( ) ( )2 23 65 6 6 7 6 7

0 5

1 2 4 4 8 82

dB FF F F F F FF

ωω− = − ± + − − + + , (15)

where

2 2 25 4 6 4 7 416 ; 4; 2 3F p F F F F F p= + = − = + − (16)

and F4 is given by (12). The relative output signal current BWrel,Iout is achieved by subtracting the two frequencies given by (15). The BWrel,Iout is plotted as a function of p with several Zrel values in Fig. 5. The maximum BWrel,Iout is achieved, when

26 relp Z= (17)

and then the BWrel,Iout is

( ), ,max1 1201 25 2.22rel Iout rel relBW Z Z= − ≈ ⋅ . (18)

Compared to the BWrel,S11, the BWrel,Iout is wider with equal Zrel and p values. Therefore, it is more challenging to achieve S11 better than –10 dB than gain flatness of 3 dB. However, when the effect of the load impedance is taken into account, the gain can be limited at high frequencies due to the parasitic capacitance at the output node.

Figure 5. Relative –3-dB output signal current bandwidth as a function of

resonator design parameter p with several Zrel values.

IV. DESIGN EXAMPLE The design of a CG LNA, which covers the UWB band

groups #1 and #3, i.e. 3–8 GHz, is presented. For simplicity, a single-ended structure was chosen, but the presented analysis can be utilized for a balanced CG LNA, too. The schematic of the LNA is shown in Fig. 6. The bonding pad was included to the simulations to achieve realistic parasitic capacitance at the input node. The transistor M1 was biased with a 1.2-mA current from a 1.2-V supply voltage. The source impedance Z0 was 50 Ω. The simulations were performed with a 0.13-µm CMOS process.

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Figure 6. Simplified schematic of CG LNA.

The desired band is 3 – 8 GHz and the center frequency is approximately 5 GHz. Therefore, the relative bandwidth is 1. First, the design criteria for source and input resonators are estimated from figures 3 and 4. To achieve better than –10 dB S11, which covers the whole band with some design margin, the required minimum relative impedance Zrel for the source resonator is 1.5. The input series resonator should be dimensioned with a p value higher than 2.

According to (4), the source resonator tuned at 5 GHz frequency should have at least 2.4-nH inductor for the desired Zrel. The source resonator was designed without additional shunt capacitance and the resonance at 5 GHz frequency was achieved with a 3.0-nH inductor. The input matching without the series input resonator is shown in Fig. 7 with a solid line. The source resonator gives S11 is better than –10 dB from 2.7 GHz to 8.8 GHz. The relative bandwidth is 1.22, which is close to the theoretical value 1.26 given by (4). The Zrel of the source resonator is evaluated with (8): Zrel = 1.83.

According to (13), the optimal value for p would be 6.7 to maximize the overall BWrel,S11. Because the Zrel was slightly overdesigned, smaller p value can be chosen and still achieve the required S11. The S11 of the whole LNA was simulated with the p values of 2, 3, and 4. The results are shown in Fig. 7 with dashed lines. The BWrel increases along with p according to the theory. The p value between 2.5 to 3 gives the required S11 bandwidth. With larger p values the S11 BW is improved but the value of the input inductor Lin gets smaller. Therefore, it is possible that optimal Lin is not reached due to limitations set by bond wire inductor to package or PCB.

Figure 7. Simulated S11. With a solid line is shown the effect of the source resonator. With a dashed line is shown the whole S11 with several p values.

The insertion gain and NF are shown in Fig 8 with p values of 2, 3, and 4. The gain and NF are approximately 12 dB and 4 dB over the whole wanted band. Both the gain and NF bandwidths increase along with p. However, the

highest operational frequency is limited by the shunt-peak load and the parasitic capacitance at the output node. Therefore, scaling the p does not improve the BW at high frequencies. The gain is decreased at 8 GHz frequency by approximately 1 dB from the maximum value. To increase the operational BW at high frequencies, the value of load resistor should be lower. As a result, the gain would degrade as well.

Figure 8. Simulated insertion gain (solid line) and NF (dashed line) with p

values of 2, 3, and 4. Both the gain and NF BW increase along with p.

CONCLUSIONS The design of a wideband CG LNA was discussed in this

paper. The effect of input and source resonators for input matching and output signal current achieved from a CG input stage were analyzed in detail. A simulation example for the LNA operating at 3 – 8 GHz band was given. The input matching was better than –10 dB and the gain flatness was 1 dB at the desired band. In this design example, the implementation of a sufficient input matching network was limited by the minimum length of the input bond wire. The upper limit for the gain was set by the parasitic capacitance of the output node. According to the design example, it is possible to achieve a unity relative BW at 5 GHz center frequency with a simple CG LNA. The simulation results are in good agreement with the theory.

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