ICSE 2006 Proc. 2006, Kuala Lumpur, Malaysia

Device Design Consideration for Nanoscale MOSFET UsingSemiconductor TCAD Tools

Teoh Chin Hong and Razali IsmailDepartment of Microelectronics and Computer Engineering,

Universiti Teknologi Malaysia,81300 Skudai, Johor, NIALAYSIA

Email: pink tchAyahoo.com razafil&e.utm.m

Abstract The evolution ofMetal-Oxide-Semiconductor Field EffectTransistor (MOSFET) technology has beengoverned mainly by device scaling over thepast twenty years. One of the key questionsconcerning future ULSI technology is whetherMOSFET devices can be scaled to 100nmchannel length and beyond for continuingdensity and performance improvement. Inthis paper, the design, fabrication andcharacterization of high-performance andlow-power 90nm channel length MOSFETdevices are described. Several parametershave to be scaled down such as gate oxidethickness, channel length, ion implantation forthreshold voltage adjustment and otherspecifications to achieve desirable electricalcharacteristic. To control the short-channeleffect (SCE) and hot-carrier reliability thatlimits device scaling, lightly doped drain(LDD) structure, shallow junction of drain /source and Shallow Trench Isolation (STI) areimplemented. Virtual Wafer Fabrication(VWF) Silvaco TCAD Tools is used forfabrication and simulation of CMOStransistor namely ATHENA and ATLAS.Simulations using these programs providedthe opportunity to study the effect of differentdevice parameters on the overall deviceperformance. The devices were simulated andgradually the performance of each one wasimproved, until an optimal deviceconfiguration was created for a particularapplication.

I. INTRODUCTION

Over the past 50 years of the semiconductorindustry, the size of MOSFET has been scaleddown obeying the Moore's law: feature sizes oftransistors are scaled at a rate of approximately0.7 times every 18 months [1]. However, asMOSFET technology approaches nanoscale

region, researchers face with critical technologybarrier known as SCE. While the gate voltagefully controls the channel conduction state in anideal MOSFET, the drain voltage begins to givemore influence on the channel potential in ananoscale MOSFET.

In order to enhance the speed performanceof the circuit and for higher density whilemaintaining its reliability and circuitperformance, the MOSFET transistor has beenscaled down by using Constant Field Scalingrules because it is easier and assumed to avoidthe high field problems. Important parameterslike channel length (L), doping concentration(NA, ND) during ion implantation for thresholdvoltage adjustment and gate oxide thickness (tox)will be scaled [2].

Advanced transistor design such as STIeliminates the bird's beak shape characteristic,subthreshold hump and field oxide thinningeffect in LOCOS isolation. STI has advantagessuch as perfect planarity, scalability and latchupimmunity [3]. Besides that, LDD is designed tosmear out the strong electric field between thechannel and heavily doped s/d, in order to reducehot-carrier generation. While shallow junction ofdrain/source can increase device density. Toreduce charge sharing effect, halo implant isintroduced in which the locally high dopingconcentration in the channel near thesource/drain junctions is created. Retrograde wellis a form of vertical channel engineering. It isused to improve SCE and to increase surfacechannel mobility by creating a low surfacechannel concentration followed by a highlydoped subsurface region.

II. OPTIMIZATION

Optimization is essential in scaling downdevice to obtain better device performance.Optimization of these devices using the TCADtools requires many hours of lab simulation time.

0-7803-9731-2/06/$20.00 ©2006 IEEE 906

ICSE 2006 Proc. 2006, Kuala Lumpur, Malaysia

Several aspects of each device were selected foroptimization. Once the device characteristicswere selected for optimization, the process ofdevice simulation began. First each parameterwas tested individually for its effect on deviceperformance as a whole. Once several plots were

obtained that indicated the particular parameter'seffect on device performance, improved valuescould then be selected for the device. Severalsimulations needed to be run to find improvedvalues for each device parameter until an optimalvalue were reached. Once an optimal value was

reached for each of the device parameters, theimproved parameters were then combined into a

single device. When all these new values were

present in a single device, they were againsimulated and adjusted to optimize based upon

their combined effects to ultimately produce an

optimal device configuration. Various analysisand discussion are done on particular parameter'seffect on device characteristics.

III. ANALYSIS AND DISCUSSION

There are a number of parameters that affectthe value of threshold voltage and drain inducedbarrier lowering (DIBL) parameter which willresult in different device performance andcharacteristics. Each of the parameters will bediscussed in the following section.

A. Effect of Channel Doping on ThresholdVoltage

The channel doping depends on severalcomponents such as the type of atom beingimplanted, the dosage and the energy of theimplant. The doping concentration and depth are

affected directly. Multiple threshold voltages can

be achieved by adjusting the channel doping as

shown in Fig. 1. Threshold voltage increases as

channel doping increases which is comparable tothe result reported in the literature [4].

Graph of Vth vs Channel Doping (9Onm NMOS)

0. 25

0. 20

0.

.0 10o

0. 05

0. 002. OOE+12 2. 50E+12 3. OOE+12 3. 50E+12 4. OOE+12 4. 50E+12 5. OOE+12

Channel Doping (cm -2)

(a)

Graph ofVth Vs Channel Doping (9Onm PMOS)

0. 00

-0. O 530-0. 20

-0. 30

-0. 40

-0. 50

-0. 60

-0. 70

E+11

Channel doping (cm'-2)

(b)

Fig. 1 Threshold voltages at different channel doping

dose for (a) 90nm NMOS (b) 90nm PMOS.

B. Effect of Oxide Thickness on ThresholdVoltage

Gate oxide thickness can be used to modifythe threshold voltage of a transistor. Variation ofthreshold voltage with different oxide thicknessfor a 90 nm device is shown in Fig. 2. Loweroxide thickness and hence lower thresholdvoltage in critical paths can maintain theperformance. Higher oxide thickness not onlyreduces the subthreshold leakage, it also reducesgate oxide tunnelling current since the oxidetunnelling current exponentially decreases withan increase in the oxide thickness [5].

907

E+11 3. 00E+11 3. 50E+11 4. 00E+11 4. 50

N,

11.1

ICSE 2006 Proc. 2006, Kuala Lumpur, Malaysia

Graph of Vth Vs Gate Oxide Thickness (9OnmNMOS)

0. 7

0.6

0. 5

0.4

; 0.3

0.2

0. 1

0

20 25 30 35 40Gate Oxide Thickness (A)

(a)

45 50

Graph of Vth Vs Gate Oxides Thickness(9Onm PMOS)

0

-0. 1

>: -O. 2

+ -O. 3

-0. 4

-0. 5

Gate oxide thickness (A)

(b)

Fig. 2 Variation of threshold voltage with different

gate oxide thickness for (a) 90nm NMOS (b)9Onm PMOS.

C. Effect of Channel Length on ThresholdVoltage

Fig. 3 illustrates how threshold voltage ofNMOS decreases as the channel length isreduced. Hence, different threshold voltage can

be achieved by using different channel length.This reduction of threshold voltage withreduction of channel length is known as

threshold voltage rolloff.

Graph ofVth Vs Channel length (Lg)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0 _0 100 200 300 400 500 600

Channel length (nm)

Fig. 3 Effect of various channel length on thresholdvoltage for NMOS.

D. Effect ofDrain Voltage on Threshold Voltage

In a short-channel device, the source anddrain depletion width in the vertical direction andthe source drain potential have a strong effect on

the band bending over a significant portion of thedevice. Therefore, the threshold voltage andconsequently the subthreshold current ofshort-channel devices, vary with the drain bias.This effect is referred to as drain induced barrierlowering (DIBL).

Fig. 4 is a plot of threshold voltage (V1) vs

drain voltage (Vd) to investigate the varying ofthreshold voltage as different drain voltage isapplied. The threshold voltage decreasing as thedrain voltage is increasing which is comparableto the explanation above. For comparison, thevalue of the threshold voltage of the 90 nm

NMOS that is doped with halo implant is higherthan the one without halo implant doping which

Graph ofVth vs Vd (90 muNMOS)

0.30

0.25 X

0.20

0. 15- 0.10

= 0.05

> 0.00

-0. 05

-0. 10

-0. 15

-0. 20 L

-I-Vth (without halo)Vth (with halo)

0.2 0.4 0.6 1 2

)~

Vd (V)

contributes less subthreshold current. By usinghalo implant, the threshold voltage degradation isreduced.

908

f

"I'--

r

4-1

15

EL. -

M-M-M."

ICSE 2006 Proc. 2006, Kuala Lumpur, Malaysia

Fig. 4 Graph of threshold voltage versus drain voltagefor 90nm NMOS with and without haloimplant.

Fig. 6 Graph of Vt versus retrograde well dose for

90nm NMOS.

E. Dependence of Halo Dose on ThresholdVoltage

Fig. 5 shows the Id-Vg curves for 90nmNMOS at different halo doses. It can be seen thatthe value of the threshold voltage increased as

we increased the halo dose. Thus, thresholddegradation can be controlled well since the haloimplant reduces the charge sharing effects fromsource and drain fields.

- 9ONLMOS haWojeaog9ONMOS hWo_iOlog

=9NMOSrRIo 721 g

Halo dose 7E+08

Halo dose 7E+±

Dr@un Currentl()

Halo dose 7E±12

Fig. 5 Id-Vg curve with different halo doses for 90nm

NMOS.

F. Dependence of Threshold Voltage on

Retrograde Well Dose

Fig. 6 shows the dependence of thresholdvoltage on retrograde well dose. The thresholdvoltage for 90 nm NMOS is increased by theincreasing retrograde well dose. Thresholdvoltage is adjustable by using retrograde welldose as well as using implantation technique.

Graph of Vth vs Retrograde well dose (90 nm NMOS)

0.6-

0.5-

0.4-

.m 0.3

0.2-

0.1I

0 L0 1E+13 2E+13 3E+13 4E+13 5E+13 6E+13

Retrograde well dose (cm-2)

G. Dependence ofDIBL on Halo Dose

Fig. 7 is the graph of DIBL versus halo dosefor the 90 nm NMOS with halo implant. It showsthat increasing halo implant dose reduces thevalue of DIBL. This indicates that we can use

halo implant to control the MOSFET degradationdue to DIBL.Fig. 7 Graph of DIBL versus halo dose for 90nm

NMOS.

H. Dependence of DIBL on Retrograde Well

Graph ofDIBL vs halo dose (90 nm NMOS)

6. 23006. 2250 =

;0. 220020. 2150

60. 21006. 20506. 2000

6. OOE O 2. OOE 1 4. OOE 1 6. OOE 1 8. OOEtl 1. OOEtl 1. 20Et11 1 1 1 2 2

Halo dose (cm-2)

Dose

Fig. 8 shows the effect of DIBL for the90nm NMOS with different retrograde welldoses. The DIBL effect is defined as the changein the threshold voltage AVt divided by thechange in the drain voltage AVd. It is clear fromFig. 8 that for a higher retrograde well dose theDIBL will decrease.

909

Graph ofDIBL Vs Retrograde Well Dose0. 350. 3

0.250. 2

0. 10. 05

0O. OE+00 5. OE 12 1. OF+13 1. 5E+13 2. O13 2. 5E+13 3. OF+13

Retrograde Well Dose (cm-2)

ICSE 2006 Proc. 2006, Kuala Lumpur, Malaysia

Fig. 8 Graph of the dependence of DIBL on

retrograde well dose for 90nm NMOS.

I. Overall Effect of Process Parameters onThreshold Voltage

Table 1: The overall effect of process parameters on

threshold voltage for 90nm NMOS and PMOS

Table 1 summarized the overall effect ofprocess parameters on threshold voltage for the90nm NMOS and PMOS. Threshold voltageincreased as channel doping, gate oxidethickness, channel length, halo dose andretrograde well dose increased. However,threshold voltage decreased as drain voltageincreased.

IV. CONCLUSION

A number of parameters that affect the valueof threshold voltage and DIBL parameter whichresult in different device performance andcharacteristics are discussed. The improvedparameters were again simulated and adjusted tooptimize based upon their combined effects toproduce an optimal device configuration.

ACKNOWLEDGEMENT

Threshold voltage

90nm 90nmNMOS PMOS

Increasing channeldopingIncreasing gateoxide thickness

Increasing channellength

Increasing drainvoltage

Increasing halo dose

Increasingretrograde well dose

9 9

0 4

9 9

a

0 0~~

6 6

a i

The authors acknowledge the Ministry ofScience, Technology and Innovation Malaysia(MOSTI) for the financial support through PTPscholarship.

REFERENCES

[1] H. Wakabayashi, et al.(2003). Sub-10-nmPlanar-Bulk-CMOS Devices using LateralJunction Control. IEDM Tech. Dig. December2003. Washington DC, 989-991.

[2] SIA et al. International Technology RoadmapforSemiconductors. 2003 edition.

[3] C. Mead and L. Conway (1979). Introduction to

VLSI systems. Addison Wesley. p. 37.

[4] N. Sirisantana, L. Wei and K. Roy (2000).High-performance low-power CMOS circuits

using multiple channel length and multiple oxidethickness. Proc. Int. Conf Computer Design.

227-232.

[5] K. Schuegraf and C. Hu (May 1994). Holeinjection Sio2 breakdown model for very low

voltage lifetime extrapolation. IEEE Trans.

Electron Device. vol. 41: 761-767.

910