MICROPROCESSOR-BASED CONTROL OF AN SVC FOR OPTIMAL LOAD COMPENSATION

Antonio G6mez Expbi to, member Francisco Gonzilez Vizquez Dep. of Elec. Engineering University of Seville, Spain

Carlos Izquierdo Mitchell, member

Tomis Gonzilez Garcia Sevillana de Electricidad, Spain

Francisco del Pozo Madrofial I. N. Thcnicas Aeroespaciales, Spain

Abstract. This paper presents an open-loop control strat- egy for optimal compensation of arbitrary loads by means of thyristor-controlled reactors. Real-time implementation of this technique on a microprocessor-based working prototype is also described. Simulation and experimental results show that, using the proposed scheme, abrupt load changes are always compen- sated within the next cycle.

Keywords: Static Var Compensators, Open-loop control, Power factor correction.

1 Introduction

Static Var Compensators (SVC) are nowadays a well-established means for reactive power compensation of large, fluctuating in- dustrial loads and/or dynamic voltage support of transmission systems [l-31. Conventional state-of-the-art SVCs are based on a thyristor-controlled reactor (TCR) in parallel with either a fixed capacitor (FC) or a set of thyristor-switched capacitor (TSC) banks [l-31.

Recently, several advanced SVC configurations have been de- scribed based on AC-DC or AC-AC power converters [4]. They provide leading or lagging VARs with a minimal use of induc- tors and capacitors. These arrangements, however, rely on a more demanding use of solid-state switching devices. Hence, in spite of their promising future, some technological and econom- ical barriers are to be destroyed before they find a generalized use in high-power applications.

As for the SVC control strategy, there are basically two ap- proaches [1,3] which can be combined. Those compensators in- tended for voltage regulation adopt a closed-loop control so that certain error signals are reduced. On the other hand, several algorithmic principles suitable for load compensation have been applied in the design of open-loop control systems.

Up to date, most control strategies are based on the assump- tion that both TCR and load currents are sinusoidal. See, for instance, [5-81. Clearly, this underlying premise is far from being true, particularly taking into account the increasing number of

non-linear loads currently in use. In this regard, revision of the classical power factor and reactive power concepts [9,10] may soon have practical consequences, not only in the instrumenta- tion field, but in load compensation as well. This new theoreti- cal background leads naturally to a frequency-domain analysis of the different magnitudes involved (susceptance, current, reactive power, etc.).

Trying to advance the state-of-the-art and, at the same time, eluding those controversial issues, this paper proposes a differ- ent, time-domain approach. I t is based on the simple idea that improving the power factor, no matter its definition, is equiv- alent to reducing the current drawn from the feeder. A TCR triggering angle is then computed which minimizes the true rms value of the total current (load+compensator). The technique is suitable for both TCF/FC and TCR/TSC compensators, and is amenable to real-time implementation. Simulation and exper- imental results included in the paper confirm the feasibility of the proposed approach.

In the course of this project, a similar strategy was suggested in [ I l l . However, sinusoidal situation i s still assumed and man- ually switched capacitors, instead of SVCs, are employed.

2 Control Strategy

Due to its simplicity, the single-phase version will be dealt with firstly. Furthermore, basic ideas are more easily visualized, since the number of involved magnitudes is lower.

2.1 Single-phase SVC The open-loop control strategy proposed in this paper is ex- plained with the help of Figure 1.

Given a load, not necessarily linear, connected to a bus where voltage is reasonably sinusoidal, the control problem reduces to find the gating angle a of the T C R which minimizes the rms value of the total current. In practice, instead of measuring the load current, i z ( t ) , it is more convenient, as will be discussed below, to measure i+(t), the compound load+capacitor current.

Mathematically, given i z ( t ) and assuming

v(l) = v c o s ut

find a that minimizes

0 with

T = 2 x f w

@7803-O219-U9 1/ooO9-0!l65$01 .OO 0199 1 I E E

ix(t) iz (t)

I i L ( f f , t ) v(t)

1’ i,(t) -

load

- Y - 4v + I T -E7

L

- Figure 1: Magnitudes involved in control

& (sin wt - sin a )

&-(sinwt + s i n a )

a < wt 5 x - a

r + (I < w t 5 27r - Q

A third possibility is to directly measure the total drawn cur-

(4) rent, i = i~ + i,. In such a case equation (7) reduces to

idt = o (10)

i L ( ( Y , t ) =

Minimization of 51 is obtained when

a

/ 0 /-+ /

,=’ / A ( L , a ) - \ 4--- 0

-- ”-

(5) lT dt = 2 1 T ( i L +io)- ai, a t = 0 aa da

Substituting for d z ~ / a a in equation (5) leads to

( a ~ + i,) dt = 0

(6) 1 ~ c o s a ( s - a ) l w ( P n - a ) / w

- 7 [l,w + 2 , ) dt -

For CY # */2 the term in brackets must vanish. Taking into account (4) this means that

1 4v x [( - a ) sin a - cos a = A(*,, a) (7)

where the following function has been defined

( r - a ) / w (Pn-a ) /w

A(&, Q) = J., i, a t - 1 i, dt (8)

Figure 2 shows a possible function A(i,, a) and the value of a which satisfies equation (7). The smoother curve represents the left side of that equation which remains fixed as long as V does not change.

Note that a = r/2 is always a solution to eq. (7). When no other Q satisfies this equation, then a decision must be taken on which gating angle should used for the next cycle. This decision is based on A(i,,O). If A(i,,O) > -4V/Lw2 then a = 7r/2, suggesting the capacitor should be increased. Otherwise a = 0 and, if possible, the capacitor should be decreased. For the case in which the capacitor is made up of several steps, this logic may be used to decide whether a new bank must be switched on or off. The triggering angle of the TCR will be automatically adapted to the new situation a cycle later.

If i, was measured instead of a, then the optimum value of a would be the solution to

r t a ) / w

Notice that , in addition to V, the value of C affects now the non-measured part of equation (9). Therefore i t must be recom- puted whenever a capacitor bank is switched on or off.

Although eq. (10) looks simpler than eq. (7), practical solu- tion of both equations requires about the same computational effort. An advantage of (10) is that the resulting a is indepen- dent of V. However there is a “philosophical” difference between both equations. As long as short-circuit capacity of the bus where the load is connected is large enough, is is not affected by the triggering instant of the TCR (Fig. 3). Thus, eq. (7) implies a pure “feedforward” control ([l], pp. 196-200).

On the other hand, some “feedback” is implicit in eq. (10) since the triggering angle a influences the measured current through i ~ ( a ) . Hence, the usual problems of closed-loop con- trol systems (slower response, risk of instability, etc.) must be faced.

It may be shown that solution of eq. (10) is equivalent to the iterative solution of eq. (7) in a cycle-wise manner, i.e. using the most recent a on the left side of (7) and computing Q for the next cycle from the right side. Depending on the initial guess and convexity of both functions, this process may lead to a wrong value, usually a = 7r/2. Actually, eq. (7) can be solved iteratively within the same cycle by means of a more reliable search process (see Practical Implementation).

The preceeding analysis has been based on the assumption that the same triggering angle will be used in alternate half- cycles of the supply frequency. This ensures that only odd har- monics will be generated. Nonetheless, there are several pos- sibilities to accommodate for different gating instants of both thyristors. Depending on the scheme adopted, a set of equa- tions similar to (7), (9) and (10) should be solved twice a cycle. The simplest approach would surely be to alternatively equate

I lo I

Figure 3: Different control philosophies

%6

+ mains load+capacitor + (12) . . . . .

i ~ 1 = 212' - 131 ; t ~ z = i23 - 112 ; a ~ 3 = i31 - i 23

and

&(sinwt - s i n a l ) a1 5 u t 5 A - 01

(13) {- L", (sinwt + s i n a l ) A + a1 5 w t 5 2n - a1

&(sin(wt - F) - sincwz)

=(sin(wt - F) + sin a?)

~ w ( s i n ( w t + F ) - s i n ~ g ) a3 5 w t + ? < 7 r - a 3

&(sin(wt + F) +sinag)

e12 =

a2 5 wt - % 5 A - a2

A + a2 5 w t - 4f 5 2% - a2

923 = I. (14)

{- (15) A + a3 5 w t + 5 27r - a3

Note that each gating angle is counted from the positive peak of its respective line-to-line voltage.

Taking into account that each T C R line current depends only on two gating angles, minimization of 53 is obtained when the following three equations are satisfied,

i31 =

1 3

Figure 4: Currents of interest for the three-phase case

each single integral of (8) to the left side of (7) divided by 2. Another possibility could be to use eq. (7), alternatively adding an offset of 10 msec. to the integral limits in (8).

Finally, expected harmonic content of voltage waveform should not significantly affect the triggering angle obtained from eq. (7) due to the double integration process implicit in equa- tions (4) and (6). As an example let us consider the addition of an in-phase odd harmonic of the form kVcos(nwt) to eq. (1). It may be easily shown that the term

1 nz.Lwz k 4v [ ( Z - a ) n s i n n a - c o s n o A

then arises in the left side of (7). For a 5% third harmonic (E = .05, n = 3), neglecting this additional term gives rise to a maximum error of 1.4 degrees in the firing angle.

2.2 Three-phase SVC

Furthermore, since

aiL2 aiL3 a i 2 3

a~ aaz aaz -=--=-

The single-phase control strategy proposed above remains valid for three-phase systems, provided all individual components (TCR, capacitor and load) are delta-connected. Each phase is then optimally and individually compensated.

However, since the T C R is always delta-connected, a simi- lar but different strategy must be devised for the case of wye- connected loads or arbitrarily connected loads whose terminals are not readily accessible.

Given i l l , ix2 and iz3 (Fig. 4) and assuming a symmetrical

equations (16) reduce to

ail2

ai23

L T ( i 1 - i 2 ) G dt = 0

( i2 - i 3 ) - dt = 0 1' aa2

set of line-to-line voltages, l T ( i 3 - il)a(y3 a i31 dt = 0

Using the notation of eq. (8), equations (18) may be written in compact form as

Ao(i1 - i 2 , c ~ i ) = 0 the objective is to find a1 , a2 and a3 which minimize the scalar

53 = lT(if + i$ + 2:) dt

AZs/3(i2 - 23, a 2 ) = 0 (19)

A4X/3(i3 - i l , a3) = 0

where subindices 0, 2 ~ / 3 and 4 ~ / 3 refer to the "offsets" which must be added to the integration limits of the respective inte- grals. Equations (19) are the 3-phase counterpart of eq. (10).

with il = 2x1 + ~ L I ; i z = i z2 + ~ L Z ; 63 = i z 3 + i ~ 3 (11)

967

As stated in the problem formulation, itl, i t 2 and i t 3 are measured rather than i l , i~ and 23. Hence, equations (19) are rearranged as

- A O ( ~ L I - i ~ 2 , a l ) = A o ( i , l - i 2 2 , a 1 )

- A Z x / 3 ( i L Z - i L 3 , a 2 ) = A 2 ~ / 3 ( i . z 2 - i z 3 j 0 2 ) (20)

- A 4 r r / 3 ( i ~ 3 - 2 . ~ 1 , ~ 3 ) = A 4 x / 3 ( i z 3 - itl, ~ 3 )

Owing to 3-phase symmetry, the former three equations are identical, provided the proper subindices are interchanged. Hence, the first one will be considered in some detail. Dropping for simplicity the subindex "0", and taking into account (la), yields

- A ( i ~ i -2~2,ai) = -2A(i12, a i ) + A ( i 2 3 , a i ) + A ( i 3 1 , ~ 1 ) (21)

(7) and depends only on a,. The other terms of (21) depend, more- over, on az and a 3 respectively. For instance, -2A(&,a l ) is composed of four integrals for a1 + a 2 < x/3, two integrals for x/3 5 a1 + a2 < 2x/3 and is null for a1 + a 2 2 2x/3. This means that equations (20) are in general coupled. Omitting the cumbersome intermediate steps, those equations lead to,

The term A ( i 1 2 , a l ) is clearly the left side of eq.

$ [4 [ 5 - a,) sin a 2 - 4 cos a2 + B 2 3 + E 2 1 = (22) 1 1 2 v [4 ,( f - 013) sin a 3 - 4 cos a 3 + B 3 1 + 8 3 2 =

where,

for 2 ~ / 3 5 at + a] 5 A

for x /3 5 ar + a] 5 2 ~ / 3 for 0 5 at + aJ 5 ~ / 3

[ $ sin a, - cos ar

- (at + a,)] sin aI - cos aJ - cos (a, + :) Brj =

Real-time solution of equations (22), though possible, is not a trivial task and, in any case, requires a great deal of computing power. In those situations in which important load unbalances are not to be expected, using the same gating angle for the three TCR branches will suffice. The added benefit that the TCR triplen harmonics are then absent from the line currents must also be assessed.

Let a be the T C R common gating angle. Then, minimization of 5 3 leads to

which may be written as (23)

Ao(i1 - i 2 , a) + A 2 x / 3 ( i Z - 23, a) + A 4 , , / 3 ( i 3 - i l , 0) = 0 (24)

Comparing (24) with (19) the following equation may be di- rectly obtained from (22),

1 [ ( z -a) s ina - c o s a + -B(a)] 2 = (25) L W 2

: < a < ; - 20) s ina - cosa -cos (a + :) 3 5 a 5 3

$ s ina - cosa O < a < ?

Note that, even for perfectly balanced loads, eq. (25) does not agree with (7) since the objective functions J1 and 5 3 are different. While J 3 is intended for minimizing the sum of the three rms line currents, 51 tries to individually minimize the rms value of each phase current.

3 Practical Implementation In order to test the proposed open-loop control algorithm, two small-scale prototype versions have been developed. A single- phase version was first designed, built and tested, before un- dertaking the full three-phase prototype. The hardware and software aspects will be discussed separately.

3.1 Hardware In this section, only the three-phase prototype will be described, since the single-phase hardware is, with minor exceptions, a sub- set of the former. A block diagram of the 220V/6KVAR com- pensator is shown in Figure 5.

The zero-crossing detector is fed with the line-to-line volt- ages producing three, TTL-level, square waveforms in phase with their respective AC voltages. The necessary isolation is obtained by means of optocouplers. These signals are used for: triggering the analog-to-digital converter, interrupting the microprocessor and synchronizing the firing circuits.

The blocks labeled SYNC. PHASE 1 to 3 generate a triggering signal delayed from the peak voltage in accordance with the data available at the microprocessor's %bit ports shown as PORT 1 to 3. Different ports are provided for each phase in case more complex control algorithms are designed in the future. If the bi- nary data equals 0 then the firing pulse is issued at peak voltage, hence providing the maximum possible current in the TCR. If the data is 255, then the pulse is produced in the zero crossing of the voltage and the current in the T C R will be zero.

Two versions of these synchronizing blocks have been devel- oped. The first one is based on a PLL multiplier whose output frequency is 1024 times that of the mains frequency. This out- put acts as the clock signal of a counter whose binary state is compared with the &bit port data. The second version is based on a local oscillator, in order to avoid the instability detected in the PLL multiplier due to environmental electromagnetic noise. The oscillator is adjusted to the same frequency as that of the PLL and its output applied to a descending counter, pre-loaded with the port data. The counter produces a signal when zero is reached.

The firing signals from the synchronizing blocks are then mod- ified in the pulse shaping blocks. The single pulses applied to their inputs are converted into trains of pulses in order to provide a safer firing of the triac valves. The VALVES block contains, in addition to the valves, amplifying circuits which drive the pulse transformers used to isolate the hardware from the mains volt age.

Conditioning of the currents required by the control algorithm is performed in the CURRENT MEASUREMENT block. Ac- cording to eq. (25), the difference between line currents, rather

%8

3 2.5 KVCIr 3 8 2 KVCIr

1 1 -

1 2 1 1 - T 1

7 ...........................

F C ]

- :

’ L---.l i I

F I R I N G T R I G . CINCLE

I R I N G PUI SE 5 H O P I N C

T R I C . 3 OUT 3,

I D F I R I N G TRIG. , T R I G . 2 our 2.-

I T R I G . 1 OUT 1..

F I R I N G T R I G .

i l l : .................................

TO LOAD

Figure 5: Block diagram of the three-phase prototype

than line currents themselves, is measured. The signals 11 - I2

and Zz - 1 3 are obtained by properly wiring the secondary wind- ings of the current transformers. The remaining difference, 13 - 11, is obtained by the control software. These signals are scaled to appropriate levels for the analog-to-digital converter in two stages, the first one being a differential amplifier, to over- come possible noise problems.

Finally, the control algorithm has been implemented on a 8088, lOMhz personal computer to which two conventional plug- in cards have been added to allow for ADC and digital I/O. The 12-bit ADC card is able to perform direct memory access simpli- fying in this way the software duties. More powerful processors currently available should allow real-time solution of the unbal- anced case (eq. (22)) by means of a reliable iterative process (e.g., Newton-Raphson).

Once the software is completely debugged there is no need to use the PC resources (hard disk, screen, etc.) and a customized stand-alone processor would suffice.

3.2 Software Solution of equations (7) and (25), for the single-phase and three-phase version respectively, has been programmed in assem- bler. Except for the higher number of computations in’volved, solution of both equations is conceptually equivalent. Hence, for simplicity, only the implementation of eq. (7) will be described.

The left side of this equation, which depends on system con- figuration, is computed “off-line” and stored in a “look-up” table ( I L ) with 256, 32-bit integer words. If appreciable voltage vari-

969

ations are to be expected, then this table should be updated “on-line”.

The measured current, i,, is sampled 128 times each cycle and stored in the processor’s memory. This task is cyclically performed by the DMA controller without CPU intervention, and is synchronized with the voltage zero-crossing. Then, the L- th position of this array ( S ) contains the sampled value i,(kAt), where At = ~ 1 6 4 .

Due to the symmetry of the integrals on the right side of eq. (7), the CPU is, meanwhile, able to compress the 128-word array S into a shorter 32-word array I defined as

Z(Z) = S(Z + 32) + S(96 - i) - [S(i + 96) + S(32 - i)] The DMA counter allows synchronization of the CPU with the DMA sampling process.

Once a complete cycle is sampled, the processor must compute the firing angle within 5 msec., i.e., before the next peak of the voltage. This is done by successively adding the elements of I and comparing this cumulative sum with the respective element of I L . That is, for each L, the expression

k

I= 1

is evaluated and, when a change of sign is detected, a linear in- terpolation between the last two values gives the optimal gating angle.

Since integer arithmetic has been used throughout, this search process takes about 1 msec. in the worst case.

Figure 6: Response to a variable inductance

Figure 7: Response to a resistance in parallel with a variable inductance

4 Test Results

Before prototype construction was undertaken, several simula- tions were run to ascertain the effectiveness of the control strat-

Curve A of Figure 6 represents a purely inductive load in- creasing linearly. The total current drawn from the bus is given by curve B. Since the gating angle applied during any cycle is computed on the basis of the former cycle, the solution will be completely optimal only at the steady state. Furthermore, as the algorithm has no information at the beginning, a is meaningless during the first cycle.

Figure 7 shows a load, initially resistive, whose power factor is progressively deteriorating. Note how the total line current remains practically constant.

In order to verify the optimality of the algoritm, many tests were repeated perturbing the computed a by small amounts &Aa. As expected, the rms value of the total current using the perturbed a was always greater than that of the optimally computed angle.

The next figures are hardcopies of experiments performed in the laboratory with both the single-phase and the three-phase prototypes. Tests carried out with the single-phase proptotype have been more extensive due mainly to limitations in the data- logging equipment (actually a spectrum analyzer with only two

egy.

.............................................................................................. i 1OA . . i . . . . . . 1 .:. . . . . . . ;. . . . !... .. ..I.. . . j . . ..:... ..... ;.. . . . i ......... i

. . . . . . . . . . . ._: . . . . . . . . . . :.. . . . . . . . . . . ..: ........ .:. . . . . .

. ................................................................................

i

................ ....... ................... ........ i I:::.. .:. ..: ..: i ......... : ......... : .; ......... : ;-loA.i......

-40.00 -- milIis&onds -- 200.00

j 10A . . j ...... 1::;: ........I ......... I ................... i ............................. i ......... i

: . .

................................................................................................

.....................................................................

...

................. . :...... ..:. i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

........................................................................... ........... . . . . . . ....... ......... ......... ......... . . . . . . . . ......... ......... ......... -lOA.:...

I I::!: i ! i : i i i i -40.00 -- milliseconds -- 208 * 88

Figure 8: Response to the sudden connection of an inductance

.........................................................................

...... . . . . . . . . ......... .........

... ....

................................................................................................ :: ?A...; ...... 1::;:. ..... : ......... ! ......... i ......... i ......... 1 ......... i ......... i ......... i -40.00 -- milliseconds -- 208 8 88 . . . . . . . . ,...." ...........................................................................

i . . . . . . . . . . . . . . . . .

. . . : SA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................ . . . . . .y, . .: .

i

. . . . . . . . . . . . ,'I . ; I ,. .

. . . . . . . . . . .......................................................................... i -5A...i ..... .I:.:;.::: .... i ................... i ......... i . ........ i ......... i ......... i ......... i -40.00 -- milliseconds -- 208.88

Figure 9: Response to an inductance randomly switched

input channels). The upper trace of Figure 8 shows the sudden connection of

an inductance in parallel with a resistive load. The lower trace proves that, except for the dc offset, the reactive component of the load current is perfectly compensated one cycle after the inductance is connected.

In Figure 9 an inductance is arbitrarily switched on, off and then definitively connected. The one-cycle delay is perfectly appreciable in the lower part. It may be also noted that, before the first switching, a residual current is drawn from the bus. This is due to the fact that , foreseeing future applications, the TCR rating is larger than that of the fixed capacitor and, hence, cr > 0 in absence of load. Moreover, as the inductive load connected is not large enough, ct < ~ / 2 in the right side of the figure. This explains the harmonic content of the total current, particularly considering that this experiment corresponds to the single-phase prototype. For a three-phase TCR, lower harmonics would be injected into the network, provided carefully designed filters are installed.

Finally, Figure 10 shows one of the T C R line currents (lower trace) in response to the sudden connection of a symmetrical inductance to the three-phase prototype (upper trace). Since a > 7r/3 in presence of this load, the two single components of the TCR line current are perfectly visible in the second half of the lower curve.

970

.....aA.. ....... .... ................................................................................... : . _ _ . :._....

: , : .................... . ....

.......... ......... ............................. ......... ......... ......... ....... ...........................

...... ......... ......... i ......... i ......... i

:

188.96

.... ........ ........ ......... ....... ........ ........ ......

..... .... ........ ..... ...... ....... ........

...... ......... ....... ......... ........ ......... .........

Figure 10: Example of the TCR line current for a > 7r/3

5 Conclusions

Most earlier approaches to power factor correction do not con- sider the nonsinusoidal nature of many loads currently in use. Besides, in computing the firing angle of a TCR, only the fun- damental component of its current is taken into account.

I t has been shown in this paper that, as long as supply volt- age waveform is not appreciably distorted, a TCR triggering an- gle can be computed which optimally compensates for rapidly changing arbitrary loads. Optimality refers here to minimizing the rms value of the total current taken from the feeder.

Both single-phase and three-phase microprocessor-based pro- totypes have been built. Simulation and experimental results have been presented which show tha t the proposed feedforward control strategy achieves the expected performance.

An industrial SVC should obviously include Bome additional refinements. For instance, if the bus short-circuit capacity is not large enough compared to the SVC rating, then more accurate results would be obtained by feeding the voltage peak value to the processor, since i t affects the optimal gating instant. Fur- thermore, detailed, system-dependent simulation studies should be carried out in order to properly design the required filters.

6 Acknowledgements

This work has been financially supported by the Spanish OCIDE under PIE grant No. 132126. Thanks are also due to Sevillana de Electricidad, the local utility through which this project was coordinated.

References

[l] Miller T. E., ed., “Reactive Power Control in Electric Sys- tems” , Wiley-Interscience, 1982.

[2] Gyugyi L., “Power Electronics in Electric Utilities: Static Var Compensators”, Proc. of the IEEE vol. 76(4), pp. 483- 494, 1988.

[3] Gyugyi L., Otto R., Putman T., “Principles and Applica- tions of Static Thyristor-controlled Shunt Compensators”, IEEE Trans. on Power Apparatus and Systems vol. 97(5), pp. 1935-1945, 1978.

97

[4] Westinghouse Elec. Corp., “Evaluation of Advanced Static Var Generators”, EPRI Report EL-3397, 1984.

[5] El-Sharkawi M., et al., “Development and Field Testing of an Adaptive Power Factor Controller”, IEEE/PES Winter Meeting, paper 87WM226-4.

[6] Gueth G., et al., “Individual Phase Control of a Static Compensator for Load Compensation and Voltage Balanc- ing and Regulation”, IEEE/PES Winter Meeting, paper 87WM042-5.

[7] Paziuk L., Chikhani A., Hackam R., “An Expert Microprc- cessor Controlled Voltage Regulator for Energy Conserva- tion and Demand Reduction in Distribution Feeders”, IEEE Trans. on Power Delibery vol. 4(4), pp. 2222-2228, 1989.

[8] El-Bolok H., Masoud M., Mahmoud M., “A Microprocessor-Based Adaptive Power Factor Corrector for Nonlinear Loads”, IEEE Trans. on In- dustrial Electronics vol. 37(j) , pp. 77-81, 1990.

[9] Shepherd W., Zaid P., “Energy Flow and Power Factor in Nonsinusoidal Circuits”, Cambridge Univ. Press, 1979.

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Antonio G 6 m e z Expdsito was born in A n d ~ j a r , Spain, in 1957. He received his electrical engineering degrees from the University of Seville. Since 1982 he has been an Assistant and Associate Professor at the Dep. of Electrical Engineering, Uni- versity of Seville. His primary areas of interest are sparse matri- ces, parallel computation, reactive power optimization and state estimation. Francisco Gonzdlez Vdzquez was born in La Coruiia, Spain, in 1942. He received his electrical engineering degrees from the Universities of Madrid and Seville. Since 1968 he has been an Assistant and Associate Professor at the Dep. of Electrical En- gineering, University of Seville. His primary areas of interest are network theory and electrical instrumentation. Carlos Izquierdo Mitchell was born in Seville, Spain, in 1936. He received his electrical engineering degrees from the Univer- sity of Madrid. Since 1967 he has been part-time Professor at the Dep. of Electrical Engineering, University of Seville. His primary areas of interest are electrical machines and energy sav- ing. Tom& Gonzdlez Garcia was born in Jerez de la Frontera, Spain, in 1963. He received his electrical engineering degree from the University of Seville. In 1989 he joined the Network Operation Dep. of Sevillana de Electricidad. His interests in- clude power electronics, and microprocessor applications. E’rancisco del Pozo Madrof ia l was born in Seville, Spain, in 1964. He received his electrical engineering degree from the Univ. of Seville. In 1990 he joined the Inst. Nacional de Tkcnicas Aeroespaciales where he is involved with the appli- cation of solar cell arrays and power electronics.

I