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setTDI u1.mbist-csr start setTDI u1.alg walk1 drscan runtest 10000 set result [getTDO status] If {$result != pass} puts "memorybist failed"
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HDL
EMS
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•Changing temp • Std. FR4, multi-IC signals •Commodity LDOs, DC/DC • Tin Can Osc, System origin clocks •JTAG assisted Functional/BIST
•Stable temperature •50ohm ZT DUT card design, dedicated • Low noise Power, DC/DC converters • Perfect Low jitter, 50/50 duty clocks • BIST/Compression vectors, delay test
On-Chip test via IEEE 1149.1 - the lowest common denominator
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IP Block
TDR
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IP Block
TDR
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BIST
TAP
TDR Register
Logic block
IC
IC www.intellitech.com
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P1 PRBS
TAP www.intellitech.com
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IP BLOCK IC2
IC1
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HSIO Test IP
BLOCK
IC2
Far End
Loopback
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BSDL for Internal JTAG TDR registers - for BIST/PLLs/SERDES IP blocks MNEMONICS for JTAG registers - Easy to remember words Package files for on-chip Infrastructure IP blocks - self-contained definitions for IIP (Infrastructure IP) PDL Script files for device initialization and IIP access - operates on registers, packages, Mnemonics
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PCB Level
ObstacleLogicBIST
MemoryBIST
SystemReset
VoltageMonitor
SysReset
PCB Level
Obstacle
IC1
BOUNDARY REGISTER
TAP
INIT-DATA REGISTER
IR & Decode & Muxing
BIST Failure Data
For ATE
User Defined Chain(s)
DACADC0
1
PLL
0
1
On-chipReset via
TAP
PRBS
Protocol
Swing
CMMV
ECIDUnique ID
AC/DC
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New standard INIT_DATA & INIT_STATUS TDRs New instructions,
INIT_SETUP/INIT_SETUP_CLAMP/INIT_RUN -Use between PRELOAD and EXTEST - Turn off PLLs
-Setup I/Os (Vcm, Vswing, protocol…. )
INIT_SETUP/INIT_SETUP_CLAMP access INIT_DATA - Uses TAP, CE, power - INIT_DATA bits control the above INIT_RUN access INIT_Status register. Can clock TCK in RTI. - Pass/Fail, Done – other bits as needed
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package SERDBIST is use STD_1149_1_2013.all; end SERDES; package body SERDBIST is use STD_1149_1_2013.all; attribute REGISTER_MNEMONICS of SERDBIST : package is "OnOff (ON (1), OFF (0));" attribute REGISTER_FIELDS of SERDES : package is "serdes_bist [4] ( "& "(Local_Loopback [1] IS (3) DEFAULT(OnOff(ON)) ), " & "(BER_en [1] IS (2) DEFAULT(OnOff(OFF)) ), " & "(GoDone [1] IS (1) DEFAULT(OnOff(OFF)) ), " & "(Pass [1] IS (0)) );" end SERDBIST;
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iPDLLevel 0 -version STD_1149_1_2013 iProcGroup SERDES iProc serdes_bist { Local BER } { # Commented section from BSDL for reference #"(Local_Loopback [1] IS (3) DEFAULT(OnOff(ON)) ), " & #"(BER_en [1] IS (2) DEFAULT(OnOff(OFF)) ), " & #"(GoDone [1] IS (1) DEFAULT(OnOff(OFF)) ), " & #"(Pass [1] IS (0)) );" iWrite Local_Loopback $Local iWrite BER_en $BER iWrite GODone ON iApply iRunLoop 100000 ;# use TCK cycles iRead GoDone 0 ;# 0 for DONE 1 for 'busy' iRead Pass 1 ;# 1 for pass 0 for fail iApply
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TypeC.BSDL TypeC.BSDL
U1 PCIe
U2 SRIO
U3 U4
iProc init_setup {} { iWrite IO1 PCIe iApply }
iProc init_setup {} { iWrite IO1 SRIO iApply }
IO1 IO1
U3.PDL U4.PDL
Board.PDL
iCall U3.init_setup iCall U4.init_setup
Board Test Engineer Developed via Software or from Templates from IC Vendor
Board Test Engineer Developed via Board Test Software, Automatically, assisted or manually
Why can’t I/O settings be delivered in BSDL?
I/O need to be Programmed at Board level
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Basic Register Fields INIT_DATA TDR
attribute REGISTER_FIELDS of INIT_Example : entity is "init_data ( "& "(Clock[5] IS (504 DOWNTO 500) ), "& "(Protocol[3] IS (302 DOWNTO 300) ), "& "(Voltage[2] IS ( 101 DOWNTO 100) ), "& "(Reserved [20] IS ( 19 DOWNTO 0) ) "& ");"
BSDL syntax for "INIT_DATA" and user defined TDRs BOUNDARY TDR
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MNEMONICS
attribute REGISTER_MNEMONICS of SERDES : package is " Protocol ( " & " OFF (000) <I/Os powered down>, "& " PCIe (001) <PCI Express>, "& " SATA (010) <SATA>, "& " SRIO (011) <Serial RapidIO>, "& " XAUI (100) <XAUI>, "& " Rsvd1 (101) <Undefined, do not use>"& )," & "Clockset ( " & " F125Mhz (00111), "& " F100Mhz (10101), "& " Illegal (00000) <Do not use!>)";
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Basic Register Fields with Mnemonics attribute REGISTER_FIELDS of INIT_Example : entity is "init_data ( "& "(Clock[5] IS (504 DOWNTO 500) Default(Clockset(100Mhz) ), "& "(Protocol[3] IS (302 DOWNTO 300) Default(Protocol (off) ), "& "(Voltage[2] IS ( 101 DOWNTO 100) RESETVAL(11) ), "& "(Reserved [20] IS ( 19 DOWNTO 0))"& ")" & "myTDR ( "& "(Addr[64] IS (163 DOWNTO 100) ), "& "(Data[64] IS (227 DOWNTO 164) ), "& "(WE[1] IS (228) RESETVAL(1) ), "& "(TempMON[7] IS (236 DOWNTO 229)) "& )";
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Device PDL (Procedure Definition Language) - Board specific
Proc init_setup {} { iWrite Clock F125Mhz # use of mnemonics iWrite Voltage 0H01 # use of values iWrite Protocol PCIe iApply } Proc init_status {} { iRead Status(1) Pass # use of mnemonics iApply }
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Some PDL Commands iWrite <reg> <value> | mnemonic iRead <reg> <expected> | mnemonic iApply # perform DR scan RTI-RTI iPrefix <dotted path> # iPrefix bank0.serdes iReset # Test Logic Reset iEndState RTI | PDR # set end state iRunloop <TCK-Count> # Loop in RTI iCall <iproc name>
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attribute Register_Association of INIT_EXAMPLE : entity is -- Port ID 'VDD_IO1' is the power source for upper bank of I/O -- '1' = large package, '0' = small package. "upper_data_bus_En : PORT (Vdd_IO1), "& "IO_En : PORT (Vdd_IO1), "& "VSEL_bits(4) : PORT (VSEL_pin(4)), "& "VSEL_bits(3) : PORT (VSEL_pin(3)), "& "VSEL_bits(2) : PORT (VSEL_pin(2)), "& "VSEL_bits(1) : PORT (VSEL_pin(1)), "& "VSEL_bits(0) : PORT (VSEL_pin(0)) "; www.intellite
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Attribute REGISTER_ASSOCIATION of MyChip : entity is "mem1.MBIST_CTRL : sysclock (F125MHz_in), "& "mem2.MBIST_CTRL : sysclock (F125MHz_in) ";
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3 SERDES with init_data Registers Common PLL
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---------------------------------------------------------- -- Package file including single SERDES segment -- and a 3 SERDES plus clock segment. -- Copywrong of the XYZ corp. ---------------------------------------------------------- PACKAGE XYZ_IO IS USE Std_1149_1_2013.all; END XYZ_IO; PACKAGE BODY XYZ_IO IS USE Std_1149_1_2013.all; attribute REGISTER_MNEMONICS of XYZ_IO : package IS "SerDes_Protocol (off (000) <Powered down>, "& " PCIe (001) <PCIExpress>, "& " SATA (010) <SATA>, "& " SRIO (011) <Serial RapidIO>, "& " XAUI (101) <XAUI>, "& " Resvd1 (100) <Undefined behavior - Do Not Use>, "& " Resvd2 (11X) <Undefined behavior - Do Not Use>), "& "SerDes_TX_Outputs (off (00) <Powered down>, "& -- Output driver swing level " Full_Swing (01) <100% Swing>, "& " Swing_p75 (10) <75% Swing>, "& " Swing_p527 (11) <52.7% Swing -– Not legal if XAUI is protocol>), "&
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attribute REGISTER_FIELDS of XYZ_IO : package IS "Channel [5] ( "& "Protocol[3] (2, 0, 1) IS DEFAULT (SerDes_Protocol (PCIe)) "& " RESETVAL(SerDes_Protocol (off)), "& "TX_Swing [2] (3, 4) IS DEFAULT (SerDes_TX_Outputs (off)) "& "), "& END XYZ_IO; --------------------------------------------------------------------------------
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Register assembly – bits predefined defined – length calculated by BSDL reader
Use XYZ_IO.all; Use XYZ_PLL.all; -- stuff removed for brevity attribute REGISTER_ASSEMBLY of INIT_Example : entity is "init_data ( "& "( reserved[105] )" & "( USING XYZ_IO ), " & "( XYZ_IO.SerDes( 0) is Channel ), " & "( USING -), "& "( dummy[1] ), " & "( USING XYZ_IO ), " & "( Array SerDes(1 TO 2) is Channel), " & "( USING XYZ_PLL), " & "( P1 is Settings), " & ");" SERDES SERDES SERDES Rsrvd TDI TDO PLL
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<type assignment>::= NOPI | NOPO | NOUPD | MON | PULSE0 | PULSE1 | SHARED <reset assignment>::= PORRESET | TRSTRESET | TAPRESET | CHRESET <domain assignment>::= <association type> <left paren> <association name> <right paren> <association type>::= DOMAIN | DOMAIN_EXTERNAL | SEGMENT <association name>::= <VHDL identifier>
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Boundary-scan REGISTER_ASSEMBLY example. Continuing the segmented boundary-scan register example from B.8.14.2, the segments defined there could be assembled, with the segment exclusion cells on the one segment, as follows. attribute REGISTER_ASSEMBLY of Chip_2013 : entity is -- Register Assembly of Boundary-scan register "boundary ( "& -- TDI, starting in NE corner and going clockwise "(North_side IS north), "& "(NEast_side IS east1), "& "(SEast_incl IS SegSel DOMAIN(DDR1) CHReset), "& "(SEast_side IS east2), "& "(SEast_mux IS SegMux), "& "(South_side IS south), "& "(West_side IS west) ) "; www.intellite
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TSV/uBump
Reg_1500
SI SO WSC
Reg_1500
SI SO WSC
Reg_1500
SI SO WSC
3210
WSC:Shift_1500
Capture_1500Update_1500
Reset*TCK
SI
SO
Sel_WSP
Gating Gating Gating
Gate_WSPC UC U
C U
C UC U
C U0
1
open
core core core
“rea
dy_t
o_sc
an”
Start_1500 End_1500
C UC UB
CA
WSC
SI SOReg_1500S
Gating
DIE2
DIE1
DIE3 DIE4
corewww.intellite
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Core1 Core2
Core3 Core4
POD
# vendor supplied reg to temp conversion proc Reg2Temp { $regval $CorF } { … … vendor conversion code } iExport -begin # this proc returns a temperature and # high level warnings could be specified iProc init-setup-temp-check { } { iRead tempreg iApply set val [iGet tempreg] # convert reg value to temperature in Celsius set temp [Reg2Temp $val CEL] #if {temp > 70} { #puts "Temperature is excessive $temp" #} return temp }
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2.5V
INPUT ( Open0)
INPUT (Open1)
OUTPUT2
Bidir with Pull0
Bidir with Pull0
A
B
C
D
Control
Bidir with Pull0 Obstacle
INPUT ( PULL1)
POWER_POS1.8V www.intellitech.com
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D
+
-
MODE=1
VDD
HSIO
GND
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BER XMIT
BER RCVR
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IC1
ABCD
POWER_POS
DC/DC Converter
3.3V
POWER_0
IC2LINKAGE_INLINKAGE_INLINKAGE_INLINKAGE_IN
VREF_INDC/DC
Converter
2.5V
VREF_OUT
INPUT
INPUT
BIDIRBIDIRBIDIRBIDIR www.intellite
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