Ideal Grounded Supercapacitor Using a DVCCTA

JOURNAL OF TELECOMMUNICATIONS, VOLUME 22, ISSUE 2, NOVEMBER 2013

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Ideal Grounded Supercapacitor Using a DVCCTA

R.Nandi, Sagarika Das and P. Venkateswaran

Abstract- The simulation of grounded ideal frequency dependent negative resistor (FDNR) type supercapacitor(D) with driving point admittance function of Y(s) = s2D is proposed.The design uses a single differential voltage current conveyor transcapacitive amplifier(DVCCTA) building block with a single grounded passive RC section. Effects of the device port errors(e) and parasitic capacitors have been shown to be negligible. Some applications of the supercapacitor in high –Q tunable selective filter and quadrature oscillator design along with experimental results are presented.

Index Terms – Synthetic supercapacitor, DVCCTA, Active Filter, FDNR

1 Introduction

The FDNR type Supercapacitor element had been shown to be quite useful in areas of analog signal processing and filtering applications[1-8 ] following the concept of Bruton . A number of supercapacitor simulation schemes are presented in the recent past using various types of building blocks e.g. voltage operational amplifier[3 ], second generation current conveyor[4-6 ], DVCCS [7],current feedback amplifier [8,9 ], operational transresistive amplifier OTRA[10] and the current backward transconductance amplifier CBTA[11 ].

The DVCCTA device is a relatively new active building block[12,13 ] suitable for various analog signal processing circuit design.Presently this device is being used primarily in the transconductance (gm) node; here we intuitively modified the device in its internal circuitry to operate in a trans capacitive (Cm) mode with a view to design newer variants of synthetic components and active filter structures .Two such new ideal supercapacitor simulation schemes are presented here using a single such transcapacitive mode of the DVCCTA. These circuit scheme are quite simple involving only one grounded passive –RC section with no component matching constraint while the supercapacitor(D) is tunable by the resistor .Analysis had been further carried out taking into account the device port mismatch errors(𝜖 ≠ 0) and byexamining the port parasitics that appear in the form of shunt RC arms[8,14,15].It is shown that effect of these

nonidealities are quite insignificant which yield extremely low active sensitivity , the losslessness of the simulated supercapacitor (D) may be preserved with appropriate design ; this feature is experimentally verified by designing some high quality (Q) filter using the supercapacitor.For experimental work ,the desired building block topology had been hardware fabricated in the laboratory by using the readily available unity current gain AD844[14] integrated circuit chips for their superior quality e.g. high slew rate and accurate pot transfer property [ 8,9,16]. The proposed designs were also tested with PSPICE macrocircuit model [16,17],for supercapacitor based high Q bandpass (BP) and Band reject (BR) characteristics; the design of grounded shunt RD type tunable quadrature oscillator is also presented. 2 Analysis The proposed simulation circuit is shown in Fig.1 where the nodal relation of the DVCCTA device are Vx = α (V1-V2), Iz=βIx, Io= δVz(sCm) and Iy1=Iy2=0;the port transfer ratios may be postulated by some mismatch errors (µ) as α =(1- εi), β= (1- εv)and δ= (1- εo ).These errors are usually extremely low[8,14] |ε| << .1 The parasitic components (3pF≤Cp,z≤9pF and 2MΩ≤rp,z≤6MΩ) appear as shunt elements as shown by dotted line [ 16]. Initial analysis assuming ideal condition µ ≈0, Cp,z≈0 and gp,z≈0 yield the driving point admittance for both circuits in Fig.1 as Yi = s2 D; D= RCmC (1)

R.Nandi(correspondingauthor) P.Venkateswaran:Dept. of Electronics & Telecommunication Engrg., Jadavpur University,Kolkata-‐‑700032,India Sagarika DasDept.of Electronics &Communication Engrg., B.P.Poddar Inst.of Mgmt.&Tech., Kolkata-‐‑700052, India


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Thus Yi represents an ideal grounded supercapacitor which is tunable by single grounded resistor ( R) without necessitating any component matching requirement; the capacitor (C) is also grounded a feature suitable for microminiaturization [18] . it may be mentioned here that the DVCCTA is an enhanced version of the unity gain current conveyor(CC) having a high input impedance differential stage at front end and a transcapacitive(Cm) stage at the back end; hence the AD844 or IC chips may be the appropriate device for its ready implementation.

(a)

(b)

Fig.1 Proposed Supercapacitor (D) simulation

3 Effects of Non idealities

We first examine the effects of the finite port errors(𝜖≠0); re analysis shows a modified admittance function given by Yi'=(α β δ)s2D for both circuits.albeit the magnitude of the supercapacitor is slightly altered as D'= (1- µt)D; µt ≈ µi+µv+µo; however its lossless quality is preserved.

Next the effects of the parasitic components are examined by writing gz=1/rz ; for Fig.1(a) the modified driving point impedance function( Zi' ) as

Zia' ={sRCp+1+a}/[s2D(1+b)+s{mCp+(1+a)Cz}+gz(1+a)]..(2)

where a = R/rp << 1, b = CzCp/CmC<<1 and m = R/rz<<1. Since in practical design we select R in kΩ, and C and Cm in nF ranges . location of the zero in eq.(2) appears at ωp≈1/RCp i.e. fp (typical)≈ 39 MHz if R =1KΩ and Cp = 5 pf. If the operating frequency range is restricted below this value (ω<ωp), we simplify the admittance function in eq.(2) as Yi' ={sRCp+1+a}/[s2D(1+b)+s{mCp+(1+a)Cz}+gz(1+a)]..(3)

The quality of the modified supercapacitor in Fig.1(a) is obtained as

qa = √(CmCR/rz)/ Ct …………(4)

where Ct is the total value of the parasitic capacitance given by Ct = Cz(1+a)+m Cp ………(5)

Thus one may obtain a large qa for the simulated supercapacitor ,e.g. typically if R = 1kΩ, rz= 5MΩ,Ct ≈ (5+5)pF,and C=Cm = 10 nF,we get 100 ≤ qa ≤300.Similar analysis yields the impedance of(𝑍!"! ) for the circuit in Fig.1(b); after writing gp = 1/rp we get

Zi'b ={sRCz+1+m}/[s2D(1+b)+sCt+gp(1+m)] …(6)

For operating frequencies ω<1/ RCz, eq.(6) simplifies to

Y i'b = s2D(1+b)+sCt+gp(1+m …….. (7)

Thus for both the circuits, the parasitic capacitors introduce nonideality in the supercapacitor quality since D element is shunted by parallel combination of Ct and rp,z ; the quality factor (qb) for the impedance for eq.(7) is

qb = √( CmCR/rp)/ C\t …. (8)

By similar reasoning we observe that very high quality (qb>>1) supercapacitor element is simulated in Fig. 1(b). it is therefore suitable for the designer to utilize these grounded high quality D elements for high selectivity filters.

4 Filter Design

Both the proposed circuits had been utilized in the design of good quality bandpass (BP) and band reject (BR) filters; the BP filter is built with the supecapacitor being shunted by a resistor(Ro) and the BR filter is designed with RD series combination, as shown in Fig.2,whrein the test responses obtained with both hardware test and PSPICE simulation are shown ; Table-1 shows some pertinent design equations. It may be seen that with appropriate component selection ,the effects of the parasitics can be minimized significantly which enables the designer the feature of single resistor fo tunability; experimental verification for fo tuning in the range of 100kHz-900kHz with good quality (1 ≤ Q ≤6) had been carried out. The possibility of designing a shunt RD

Zin

R

y2 0

DVCCTA (sCm) y1 x z

Cz

Cp

C

Zin

y2 0

DVCCTA (sCm) y1 x z

Cz

Cp

C

R


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sinusoid oscillator with quadrature wave response is also verified as shown in Fig.2

(a)→KHz

(b) → KHz

Fig.2 Supercapacitor based filter design: (a) BP response tuned at fo=500KHz ; Q ≈ 6.6 with C=Cm=330pF, R=Ro=1KΩ, Co=50pF (b)BR response tuned at fo=460KHz; Q≈ 7.2 with C=Cm=347pF, R=Ro=1KΩ, Co=2.5nF (c) Quadrature oscillation at Vx using shunt RD combination tuned to fo=750KHz tested with C=100pF, R=1KΩ, Ro = 4.5KΩ ; fo-tuning verified in the range 300KH~1.2MHz by varying grounded-Ro ▬ Simulation ● Hardware test (d) spectral response of oscillator wave: THD≈3.3% measured 5 Conclusion

Using a single DVCCTA active building block and only the minimum number of all grounded passive RC components, two new design for ideal grounded supercapacitor type FDNR element simulation is proposed wherein the active device had been configured intuitively in the transcapacitive mode.

(c)

The use of the CFA device had been found to be quite convenient for deriving this mode owing to the superior terminal properties [8,14] of the AD844 device. Details analysis of the proposed designs taking into effect of the device parasitic, show that the nonideal effects are quite insignificant. Applications of the supercapacitors in high quality BP and BR filter design examples are presented.

(d) → Hz

0 -25 -50

0 1M

M 2M 3M

7 0

Zin

Fbp

Fbr

T

Time (s)0.00 1.00u 2.00u 3.00u 4.00u

Output

-8.50

0.00

8.50

0 2.5u 5u 7.5u 10u Time(s)


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TABLE 1

Summary of Supercapacirtor design equations under nonideal conditions and filter design example Fig.1 Yi(ideal) Zi(Nonideal) Filter Transfer function (a) 𝑌! = 𝑠!𝐷 Zia' ={sRCp+1+a}/[s2D(1+b)+sCt+gz(1+a)] Fbp = sCoRo/[DRo+sRoCo(1+x) +(1+a)σ] 𝐷 = 𝑅𝐶𝐶! if ω<1/RCp and a<<1 ω0 =1/ 𝐶!𝐶𝑅𝑅! ≈ 1/𝐶√(𝑅𝑅! )if C=Cm

𝑍!"! = !![!!!!!!!!!!!!!]

Q = √ (CmCR/Ro)/(1+µCo ) ≈ √ (R/Ro)(C/Co)

𝑞! =!!!"/!!!!

Fbr={ s2DRo+sCtRo+1}/[S2DRo+s{CtRo+(D/Ro)}+1+µ] (b) 𝑌! = 𝑠!𝐷 Zi'b ={sRCz+1+m}/[s2D(1+b)+sCt+gp(1+m) 𝐷 = 𝑅𝐶𝐶! if ω<1/RCz and m<<1 ωo= 1/√DRo Zi'b =rp/[s2Drz+sCtrz+1)] qz = √ (CmC/Ct )>>1 qb= =√ (CmCR/rp)/Ct qp ≡ Q =√ (CmCRRo)/[CtRo+(CmCR/Co)] ≈C/C0 if C= Cm and R = R0 Note: For both Figs.1(a) and (b) - εεthe super capacitor becomes ideal with suitable component choice,e.g., Ct<<√(CCm) , 𝜇 = 𝐶t/C0, b= CzCp/CCm , a = R/rp , m= R/rz, σ= Ro/rz, 𝜇, 𝑎, 𝑏,𝑚,𝜎 ≪ 1. Ct= m Cp +(1+a)Cz.. References 1.L.T.Bruton,(1980). RC-Active Circuits: Theory and Design. Englewood Cliffs, NJ: Prentice Hall. 2.A. Antoniou, “Realization of gyrators using operational

amplifiers and their use in RC-active network synthesis”, IEEE Proc., vol.116,1838-1850,1969.

3.R. Nandi, “Novel active-R supercapacitor simulation :Applications in low-sensitivity multifunction network realization”, Electron. Lett., vol.16,570-571, 1980. 4.P.Martinek,“Lossy FDNR based on CCII(-) current Conveyor”,Proc.Int. Conf. Radioelecktronica. Brno,CzechRepublic.www.urel.feec.vutbr.cz/archive/ra2006. 5.R.Senani,“Floating ideal FDNR using only two current conveyors. Electron Lett., vol.20, 205-206,1984. 6.S.Nandi, P.B.Jana & R.Nandi, “A Novel floating ideal

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9.T.A.Abuelmatti,”New grounded immittance function simulators using single current feedback operational amplifier”, Analog.Int.Cct.Sig.Proc.,vol.71,95-100,2012.

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Ideal Grounded Supercapacitor Using a DVCCTA