Hyperlynx a PWB Design Tool

HYPERLYNX- A PWB DESIGN TOOL

Sandy Mazzola

BAE Systems Inc

HYPERLYNX

The HyperLynx suite of tools can be used in virtually any design flow to help eliminate signal integrity, crosstalk, and EMC problems early, allowing you to "get it right the first time." These simulation tools come ready to use with unprecedented ease of use, delivering high speed analysis to every engineer's desktop.

HYPERLYNX

Before layout begins (LineSim) Generation of high-speed PCB-routing

constraints (LineSim) After PCB layout (BoardSim) During system analysis of a multiple

board design (BoardSim MultiBoard Option)

HYPERLYNX VERSIONS

LINESIM LINESIM EMC LINESIM CROSSTALK BOARDSIM BOARDSIM EMC BOARDSIM CROSSTALK BOARDSIM MULTI-BOARD

HYPERLYNX

A Mentor Graphics Product Pricey Initial cost is 3K to 50K depending on

configuration 2K a year maintenance cost

HYPERLYNX - BOARDSIM

PWB Design provides 3 ASCII source files unique to ALLEGRO to a local pc

Component & connectivity data (a_c) Layout data (a_l) Outline data (a_o)

Hyperlynx ALLEGRO translator run at a local PC converts these ASCII files to HYP files

Result is an image viewable PWB layout

HYPERLYNX PRELIMINARY PROCESS

Use stackup editor to verify Power/Ground plane & signal layer assignments & add/delete layers or change type

Adjust dielectric thicknesses/constants Adjust copper thicknesses Layers are color coded Use Power supply editor to verify correct

assignment of power supply voltages

CROSSTALK - BATCH MODE BATCH MODE –select board wizard Set voltage coupled threshold and rise/fall

times – Then run Report issued showing all aggressor nets

that produce crosstalk at or greater then threshold value on every victim net

Report does not know what actually drives the aggressor nets. It assumes default rise/fall times.

Requires analysis to identify true problems.

CROSSTALK - BATCH MODE ANALYSIS

Analyze batch crosstalk results Test points may be don’t care situations Static sources not an issue Is the source Synchronus/Asynchronus ?

CROSSTALK ISSUESFORWARD CROSSTALK Forward Crosstalk = Crosstalk appearing on

the victim line at the receiver end of the aggressor line

• Function of the difference between capacitive crosstalk and mutual inductance crosstalk

• Duration = rise time of aggressor line driver• Amplitude proportional to rise time and line

length• Polarity opposite aggressor driver signal

transition polarity

CROSSTALK ISSUESBACKWARD CROSSTALK Backward Crosstalk = Crosstalk appearing on the victim

line at the driver end of the aggressor line• Function of the sum of the capacitive and mutual

inductance crosstalk currents• Duration = Twice the transition time (Time for signal to

travel down the line and return)• Amplitude = Independent of line length when line is

electrically long; directly proportional to length when line is short

• Polarity = same as aggressor driver signal transition polarity

SIGNAL INTEGRITY

Delays Overshoot Multiple Threshold Crossing Ringing

SIGNAL INTEGRITY ANALYSIS PROCESS

Select Net (sorted by name, length, or trace width)

Net now visible on PWB image with colors corresponding to layer colors

All nets can be shown Nets on a single layer can be shown by

changing all other layer colors to background color

ASSIGN DRIVERS AND RECEIVERS

Click on component button associated with that net

Select models Array of IBIS, Hyperlynx.mod and .mdl devices

along with easy models May need to obtain IBIS models from vendors Repeat for all other drivers/receivers on net

IBIS- Input/Output Buffer Information Specification

The input/output buffer information specification (IBIS) is a device-modeling standard that was developed in 1993 by a consortium of companies from within the electronic design industry. IBIS allows the development of device models that preserve the proprietary nature of integrated circuit device designs, while at the same time providing information-rich models for signal integrity and electromagnetic compatibility (EMC) analysis.

IBIS - Input/Output Information Specification An IBIS model library comes with Hyperlynx.

These models enable accurate simulations of drivers and receivers

Can be downloaded from vendor and other websites

Models provide V/I characteristics of inputs and outputs including ground clamping and VCC clamping

Models include parasitics Defaults available for rapid simulation

SIGNAL ANALYSIS MODE

After selecting net - Assign Probes Select simulation Set horizontal and vertical scales Use cursors to obtain waveform details Print or copy/paste scope display

SIGNAL ANALYSIS MODE

CROSSTALK - SIGNAL ANALYSIS MODE

Need models Enable crosstalk Set Threshold PWB image will now display aggressor

nets as dotted lines These nets will produce crosstalk at

threshold level or greater on selected net

CROSSTALK SIGNAL ANALYSIS

Cross-sectional view of traces involved in crosstalk is displayed

On PWB image, footprint view is highlighted

Make changes as necessary based on results

EMC ANALYSIS MODE

Have not used program in Spectrum Analyzer mode with antenna probes

Simulation against radiated emissions requirements

Very complicated – unbounded condition Hope to work with it in the future

LAYOUT/STACKUP DESIGN RULES GENERAL RULES -Partition Signals

- Static/Quasistatic-Low Level-High Level- Clock and high rate signals- Video and Analog-Low Level-Moderate Level-High Level- Gates- Triggers- Differential

LAYOUT/STACKUP DESIGN RULES

Digital Power and Digital Ground should be assigned planes

Adjacent signal layers should have traces orthogonal

A signal trace should ideally run over an unbroken plane layer so that the current return is in the image of the trace

A slot in the plane under a signal trace will result in significant radiation from the trace


For power not assigned to planes, use the widest possible traces (50 mils preferred) and run ground traces in parallel

Keep like signals together to the extent practical

Clocks and high rate signals on their own layer Analog and video on a separate layer

Keep low traces away from moderate and high level traces


Bury the fastest signals the deepest (bury them between the power and ground planes)

Static/Quasistatic signals can be on top and bottom layers or outside Power/Ground planes

Keep differential signals together on same layer and equal in length


Trace length to decoupling capacitors must be short

Tantalum decoupling capacitors should be located at the I/O connectors with shortest possible trace connection between connector and capacitor

The closer any trace is to a plane the better


The wider the separation between traces that can interfere, the better

It is di/dt that causes crosstalk and EMI emissions. Pay close attention to signals involving large current swings.

For boards with mixed speeds/levels, keep high speed/level circuits closest to the I/O connector.

TRACES AS TRANSMISSION LINES

PCB traces act as transmission lines when line delay is equal to or greater than ½ the rise (or fall) time

National semiconductor uses 1/3 and Hyperlynx uses 1/6

Line delay is a function of propagation speed and trace length


Propagation Speed = C/(εr)1/2

C =Speed of Light = 3 x 10 8 meters per second

εr = Relative dielectric constant

For εr = 4.1 (typical value of polyimide) signal speed = 3 x 10 8 meters/sec x 39.37 inches/meter/(4.1) ½ = 5.83 x 10 9 inches per second = 5.83 inches per nanosecond


Propagation Delay- Tpd = reciprocal = 1 nanosecond/5.83” = .171 nanoseconds per inch

Transition electrical length for a 2 nanosecond rise time is 2 x 5.83 = 11.66 inches

Critical length = ½ transition electrical length For 2 nanosecond rise time critical length is

5.83 inches

TERMINATION TYPES AND THEIR ADVANTAGES/DISADVANTAGES

Series (BACKMATCHING)- A resistor in series with the driver output that attempts to match the source impedance to the transmission line impedance of the trace

Only one component required Least current power drain Damps entire switching circuit Best for a single receiver, or receivers grouped

at last third of the line Best for CMOS to CMOS logic interfaces

TERMINATION TYPES - SERIES

Hard to select the proper resistor value (Hyperlynx shines in this application)

Lower slew rates than parallel with capacitive loads

TERMINATION TYPES - DC PARALLEL, PULLUP OR PULLDOWN

A resistor to ground or to VCC at the receiver end

• Only one component required• Easier to chose resistor value• Works with multiple receivers (anywhere along

trace)• Pullup to VCC aids sourcing; pulldown to

ground aids sinking• Connect to ground for low duty cycle; VCC for

high

TERMINATION TYPES –AC PARALEL

Reduced power compared to DC termination Easier to chose resistor value Works with multiple receivers Requires two components Hard to choose capacitor value Too small a capacitor results in

over/undershoot Not for RS422 and not for high current drivers

TERMINATION TYPES - THEVENIN

Advantages/Disadvantages about the same as DC parallel

Good overshoot protection Aids in sourcing and sinking load currents Requires two components Lowers slew rate Can bias CMOS receiver to higher dissipation

state

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Hyperlynx a PWB Design Tool