HYBRID MEMORY CUBE

Present ByRAHUL NADHEC7No:59Guided ByMr.NISHANTHDept. of ECEHYBRID MEMORY CUBEIntroductionRandom access memory(RAM)Currently using RAMsProblems with existing technologiesThe Hybrid Memory CubeHMC Architecture Through Silicon Via (TSV) TechnologyProcessor memory interactionMemory technology comparisonAdvantagesDisadvantagesConclusion

CONTENTSINTRODUCTIONNowadays we uses multi-core processors in computers for better performance. DRAM technology has been utilized as main memory in microprocessor-based systems for decades. Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a new memory technology which have three-dimensional DRAM architecture that improves latency, bandwidth, power and density. RANDOM ACCESS MEMORY(RAM)The RAM can be both read and, written, and is used to hold the programs, operating system, and data required by a computer system.

CLASSIFICATION OF RAMRAMSRAMDRAMASYNCHRONOUSSYNCHRONOUSRDRAMDDR SDRAMDDR1DDR2DDR3DDR4CURRENTLY USING RAMS1)DDR2DDR2 is the next generation of memory developed after DDRDDR2 is a 240 pin DIMM design that operates at 1.8 volts.Has pre fetch buffer size 4 bits.Starting in 2004, DDR2 was launched for use in desktops, servers, notebooks, telecommunications/networking and other platforms.The maximum memory bandwidth of DDR2 is 5.34 GB/sec at 800MHz operating frequency

CURRENTLY USING RAMS-Continue..2)DDR3DDR3 was the next generation memory introduced in the summer of 2007 as the natural successor to DDR2.DDR3 increased the pre-fetch buffer size to 8-bitsvoltage level is lowered to 1.5 V.The physical DDR3 is also designed with 240 pinsThe maximum memory bandwidth of DDR2 is 10.66 GB/sec at 800MHz operating frequency.

PROBLEMS WITH EXISTING TECHNOLOGIES

Latency (memory wall)Bandwidth related issuesPower / energyMulti-core processors generate higher random request ratesMemory capacity per unit footprintScalability of bandwidth, densities, request rates and lower latencies

THE HYBRID MEMORY CUBE

Micron's Hybrid Memory Cube features a stack of individual DRAMs connected by vertical pipelines or vias.IBMs new 3-D manufacturing technology TSV used to connect the 3D micro structure.The memory bandwidth is above 128 GB/Sec.For HMC, Area needed for 1GB is 2.56mm2 .For DDR3, area needed for 1GB is 294mm2 .

HMC ARCHITECTURE

DRAM LAYERSLOGIC BASEVERTICAL SLICESFor optimized management of refresh,Self test, error detection and correction

HMC ARCHITECTUREContinue..

Logic base contains control and access circuits built in the memory module.Wide ,high-speed local bus for data movement.Advanced memory control provides DRAM control at memory rather than distant the processor.Crossbar switch activates desired memory location.

DRAM ARRAY & ACCESSDRAM cell is made up of a single MOS transistor and a storage capacitor.The memory cell is written to by placing a 1 or 0 charge into the capacitor cell.This charge, leaks off the capacitor due to the sub-threshold current of the cell transistor.The charge must be refreshed several times in each second.SINGLE DRAM CELL

Bit lineWord lineCapacitor

Transistor

SIMPLE 4X4 DRAM ARRAY

Data I/OHOW A MEMORY LOCATION IS ACCESSED IN HMC?CPU sends address, control signals and clock to the logic base of HMC through the high speed link.The memory map in the memory controller decodes the memory address into (layer, bank, row & column).The crossbar switch activates the desired memory location.Command generator generates commands for the target memory(activate ,read ,write ,pre charge ,refresh ).The requested location is copied to the row buffer of the selected bank (memory read). The requested location of the selected bank is written by data in the row buffer (memory write).

THROUGH SILICON VIA (TSV) TECHNOLOGY

Through-Silicon-Via (TSV) is the enabling technology for the 3D integration of multiple dies into a single stack.Provide vertical electrical connectionsfrom the active side to the backside.Provides much higher input/output density than wire bonding.Inductive losses reduces.Consume less power.

TSV PROCESS AND INTEGRATION1)VIA CreationDeep reactive ion etch technology is used.2)VIA EtchingVIAS are etched during or after back end of line processing from the front side of full thickness wafer or backside of a thinned wafer. Size of etched VIA is 10-25 micrometer.3)VIA LinersTo avoid shorting to the silicon, the etched VIAS are lined with insulating layer. CVD is used.4)Depositing barrier layerFor chemically isolate semiconductor from soft metal interconnect. Titanium and Tantalum are used as barrier materials.TSV PROCESS AND INTEGRATION-continue..5)VIA FillDone by using Copper electroplating6)Remove oxide and metalChemical mechanical polishing is used.

Types of process sequencesMEMORY TECHNOLOGY COMPARISON

TechnologyVDD(V)IDD(mA)BW(GB/s)Power(mW/GB/s)DDR1(1GB Module)2.52.192.662057.06DDR2(2GB Module)1.82.885.34971.51DDR3(2GB Module)1.53.6810.66517.63HMC(4GB Module)1.29.2312886.53ADVANTAGES

Higher bandwidthHigher signaling rateLower energy per useful unit of work doneLower system latencyIncreased request rate, for many-coreHigher memory packing densityScalability for higher future bandwidths and density footprint

DISADVANTAGESCost is high (30%higher than DDR3)Designing is complex.Manufacturing issues.Need new motherboard form factor.

CONCLUSIONHybrid Memory Cube is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiencyThrough collaboration with IBM, Micron will provide the industry's most capable memory offeringThe goal is to get the first 3D chip modules to market by 2013.REFERENCESwww.hybridmemorycube.orgwww.techonicals.comwww.en.wikipedia.orgwww.engineering.comwww.ieeexplore.orgwww.google.com

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