HV MOSFET Modeling with HiSIM_HV

Benchmarks and New Developments

Ehrenfried Seebacher, Mitiko Muira Matausch, Kund Molnar2011-09-16

Hiroshima University

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• HV Transistor • Compact Modeling Requirements• HV transistor sub-circuit modeling (the reference)• State of the art HV Transistor Compact Models• HiSIM_HV 1.x and 2.x

•Benchmarking: DC, AC • Summary

Presentation Overview

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FOMs for HV Transistor Modeling

• RON (On Resistor) (high vgs, low vds, and temp.)• IDSAT (Saturation Current) ?• VT long & short• Cgg & Cgd Miller Cap • Analog parameter for long channel length• RF Parameter FT, FMAX ?

3

Model s

hould

at lea

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demon

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Process

spec

as

good

as po

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HV CMOS Transistor Types

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Small on-resistance and high BV are contrary effects. The optimization of the tradeoff between both quantities is of major interest.

The gate length is extended beyond the body-drain well junction, which increases the junction BV. The gate acts as a field plate to bends the electric field. RESURFeffect

Quasi-Saturation Effect.

Increased junction breakdown voltage (BV) of the drain diffusion is achieved by using a deep drain well

PWELL

PWELL

NWELL

Nwell

Nwell

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Sub-circuit Modeling

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Sub-circuit Model Features and Limitations

HV MOS Transistor Model Features:•Basic geometrical and process-related aspects such as oxide thickness, junction depth, effective channel length and width•RON modeling•Quasi saturation region and the saturation region •Geometry scaling, Short-channel effects •1/f and thermal noise equation•Temperature Modeling for RON, VT, IDSAT•High Voltage Parasitic Models•Bulk (Substrate) current•Effects of doping profiles, substrate effect•Modeling of weak, moderate and strong inversion behavior•Parasitic bipolar junction transistor (BJT).

Model Limitations:•RF modeling•SH modeling•Cgd, Cgg ……•Graded channel•Impact ionization in the drift region•High-side switch (sub-circuit extension needed).

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State of the Art HV Compact Models and new Developments

EKV HV Transistor–Under development within the EU Project COMON

“A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET” Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, and Mingchun Tang

PSP HV – Transistor Model–In development based on PSP surface potential model

MM20–asymmetrical, surface-potential-based LDMOS model, developed by NXP Research

HiSIM_HV–CMC Standard model version 1.1.2 and 1.2.1–Version 2.0.0 in evaluation

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Channel-Length ModulationOverlap Capacitance

Beyond Gradual-Channel Approximation

Complete Surface-Potential-Based Model

fS0 : at source edge

fSL : at the end of the gradual-channel approx.

fS(DL) : at drain edge (calculated from fSL)

Extension of Bulk-MOSFET Model HiSIM2

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HiSIM-HV

(Asymmetric) (Symmetric)

a few hundred volts > Bias Range > a few volts

Vgs,eff = Vgs – Ids x Rs

Vds,eff = Vds – Ids x (Rs + Rdrift )

Vbs,eff = Vbs – Ids x Rs

potential drop

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Consistent Modeling in Drift Region

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Hiroshima University &

Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.

Ldrift

Ndrift

VDDP

Potential drop in the drift region

Vds

Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.

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HiSIM reproduces fS(DL) calculated by 2D-device simulator.

: potential determining 　 LDMOS characteristics

fS(DL)

f S(D

L) [

V]

fS(DL)

f S(D

L) [

V]

f S(D

L) [

V]

f S(D

L) [

V]

Vgs [V] Vds [V]

Key Potential Values

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VDDPVDDP

HV HV

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Modeling of Rdrift

HiSIM_HV 1.0.0 Series

Bias Dependence is modeled based on principle.

Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.

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Quasi-saturation behavior of LDMOS is reproduced.

: 2D-Device Simulation Results

: HiSIM-HV Results

I d [

A]

Vgs=2.5V

Vgs=5V

Vgs=7.5V

Vgs=10V

gd [

S]

Accuracy Comparison of Ids-Vds

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Relatively Low Breakdown Voltage

Relatively High Breakdown Voltage

Current-Voltage Characteristics

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Empirical Model: Issues

Care must be taken when adjusting critical parameters describing the Vgs dependence.

Ids - Vgs

Gm vs. Vgs

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Model Benchmark Output CharacteristicH

iSIM

_HV

1.1.

2 v.

BSI

M3v

3 Su

bcirc

uit

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Capacitance-Voltage Characteristics

Ca

pac

ita

nc

e [

fF]

Vgs [V]

-4 -2 0 2 4

2.0

1.8

1.2

0.8

0.4

Vgs [V]

Ca

pac

ita

nc

e [

fF]

Cgb

Cgg

Cgd

CgsVds=0V

Asymmetrical LDMOS Symmetrical HVMOS

Normal MOSFET

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AC Modeling: Cgg BSIM3+JFETS Subckt. HiSIM_HV

• Subcircuit: bad fitting quality, especially in accumulation.• HiSIM_HV: good fitting quality in all regions.

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Self-Heating Effect for DC Analysis

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RC-Network:

Self-Heating Effect for AC Analysis

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Modeling Rdrift

HiSIM_HV 2.0.0 Series

MOSFET + Resistor

MOSFET Resistor

DPChannel

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Node potential Vddp is solved iteratively.

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Velocity saturation affects strongly on I-V characteristics.

2D-Device Simulation

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VDDPI d

dp

I-V Characteristics of Resistor

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W0

Wjunc

Wdep

xov

Lover

Djunc

xdep

xjunc

ddpddp driftov

VI W nx q

Ldrift

0 00

junc

- + over

ov

W WW A W W

D Lx dep junc

2 20 juncW L Dover

xjuncxdep

Djunc

A

: junction depth: current exude coefficient into depletion regionVddp

ddpI

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Modeling Current-Flow in Overlap Region

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I d [m

A]

Vds [V]

xov improvements

Vgs= 3~9V, 15V, 30V

Vgs [V]

2D-Device Sim.

HiSIM_HV

I d [m

A]

Vds [V]

Vds = 0.5V, 2V, 5V, 10~30V

Vgs [V]

I d [m

A]

(Lch = 1mm , Lover = 1mm, Djunc = 2mm)

Verification of I-V Characteristics

Vds = 0.5V, 2V, 5V, 10~30V

Vgs= 3~9V, 15V, 30V

I d [m

A]

The xov model enables to fit I-V characteristics for wide range

of bias conditions.

27

Vds = 0.5V, 2V, 5V, 10~30V

Vgs= 3~9V, 15V, 30V

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Empirical Model vs. Physical Model: IdVg

Ids - Vgs

Gm vs. Vgs

HiSIM_HV 1.x.x Old Empirical HiSIM_HV 2.x.x New Physical

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Empirical Model vs. Physical Model: IdVd

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HiSIM_HV 1.x.x Old Empirical HiSIM_HV 2.x.x New Physical

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HiSIM_HV Release

Hiroshima University &

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The Extreme Case; 120V Transistors

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HV NMOS output and transfer characteristic of a typical wafer. W/L=40/0.5, VGS= 2.9, 4.8, 6.7, 8.6, 10.5, 12.4, 14.3, 16.2, 18.1, 20 V, VBS=0 V. &VBS= 0, -1, -2, -3, -4 V, VDS=0.1 V.+ = measured, full lines= BSIM3v3 model; dashed lines = HiSIM_HV 1.2.1

Hiroshima University &

HiSIM_HV 1.2.1 v. BSIM3 sub-circuit

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Isolated HVMOS: High-Side Switch Modeling

- HVMOS used on the low-side of a load:Source and Substrate hold at the same potential- HVMOS used on the high-side of a load:Both Source and Drain can be placed at high potential=> Ron is changing with Vsub-s

Vsub=0

Vsub=-120V

Transfer Characteristics

Vd=0.1V, Vs=Vb=0

HiSIM_HV 1.2.1: Vsub modulates the effective depth of the drift region: Rdrift(Vsub,s)

Hiroshima University &

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HiSIM_HVThe following effects are also included:• Depletion effect of the gate polycrystalline

silicon (poly-Si).• Quantum mechanical• CLM• Narrow channel• STI• Leakage currents

(gate, substrate and gate-induced drain leakage (GIDL) currents).

• Source/bulk and drain/bulk diode models.• Noise models (1/f, thermal noise, induced

gate noise).• Non-quasi static (NQS) model.

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Complete Surface potential-based:HiSIM_HV solves the Poisson equation along the MOSFETchannel iteratively, including the resistance effect in the drift region.

high flexibility20 model flagsscales with the gate width,

the gate length, the number of gate fingers and the drift region length.

In addition, HiSIM_HV is capable of modeling symmetric and asymmetric HV devices.

Hiroshima University &

© 2011 austriamicrosystems

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Summary

Decision for HV Model depends very much on the applicationSub-circuit approach is very flexible and usable for switching

applications and for analog applications using large transistors sizes.

HiSIM_HV 1.1.2 and 1.2.1 shows high accuracy for all benchmarks.Detailed know how in parameter extraction needed Extensive measurements necessary.

HiSIM_HV 2.x First Version New physical drift region model is under evaluation and shows excellent benchmark results.

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© 2011 austriamicrosystems

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