I. Hng dn s dng phn mm ISE 12.4 vit code VHDL v m phng bng ISIM v MODELSIM tch hp trong ISE12.4. 1.M phngVHDL s dng ISIM tch hp trong ISE12.4. bt u chng trnh ta khi ng ISE t destop hoc t START nh sau:

hoc click double vo shortcut trn mn hnh:

Sau khi khi ng ISE ta c giao din nh sau:

Ta bt u qu trnh to project VHDL v m phng trn ISIM tch hp trong ISE theo cc bc sau: Chn Newproject:

c hnh sau:

Phn son code VHDL y Cha cc file

trong project

iu khin kim tra, dch, np chng trnh hay m phng,

Cc bo co khi thao tc hin th ti y

Bin dch, kim tra code VHDL v thao tc khc hoc m phng

Ta chn ni lu tr project m thc hin vo no sau ny d kim tra ri chn OK:

Chn tn file VHDL mc name ri chn Next:

Ta c hnh sau:

y ta chn dng FPGA tng ng, ngn ng l VHDL v nu m phng bng ISIM th ta chn mc Simulator l Isim, nu m phng bng Modelsim th ta chn Modelsim ri chn Next ta c:

Chn Finish ta c hnh tng ng nh sau:

Tip theo ta to 1 file new sorce nh sau son code VHDL:

c hnh sau:

Ta chn VHDL modul v t tn cho file VHDL cn son tho nh hnh sau ri nhn Next:

Tip theo ta chn cc chn vo, ra v s bit ca mi ng d liu vo ra tng ng nh sau ri nhn Next:

Ta c hnh sau, chn Finish.Ch ta t tn cc ng d liu vo ra khng c trng vi cc t kho ca VHDL, trong trng hp ny ta chn li u ra l outp:

Ta s c hnh sau:

Gi ta tin hnh son tho code VHDL sau vo vng son tho code VHDL: ---------------------------------------------------------------------------------- -- Company: HVKT Quan Su -- Engineer: kqha1025@gmail.com -- -- Create Date: 14:07:40 03/28/2011 -- Design Name: -- Module Name: chiatan - Behavioral

-- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity chiatan is generic(n : integer := 6); Port ( inp : in STD_LOGIC; outp : out STD_LOGIC); end chiatan; architecture Behavioral of chiatan is signal dem : integer ; begin ------------------------------------------- process(inp) variable dem1 : integer range 0 to n; begin if (inp'event and inp = '1') then dem1 := dem1 +1; end if; if(dem1 =n) then dem1 := 0; end if; dem

begin if(dem < 3) then outp

Tip theo ta tin hnh m phng trn ISIM: Ta chn Simulation v chn nh hnh sau:

Click double vo Simulate Behavioral Model hoc chn chut phi nh hnh sau:

Khng li

V ta c kt qu hnh m phng vi giao din ISIM nh sau:

Nu ta cn kim tra tn hiu no th ta s add tn hiu sang vng hin th dng sng kim tra hoc khng cn th ta c th xo i nh sau: Hnh sau th hin s add thm outp kim tra.

Th vin s dng trong file VHDL

Cc tn hiu vo ra v cc bin s dng trong project

Khu vc th hin cc tn hiu dng sng kho st

Cc thng bo khi thao tc ISIM hoc ta thc hin lnh trc tip iu khin ISIM ti y.

Tip theo ta khi to gi tr ban u cho tn hiu u vo, y l inp l dng clk nn ta chn nh hnh sau:

Ta c:

Ta in cc gi tr khi to nh hnh sau ri chn OK:

Tip theo ta chnh li thi gian kho st v tin hnh nhn phm ta

c kt qu( s dng cc phm ny tin quan st kt qu)

Chn xem ta c kt qu nh sau:

Phng to xem kt qu ta c hnh sau:

T gin dng sng trn cho ta thy kt qu hon ton chnh xc. Nh vy l ta tin hnh son tho code VHDL v m phng bng ISIM tch hp trn ISE xong. Trn y l nhng phn c bn nht, m rng thm th cc bn c thm help ca phn mm hoc tm c trn mng Internet. Chc cc bn thnh cng. Phn tip theo ti s hng dn cc bn m phng trn ModelSim tch hp trn ISE. 2.M phngVHDL s dng ModelSim tch hp trong ISE12.4.

Cc bc to project mi nh phn 1 ch khc l khi ta chn phn mm m phng lc ny l Modelsim tch hp trong ISE khi gi. Ch l ta phi ci

phn mm ModelSim tng ng trn my ca cc bn. y ti ci bn ModelSim 6.5 SE nn ta chn mc chn phn mm m phng khc phn 1 nh hnh sau:

V lm cc bc tng t nh phn 1, n bc chun b m phng ta chn phn mm l ModelSIM nh hnh sau:

Tip theo ta phi chn mc cha phn mm ModelSim m ta ci trong my ModelSim6.5 theo cc hnh sau:

mc Model Tech Simulator ta chn ng dn n file Modelsim.exe nh hnh sau, sau chn OK:

Tip theo ta chn thi gian hn ch cho kho st nh sau:

Sau chn OK. Tip theo ta chn m phng trn Modelsim nh hnh sau:

Ta c giao din trn ModelSim nh sau: Cc bn chn No

Ta thc hin ci t thi gian cho tn hiu inp nh sau:

Chn OK. Tip theo ta chn phm RUN kim tra kt qu dng sng nh sau: Hoc cc bn c th g trc tip lnh Run 2000ns trong ca s lnh pha di cng.

T kt qu hnh trn hon ton chnh xc vi chng trnh. Vy l ti hng dn xong cch son code trn ISE v m phng trn ModelSim. Cc bn tm hiu thm trong Help bit thm cc tnh nng khc. II. Hng dn son tho code VHDL trn phn mm Notepad++ v m phng trn ModelSim. 1.Son tho code VHDL trn phn mm Notepad++. Khi ng phn mm Notepad++ bng cch click p chut vo Shortcut trn destop hoc t thanh Start nh sau:

Ta c giao din ca Notepad++ nh sau:

Cc bn s tin hnh lu tn file VHDL cn thc hin di dng file .vhd ri sau tin hnh son code VHDL, y ti thc hin v d chia tn nh sau: Chn save as

Sau chn tn file.vhd v save type l all type

Ta c hnh sau:

T file ny ta tin hnh son code y nh sau: ---------------------------------------------------------------------------------- -- Company: HVKT Quan Su -- Engineer: kqha1025@gmail.com -- -- Create Date: 14:07:40 03/28/2011 -- Design Name: -- Module Name: chiatan - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all; entity chiatan is generic(n : integer := 6); Port ( inp : in STD_LOGIC; outp : out STD_LOGIC); end chiatan; architecture Behavioral of chiatan is signal dem : integer ; begin ------------------------------------------- process(inp) variable dem1 : integer range 0 to n; begin if (inp'event and inp = '1') then dem1 := dem1 +1; end if; if(dem1 =n) then dem1 := 0; end if; dem

Ri ta chn save file, sau ta bt u m phng bng phn mm ModelSim. 2.M phng file VHDL son tho trn Notepad++ bng phn mm Modelsim. Khi to ModelSim t thanh Start hoc t Shortcut trn destop nh sau:

Ta c giao din chng trnh nh sau:

T y ta tin hnh cc bc nh sau:

G lnh vlib work:

G lnh vcom chiatan.vhd nh sau:

G lnh vsim chiatan nh sau:

Tip theo ta add cc tn hiu sang vng test dng sng kim tra nh sau:

Tip theo ta chn quy lut clk cho tn hiu inp nh sau:

Ri chn OK.

Nhn phm m phng v ta c kt qu nh sau:

T kt qu ta thy hon ton chnh xc nh cc trng hp trc. Cc bn c th tm hiu thm t Help ca phn mm.