Rev. 1.00 1 November 19, 2019 Rev. 1.00 PB November 19, 2019

HT82V82Image/Neural-network Processor

Features• Dual-core symmetric high-performance video DSP,

each core contains ♦ up to 250MHz ♦ 5-stage pipeline ♦ Dynamic branch prediction ♦ I/D Caches, 2-way set-associative, 32KB each ♦ IEEE 754 Compliant single-precision Floating-

-Point Unit – FPU ♦ Nested interrupt controller with programmable

priority levels ♦ 16/32-bit instruction set ♦ SIMD instruction set ♦ General DSP instructions ♦ Rich featured video instruction set

• L1/L2 Memory Architecture ♦ 32KB L1 Program Cache, each core ♦ 16KB L1 Program RAM, each core ♦ 32KB L1 Data Cache, each core ♦ 32KB L1 Data RAM, each core ♦ 256KB L2 United Mapped RAM

• External Memory Interface ♦ 16/32-bit DDR2/3 memory interface ♦ NOR Flash memory interface

• Embedded Hardware Engine to accelerate video processing

• Enhanced Direct Memory Access – EDMA• Sensor Input interface

♦ Support two 8~20MHz 3~6ch CIS line sensor modules

♦ Supports two CMOS area sensor modules• Output interface

♦ Serial interface: High speed 4-wire SPI up to 40MHz.

♦ Parallel interface: TFT LCD display• Supports peripheral interfaces like I2C, SPI, UART,

SPI, Timer and 16-ch 10-bit ADC• Supports External Parallel Interfaces – EPI • SDIO interface

♦ Supports two different data bus modes: 1-bit (default) and 4-bit

♦ Supports two different speed modes: Normal speed (default) and High speed

♦ SD clock frequency of up to (fHCLK/2)MHz ♦ SPI mode and MMC stream mode not supported

• Robust security boot mechanism• Embedded LVR and POR circuits• 256-pin TFBGA package

Applications• Double-sided currency detector scanner• License Plate Recognition System• Automatic Optical Inspection System

General DescriptionThe HT82V82 is a fully integrated device for CIS and CMOS image processing and deep learning applications. It features a state-of-the-art dual-core floating-point DSP core, powerful Hardware Engine including Video processor and NPU (Neural Processing Unit) to accelerate image processing and AI computing, programmable timing generator and video processing modules for high-speed double-sided scanning for currency detection and face recognition applications.

The dual-core DSP processors offer performance up to 250MHz, each compl ian t wi th IEEE 754 single-precision floating-point operations and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The hardware engine provides hardware implementation of signal and image processing algorithms like Rotation, Decimation, JPEG Encoder, Image Histogram, CNN, Integral Image, etc. to offload the dual-core DSP’s loading and accelerate video processing.

The Sensor Interface provides an interface for image capture from CMOS or CIS sensors. The HT82V82 can be connected to a CMOS sensor directly through the sensor Interface. In conjunction with an Analog Front End (AFE) IC such as the HT82V48, it can also be connected to a CIS sensor, utilising the embedded Timing Generator.

The device also includes rich peripherals for UART, SPI, I2C, 16-ch ADC, SDIO, EPI (external parallel interface) to enable simplified interfacing to existing control systems. A high speed synchronous memory interface is provided for the popular DDR2/DDR3 memory.

By providing a robust security boot mechanism, the HT82V82 provides users with protected proprietary intellectual property measures and prevents external entities from modifying the user-developed program code.

HT82V82 is the best choice for next-generation applications that require image processing and deep learning in one integrated package. These applications span a wide array of video markets, like high-speed double-sided Currency Recognition, License Plate Recognition, Automatic Optical Inspection and Facial Recognition.

Rev. 1.00 2 November 19, 2019

HT82V82

Device Information

Peripherals CIS Line Sensor

CMOSArea Sensor

L1 Cache RAM 32KB×2L1 Program RAM 16KB×2L1 Data RAM 32KB×2L2 RAM 256KBeFuse 128 bits

Sensor InCIS 2 —CMOS — 2

Video OutSPI 1 —LCD Display — 1

CommunicationUART 4SPI 2I2C 2

TimerTimer/PWM (GPTM) 4Internal Timer (BFTM) 2WDT 1

PDMA 8 channelsAES 1SHA 1SDIO 1EPI 1GPIO Up to 40EXTI 8

10-bit ADCNumber of channels

1Max. 16 Channels

Comparator 1DSP frequency Up to 250MHzDDR frequency Up to 400MHzOperating voltage 2.0V ~ 3.6VOperating temperature -40°C ~ +85°CPackage 256-pin TFBGA

Rev. 1.00 3 November 19, 2019

HT82V82

Block Diagram

DSP

DSP

DSP

DDR3Ctrl

DSP

AFECISsensor

Multi-layer AHB

EDMA HWEngine

PDMA AHB2APBbridge

APB

SPI EPI

req

VIU_req

PHY

I2C/UART

16-ch ADC EXTI Timer/

PWM

DSP

DDR3memory

DSP

Nor_Flash

SF_Ctrl

CPU_req

Decrypt

L2 SRAM256K

BootROM

int1

int2

ILM ILM

Data InstructionData Instruction

DSP1

Icache Dcache

M2 M3DLM DLM

VIU

FPU

DSP0

Icache Dcache

M0 M1

FPU

DSP

DSP DSP

PLL

LVR DLL

DSPPOR

32K 32K 32K 32K 16K

32K

16K

32K

ckcu/rstcu

M8M9M4/5

SPI

GPIO

CSICMOSsensor

ARMVOU SPI

JTAG ICE

VOU_INTM11

SDIO DSP

SDIOCard

I80/VGA LCDDisplay

Pin Assignment1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A SF_MDO

ICE_TDI

PB0_ADC0

PB6_ADC6

PB11_ADC11

PB14_ADC14

CIS2_UVLED

CIS2_MODE AFE2_DIN5 AFE2_DIN4 AFE2_

DIN6 CIS_CLK CIS_SP CIS1_MODE FSOURCE AFE1_

DIN14

B ICE_TCK

ICE_TRST

PB1_ADC1

PB4_ADC4

PB10_ADC10

PB13_ADC13

CIS2_IR2LED

AFE2_DIN10 AFE2_DIN9 AFE2_DIN7 AFE2_

DIN3AFE_MDAT

CIS1_GLED

CIS1_RLED

AFE1_DIN15

CMP_IN

C SF_MDI

ICE_TDO

PB2_ADC2

PB3_ADC3

PB8_ADC8

PB12_ADC12

CIS2_IRLED

AFE2_DIN11 AFE2_DIN8 AFE2_SHD AFE2_

MCSNCIS1_UVLED

CIS1_BLED

AFE1_DIN13

AFE1_DIN11

AFE1_DIN6

D ICE_TMS PC3 PC2 PB5_

ADC5PB9_ADC9 SF_MCSN CIS2_

BLEDAFE2_DIN13

AFE2_DIN12

AFE2_ADCK

AFE1_MCSN

CIS1_IR2LED

CIS1_IRLED

AFE1_DIN12 AFE1_DIN5 AFE1_

DIN2

E PC1 PC0 PA13 PB7_ADC7

VCC3A_ADC

VCC3IO_ADC

CIS2_RLED

AFE2_DIN15

AFE2_DIN14 AFE2_DIN1 AFE_MCK VCC10A_

DLLVCC3A_

CMPAFE1_DIN7 AFE1_DIN1 AFE1_

DIN0

F PA15 PA14 PA12 PA11 PB15_ADC15 SF_MCK CIS2_

GLED VCC3IO_3 VCC3IO_3 AFE2_DIN2 AFE2_DIN0

AFE1_DIN9

AFE1_ADCK

AFE1_SHD

FRM_START

UR0_TX

G PA9 PA8 PA7 PA10 PA6 VCC3IO_1 VCCK VCCK VCCK VCC3IO_2 AFE1_DIN10

AFE1_DIN8

AFE1_DIN4

AFE1_DIN3 FRM_EN UR0_

RX

H DR_DQ13

DR_DQ12 PA1 PA0 PA5 VCC3IO_1 VCCK GND GND VCC3IO_2 RSTN BOOT_EN VO_SDO VO_

SDI VO_CSN VO_SCK

J DR_DQ8

DR_VREF1

DR_DQ9 PA2 PA4 VCC15O_

DDR2 VCCK GND GND VCC15O_DDR4 VO_INT TEST ROLLER_

OUT PC4 GND3IO_OSC XOUT

K DR_DQSB1 GND DR_

DQ15 DR_DM1 PA3 VCC15O_DDR2 VCCK VCCK VCCK VCC15O_

DDR4 PC5 VCC10A_PLL

DR_RDRVDN

DR_VREF3

VCC3IO_OSC XIN

L DR_DQS1 GND DR_

DQ10DR_DQ11

VCC15O_DDRCK2

VCC15O_DDR1

VCC15O_DDR1

VCC15O_DDR0

VCC15O_DDR0

VCC15O_DDR3

VCC15O_DDR3

VCC15O_DDRCK4

DR_RDRVUP

DR_DQ28 GND DR_

DQSB3

M DR_DQ14 GND DR_

DQ6 DR_DQ0 VCC15O_DDRCK1 DR_A14 DR_A8 VCC15O_

DDRCK0 DR_DQ19 DR_DQ18 VCC15O_DDRCK3 PC6 PC7 DR_

DQ31 GND DR_DQS3

N DR_DQ5

DR_VREF0

DR_DQ4 DR_BA2 DR_A12 DR_A5 DR_A3 DR_BA1 DR_CSN DR_WEN DR_DQ23 DR_DM3 DR_DQ30 DR_

DQ16 DR_DQ25 DR_DQ29

P DR_DQSB0

DR_DQ1

DR_DQ3 DR_CKE DR_A6 DR_A4 DR_A0 DR_A10 DR_BA0 DR_RASN DR_A13 DR_ODT1 DR_DQ21 DR_

DQ20 DR_DQ27 DR_DQ24

R DR_DQS0 GND DR_

DQ2DR_

RESETN DR_A7 DR_A1 GND GND GND GND DR_ODT0 VCC10A_DDR0 GND GND DR_VREF2 DR_

DQ26

T DR_DM0 GND DR_

DQ7 DR_A9 DR_A11 DR_A2 DR_CK1 DR_CKB1 DR_CK0 DR_CKB0 DR_CASN DR_DQ22 DR_DQS2 DR_DQSB2 DR_DM2 DR_

DQ17

Rev. 1.00 4 November 19, 2019

HT82V82

Pin DescriptionPin Ball

Assignment DescriptionName DIR TYP PUL mA

SF_MDO O — — 4 A1 Serial Nor-Flash Data OutputICE_TCK I — U — B1 DSP ICE ClockICE_TMS I — U — D1 DSP ICE Mode SelectionSF_MDI I — U — C1 Serial Nor-Flash Data InputICE_TRST I — D — B2 DSP ICE ResetICE_TDI I — U — A2 DSP ICE Data InputPC2 B — U 4 D3 General Purpose Port C 2ICE_TDO O — — 8 C2 DSP ICE Data OutputPC3 B — U 4 D2 General Purpose Port C 3PC0 B — U 4 E2 General Purpose Port C 0PC1 B — U 4 E1 General Purpose Port C 1PA15 B — U 4 F1 General Purpose Port A 15PA14 B — U 4 F2 General Purpose Port A 14PA13 B — U 4 E3 General Purpose Port A 13 PA12 B — U 4 F3 General Purpose Port A 12PA11 B — U 4 F4 General Purpose Port A 11PA10 B — U 4 G4 General Purpose Port A 10PA9 B — U 4 G1 General Purpose Port A 9PA8 B — U 4 G2 General Purpose Port A 8PA7 B — U 4 G3 General Purpose Port A 7PA6 B — U 4 G5 General Purpose Port A 6PA5 B — U 4 H5 General Purpose Port A 5PA4 B — U 4 J5 General Purpose Port A 4PA3 B — U 4 K5 General Purpose Port A 3PA2 B — U 4 J4 General Purpose Port A 2PA1 B — U 4 H3 General Purpose Port A 1PA0 B — U 4 H4 General Purpose Port A 0DR_VREF1 AI — — — J2 Reference voltage for data bus bit 8~15 receiversDR_DQ12 B — — — H2 DDR-RAM data bus bit 12DR_DQ13 B — — — H1 DDR-RAM data bus bit 13DR_DQ8 B — — — J1 DDR-RAM data bus bit 8DR_DQ9 B — — — J3 DDR-RAM data bus bit 9DR_DM1 O — — — K4 DDR-RAM Data bit 8~15 maskDR_DQSB1 B — — — K1 DDR-RAM data strobe complement bit 8~15DR_DQS1 B — — — L1 DDR-RAM data strobe bit 8~15VCC15O_DDRCK0 P — — — M8 1.5V digital power supply for CK/CKBDR_DQ14 B — — — M1 DDR-RAM data bus bit 14DR_DQ15 B — — — K3 DDR-RAM data bus bit 15DR_DQ10 B — — — L3 DDR-RAM data bus bit 10DR_DQ11 B — — — L4 DDR-RAM data bus bit 11DR_VREF0 AI — — — N2 Reference voltage for data bus bit 0~7 receiversDR_DQ4 B — — — N3 DDR-RAM data bus bit 4DR_DQ5 B — — — N1 DDR-RAM data bus bit 5DR_DQ0 B — — — M4 DDR-RAM data bus bit 0DR_DQ1 B — — — P2 DDR-RAM data bus bit 1DR_DM0 O — — — T1 DDR-RAM Data bit 0~7 mask

Rev. 1.00 5 November 19, 2019

HT82V82

Pin Ball Assignment Description

Name DIR TYP PUL mADR_DQSB0 B — — — P1 DDR-RAM data strobe complement bit 0~7DR_DQS0 B — — — R1 DDR-RAM data strobe bit 0~7VCC15O_DDRCK1 P — — — M5 1.5V digital power supply for CK/CKBDR_DQ6 B — — — M3 DDR-RAM data bus bit 6DR_DQ7 B — — — T3 DDR-RAM data bus bit 7DR_DQ2 B — — — R3 DDR-RAM data bus bit 2DR_DQ3 B — — — P3 DDR-RAM data bus bit 3DR_RESETN O — — — R4 DDR-RAM reset, low activeDR_CKE O — — — P4 DDR-RAM clock enableDR_BA2 O — — — N4 DDR-RAM bank address bit 2DR_A14 O — — — M6 DDR-RAM address bus bit 14DR_A9 O — — — T4 DDR-RAM address bus bit 9DR_A12 O — — — N5 DDR-RAM address bus bit 12DR_A11 O — — — T5 DDR-RAM address bus bit 11DR_A7 O — — — R5 DDR-RAM address bus bit 7DR_A8 O — — — M7 DDR-RAM address bus bit 8DR_A6 O — — — P5 DDR-RAM address bus bit 6DR_A5 O — — — N6 DDR-RAM address bus bit 5DR_A4 O — — — P6 DDR-RAM address bus bit 4DR_A3 O — — — N7 DDR-RAM address bus bit 3DR_A1 O — — — R6 DDR-RAM address bus bit 1DR_A2 O — — — T6 DDR-RAM address bus bit 2DR_CK1 O — — — T7 DDR-RAM 2nd chip clockDR_CKB1 O — — — T8 DDR-RAM 2nd chip clock complementVCC15O_DDRCK2 P — — — L5 1.5V digital power supply for CK/CKBDR_CK0 O — — — T9 DDR-RAM 1st chip clock DR_CKB0 O — — — T10 DDR-RAM 1st chip clock complementDR_A0 O — — — P7 DDR-RAM address bus bit 0DR_A10 O — — — P8 DDR-RAM address bus bit 10DR_BA1 O — — — N8 DDR-RAM bank address bit 1DR_BA0 O — — — P9 DDR-RAM bank address bit 0DR_RASN O — — — P10 DDR-RAM Row Address Strobe, Active LowDR_CSN O — — — N9 DDR-RAM Chip Select, Active LowDR_WEN O — — — N10 DDR-RAM Write Enable, Active LowDR_ODT0 O — — — R11 DDR-RAM 1st Chip on-die terminationDR_CASN O — — — T11 DDR-RAM Column Address Strobe, Active LowDR_A13 O — — — P11 DDR-RAM address bus bit 13DR_ODT1 O — — — P12 DDR-RAM 2nd Chip on-die terminationVCC10A_DDR0 P — — — R12 1.0V analog power supply for DDR PLLDR_DQ19 B — — — M9 DDR-RAM data bus bit 19DR_DQ18 B — — — M10 DDR-RAM data bus bit 18DR_DQ23 B — — — N11 DDR-RAM data bus bit 23DR_DQ22 B — — — T12 DDR-RAM data bus bit 22DR_DQS2 B — — — T13 DDR-RAM data strobe bit 16~23DR_DQSB2 B — — — T14 DDR-RAM data strobe complement bit 16~23VCC15O_DDRCK3 P — — — M11 1.5V digital power supply for CK/CKBDR_DM2 O — — — T15 DDR-RAM data bit 16~23 mask

Rev. 1.00 6 November 19, 2019

HT82V82

Pin Ball Assignment Description

Name DIR TYP PUL mADR_DQ17 B — — — T16 DDR-RAM data bus bit 17DR_DQ16 B — — — N14 DDR-RAM data bus bit 16DR_DQ21 B — — — P13 DDR-RAM data bus bit 21DR_DQ20 B — — — P14 DDR-RAM data bus bit 20DR_VREF2 AI — — — R15 Reference voltage for data bus bit 16~23 receiversDR_DQ27 B — — — P15 DDR-RAM data bus bit 27DR_DQ26 B — — — R16 DDR-RAM data bus bit 26DR_DQ31 B — — — M14 DDR-RAM data bus bit 31DR_DQ30 B — — — N13 DDR-RAM data bus bit 30VCC15O_DDRCK4 P — — — L12 1.5V digital power supply for CK/CKBDR_DQS3 B — — — M16 DDR-RAM data strobe bit 24~31DR_DQSB3 B — — — L16 DDR-RAM data strobe complement bit 24~31DR_DM3 O — — — N12 DDR-RAM data bit 24~31 maskDR_DQ25 B — — — N15 DDR-RAM data bus bit 25DR_DQ24 B — — — P16 DDR-RAM data bus bit 24DR_DQ29 B — — — N16 DDR-RAM data bus bit 29DR_DQ28 B — — — L14 DDR-RAM data bus bit 28DR_VREF3 AI — — — K14 Reference voltage for data bus bit 24~31 receiversDR_RDRVUP O — — — L13 Pad connected to ground through a 240Ω resistor

DR_RDRVDN O — — — K13 Pad connected to a 1.5V DDR3 power through a 240Ω resistor

VCC3IO_OSC P — — — K15 Oscillator 3.3V power supplyXIN I — — — K16 Oscillator InputXOUT O — — — J16 Oscillator OutputGND3IO_OSC P — — — J15 Oscillator groundVCC10A_PLL P — — — K12 1.0V power supply for Internal 2 PLLsPC7 B — U 4 M13 General Purpose Port C 7PC6 B — U 4 M12 General Purpose Port C 6PC5 B — U 4 K11 General Purpose Port C 5PC4 B — U 4 J14 General Purpose Port C 4ROLLER_OUT O — — 8 J13 Comparator Output for Roller Output, Square wave

VO_SDI B — U 4 H14 VOU Slave SPI Video Data Input or VOU Master SPI Video Data Output

VO_SDO B — U 4 H13 VOU Slave SPI Video Data Output or VOU Master SPI Video Data Input

VO_SCK B — U 4 H16 VOU Slave SPI Video Clock Input orVOU Master SPI Video Clock Output

VO_CSN B — U 4 H15 VOU Slave SPI Video Chip Select Input orVOU Master SPI Video Chip Select Output

VO_INT O — — 4 J11 Slave SPI Video Interrupt OutputTEST I — D — J12 Test Mode Input

BOOT_EN I — U — H12Boot Enable Input0: No Boot, ISP burning code to external NOR_Flash.1: Boot from external NOR_Flash

RSTN I S U — H11 System Reset, Active LowUR0_RX I — U — G16 UART0 RXUR0_TX O — — 8 F16 UART0 TXFRM_EN I — D — G15 Frame Enable InputFRM_START I — U — F15 Frame Start Input

Rev. 1.00 7 November 19, 2019

HT82V82

Pin Ball Assignment Description

Name DIR TYP PUL mAAFE1_DIN1 I — U — E15 AFE_DIN1 from external 1st AFEAFE1_DIN0 I — U — E16 AFE_DIN0 from external 1st AFEAFE1_DIN3 I — U — G14 AFE_DIN3 from external 1st AFEAFE1_DIN2 I — U — D16 AFE_DIN2 from external 1st AFEAFE1_DIN5 I — U — D15 AFE_DIN5 from external 1st AFEAFE1_DIN4 I — U — G13 AFE_DIN4 from external 1st AFEAFE1_DIN7 I — U — E14 AFE_DIN7 from external 1st AFEAFE1_DIN6 I — U — C16 AFE_DIN6 from external 1st AFEAFE1_SHD B — D 8 F14 AFE SHD Output to 1st AFEAFE1_ADCK B — D 8 F13 AFE ADCK Output to 1st AFEAFE1_DIN8 I — U — G12 AFE_DIN8 from external 1st AFEAFE1_DIN10 I — U — G11 AFE_DIN10 from external 1st AFEAFE1_DIN9 I — U — F12 AFE_DIN9 from external 1st AFEAFE1_DIN12 I — U — D14 AFE_DIN12 from external 1st AFEAFE1_DIN11 I — U — C15 AFE_DIN11 from external 1st AFEAFE1_DIN13 I — U — C14 AFE_DIN13 from external 1st AFECMP_IN AI — — — B16 Comparator Input for Roller Input, Sine waveVCC3A_CMP P — — — E13 3.3V analog comparator power supplyVCC10A_DLL P — — — E12 1.0V power supply for internal DLLAFE1_DIN14 I — U — A16 AFE_DIN14 from external 1st AFEFSOURCE P — — — A15 E-fuse 3.3V programming powerCIS1_MODE O — — 4 A14 1st CIS Mode SelectAFE1_DIN15 I — U — B15 AFE_DIN15 from external 1st AFECIS1_RLED B — D 8 B14 1st CIS Module Red LED Active Slot ControlCIS1_GLED B — D 8 B13 1st CIS Module Green LED Active Slot ControlCIS1_IRLED B — D 8 D13 1st CIS Module IR LED Active Slot ControlCIS1_BLED B — D 8 C13 1st CIS Module Blue LED Active Slot ControlCIS1_IR2LED B — D 8 D12 1st CIS Module IR2 LED Active Slot ControlCIS1_UVLED B — D 8 C12 1st CIS Module UV LED Active Slot ControlCIS_CLK O — — 8 A12 CIS Module Pixel ClockCIS_SP O — — 8 A13 CIS Module Start PulseAFE_MDAT B — U 8 B12 AFE Master SPI Serial Data I/OAFE1_MCSN O — — 4 D11 AFE SPI Chip Select Output to 1st AFEAFE_MCK O — — 8 E11 AFE Master SPI Serial ClockAFE2_MCSN O — — 4 C11 AFE SPI Chip Select Output to 2nd AFEAFE2_DIN0 B — U 4 F11 AFE_DIN0 from external 2nd AFEAFE2_DIN1 B — U 4 E10 AFE_DIN1 from external 2nd AFEAFE2_DIN2 B — U 4 F10 AFE_DIN2 from external 2nd AFEAFE2_DIN3 B — U 4 B11 AFE_DIN3 from external 2nd AFEAFE2_DIN4 B — U 4 A10 AFE_DIN4 from external 2nd AFEAFE2_DIN5 B — U 4 A9 AFE_DIN5 from external 2nd AFEAFE2_DIN6 B — U 4 A11 AFE_DIN6 from external 2nd AFEAFE2_DIN7 B — U 4 B10 AFE_DIN7 from external 2nd AFEAFE2_ADCK B — D 8 D10 AFE ADCK Output to 2nd AFEAFE2_SHD B — D 8 C10 AFE SHD Output to 2nd AFEAFE2_DIN8 B — U 4 C9 AFE_DIN8 from external 2nd AFEAFE2_DIN9 B — U 4 B9 AFE_DIN9 from external 2nd AFE

Rev. 1.00 8 November 19, 2019

HT82V82

Pin Ball Assignment Description

Name DIR TYP PUL mAAFE2_DIN10 B — U 4 B8 AFE_DIN10 from external 2nd AFEAFE2_DIN11 B — U 4 C8 AFE_DIN11 from external 2nd AFEAFE2_DIN12 B — U 4 D9 AFE_DIN12 from external 2nd AFEAFE2_DIN13 B — U 4 D8 AFE_DIN13 from external 2nd AFEAFE2_DIN14 B — U 4 E9 AFE_DIN14 from external 2nd AFEAFE2_DIN15 B — U 4 E8 AFE_DIN15 from external 2nd AFECIS2_MODE O — — 4 A8 2nd CIS Mode SelectCIS2_RLED B — D 8 E7 2nd CIS Module Red LED Active Slot ControlCIS2_GLED B — D 8 F7 2nd CIS Module Green LED Active Slot ControlCIS2_BLED B — D 8 D7 2nd CIS Module Blue LED Active Slot ControlCIS2_IRLED B — D 8 C7 2nd CIS Module IR LED Active Slot ControlCIS2_UVLED B — D 8 A7 2nd CIS Module UV LED Active Slot ControlCIS2_IR2LED B — D 8 B7 2nd CIS Module IR2 LED Active Slot ControlSF_MCSN O — — 4 D6 Serial Nor-Flash Chip Selection, active lowSF_MCK O — — 4 F6 Serial Nor-Flash clockPB15_ADC15 B — U 4 F5 General Purpose Port B 15 or ADC CH 15 InputPB14_ADC14 B — U 4 A6 General Purpose Port B 14 or ADC CH 14 InputPB13_ADC13 B — U 4 B6 General Purpose Port B 13 or ADC CH 13 InputPB12_ADC12 B — U 4 C6 General Purpose Port B 12 or ADC CH 12 InputPB11_ADC11 B — U 4 A5 General Purpose Port B 11 or ADC CH 11 InputPB10_ADC10 B — U 4 B5 General Purpose Port B 10 or ADC CH 10 InputPB9_ADC9 B — U 4 D5 General Purpose Port B 9 or ADC CH 9 InputPB8_ADC8 B — U 4 C5 General Purpose Port B 8 or ADC CH 8 InputVCC3IO_ADC P — — — E6 3.3V ADC power supply for IOVCC3A_ADC P — — — E5 3.3V ADC power supply for analogPB7_ADC7 B — U 4 E4 General Purpose Port B 7 or ADC CH 7 InputPB5_ADC5 B — U 4 D4 General Purpose Port B 5 or ADC CH 5 InputPB6_ADC6 B — U 4 A4 General Purpose Port B 6 or ADC CH 6 InputPB3_ADC3 B — U 4 C4 General Purpose Port B 3 or ADC CH 3 InputPB4_ADC4 B — U 4 B4 General Purpose Port B 4 or ADC CH 4 InputPB1_ADC1 B — U 4 B3 General Purpose Port B 1 or ADC CH 1 InputPB2_ADC2 B — U 4 C3 General Purpose Port B 2 or ADC CH 2 InputPB0_ADC0 B — U 4 A3 General Purpose Port B 0 or ADC CH 0 InputVCC3IO_1 P — — — G6, H6 Pad power 3.3V pinVCC3IO_2 P — — — G10, H10 Pad power 3.3V pinVCC3IO_3 P — — — F8, F9 Pad power 3.3V pinVCC15O_DDR0 P — — — L8, L9 1.5V digital power supplyVCC15O_DDR1 P — — — L6, L7 1.5V digital power supplyVCC15O_DDR2 P — — — J6, K6 1.5V digital power supplyVCC15O_DDR3 P — — — L10, L11 1.5V digital power supplyVCC15O_DDR4 P — — — J10, K10 1.5V digital power supply

VCCK P — — —G7, G8, G9, H7, J7, K7,

K8, K91.0V digital power supply

Rev. 1.00 9 November 19, 2019

HT82V82

Pin Ball Assignment Description

Name DIR TYP PUL mA

GND P — — —

K2, L2, M2, R2, T2, R7, H8, J8, R8, H9, J9, R9, R10, R13,

R14, L15, M15

Ground

Note: DIR: Pad direction; B: Bi-directional; O: Output; I: Input;P: Power; AI: Analog Input; TYP: Pad type; S: Schmitt trigger;PUL: Pad internal pull up/down 75kΩ resister; U: Pull-up; D: Pull-down;mA: Pad driving current capability.

Pin MUX Table for AFIO

AFIO[1:0]2’b00 (AF0) 2’b01 (AF1) 2’b10 (AF2) 2’b11 (AF3) Comment

DEB_EN=0 DEB_EN=1 EPI_EN=0 EPI_EN=1

PA0 GPIO0 Debug[0] SPI1_CSN UART1_TX I2C0_SCL I2C0_SCL —PA1 GPIO1 Debug[1] SPI1_SCK UART1_RX I2C0_SDA I2C0_SDA —PA2 GPIO2 Debug[2] SPI1_MOSI UART2_TX I2C1_SCL I2C1_SCL —PA3 GPIO3 Debug[3] SPI1_MISO UART2_RX I2C1_SDA I2C1_SDA —PA4 GPIO4 Debug[4] *Same *Same — EPI_WRN_o EPIPA5 GPIO5 Debug[5] *Same *Same — EPI_RDN_o EPIPA6 GPIO6 Debug[6] GT0_CH0 SD_WRPOT — — GPTM0; EPIPA7 GPIO7 Debug[7] GT0_CH1 SD_DETECT — — GPTM0; EPIPA8 GPIO8 Debug[8] GT0_CH2 SDDAT1 — — GPTM0; EPIPA9 GPIO9 Debug[9] GT0_CH3 SDDAT0 — — GPTM0; EPI

PA10 GPIO10 Debug[10] GT0_ETI SDCLK — — GPTM0; EPIPA11 GPIO11 Debug[11] *Same SDCMD — — GPIO_INT0; SDIOPA12 GPIO12 Debug[12] *Same SDDAT3 — — GPIO_INT1; SDIOPA13 GPIO13 Debug[13] *Same SDDAT2 — — GPIO_INT2; SDIOPA14 GPIO14 Debug[14] *Same *Same — EPI_D[0] GPIO_INT3; EPIPA15 GPIO15 Debug[15] *Same *Same — EPI_D[1] GPIO_INT4; EPIPB0 GPIO16 *Same ADC_CH0 *Same — — ADC_CH0PB1 GPIO17 *Same ADC_CH1 *Same — — ADC_CH1PB2 GPIO18 *Same ADC_CH2 *Same — EPI_D[2] ADC_CH2; EPIPB3 GPIO19 *Same ADC_CH3 *Same — EPI_D[3] ADC_CH3; EPIPB4 GPIO20 *Same ADC_CH4 *Same — EPI_D[4] ADC_CH4; EPIPB5 GPIO21 *Same ADC_CH5 *Same — EPI_D[5] ADC_CH5; EPIPB6 GPIO22 *Same ADC_CH6 *Same — EPI_D[6] ADC_CH6; EPI

PB7 GPIO23 *Same ADC_CH7 *Same — EPI_D[7] ADC_CH7; EPI

PB8 GPIO24 *Same ADC_CH8 CKOUT — EPI_D[8] ADC_CH8; EPIPB9 GPIO25 *Same ADC_CH9 GT3_ETI — EPI_D[9] ADC_CH9; EPI

PB10 GPIO26 *Same ADC_CH10 GT2_ETI — EPI_D[10] ADC_CH10; EPIPB11 GPIO27 *Same ADC_CH11 GT1_ETI — EPI_D[11] ADC_CH11, GPTM1; EPIPB12 GPIO28 *Same ADC_CH12 GT1_CH0 — EPI_D[12] ADC_CH12, GPTM1; EPIPB13 GPIO29 *Same ADC_CH13 GT1_CH1 — EPI_D[13] ADC_CH13, GPTM1; EPIPB14 GPIO30 *Same ADC_CH14 GT1_CH2 — EPI_D[14] ADC_CH14, GPTM1; EPIPB15 GPIO31 *Same ADC_CH15 GT1_CH3 — EPI_D[15] ADC_CH15, GPTM1; EPIPC0 GPIO32 Debug[16] UART2_TX GT2_CH0 SPI1_CSN EPI_DREQ_i UART2; GPTM2; SPI1; EPIPC1 GPIO33 Debug[17] UART2_RX GT2_CH1 SPI1_SCK EPI_DACK_o UART2; GPTM2; SPI1; EPIPC2 GPIO34 Debug[18] UART3_TX GT2_CH2 SPI1_MOSI EPI_CLK_i UART3; GPTM2; SPI1; EPIPC3 GPIO35 Debug[19] UART3_RX GT2_CH3 SPI1_MISO EPI_CLK1_i UART3; GPTM2; SPI1; EPI

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AFIO[1:0]2’b00 (AF0) 2’b01 (AF1) 2’b10 (AF2) 2’b11 (AF3) Comment

DEB_EN=0 DEB_EN=1 EPI_EN=0 EPI_EN=1

PC4 GPIO36 Debug[20] I2C0_SCL GT3_CH0 SPI2_CSN SPI2_CSN I2C0; GPTM3; SPI2PC5 GPIO37 Debug[21] I2C0_SDA GT3_CH1 SPI2_SCK SPI2_SCK I2C0; GPTM3; SPI2PC6 GPIO38 Debug[22] I2C1_SCL GT3_CH2 SPI2_MOSI SPI2_MOSI I2C1; GPTM3; SPI2PC7 GPIO39 Debug[23] I2C1_SDA GT3_CH3 SPI2_MISO SPI2_MISO I2C1; GPTM3; SPI2

UART0_TX — — — — — — UART0 for ISPUART0_RX — — — — — — UART0 for ISP

Note: “*Same” means same as AF0: GPIOn.

CIS and CMOS Pin MUX Table

PinCIS CMOS (*)

2 input & 1 output2 input 1 input & 1 outputAFE1_ADCK_b AFE_ADCK_o AFE_ADCK_o LCD_DO_b[17]AFE1_SHD_b AFE_SHD_o AFE_SHD_o LCD_DO_b[16]

AFE1_DIN_i[15:10] Same Same

CMOS2_PCLK_iCMOS2_VSYNC_iCMOS2_HSYNC_iCMOS_PCLK_iCMOS_VSYNC_iCMOS_HSYNC_i

AFE1_DIN_i[9:8] Same Same CMOS2_DIN_i[1:0]AFE1_DIN_i[7:0] Same Same CMOS_DIN_i[7:0]AFE_MCSN_o Same Same CMOS_PWDN_oAFE_MCK_o Same Same CMOS_SCL_oAFE_MDAT_b Same Same CMOS_SDA_bCIS_CLK_o Same Same NACIS_SP_o Same Same CMOS_MCLK_oCIS_MODE_o Same Same CMOS2_PWDN_oCIS1_GLED_b CIS_GLED_o CIS_GLED_o CMOS2_DIN_i[2]CIS1_RLED_b CIS_RLED_o CIS_RLED_o CMOS2_DIN_i[3]CIS1_BLED_b CIS_BLED_o CIS_BLED_o CMOS2_DIN_i[4]CIS1_IRLED_b CIS_IRLED_o CIS_IRLED_o CMOS2_DIN_i[5]CIS1_UVLED_b CIS_UVLED_o CIS_UVLED_o CMOS2_DIN_i[6]CIS1_IR2LED_b CIS_IR2LED_o CIS_IR2LED_o CMOS2_DIN_i[7]AFE2_MCSN_o Same LCD_CSN_o LCD_CSN_oAFE2_ADCK_b Same LCD_DCLK_o LCD_DCLK_oAFE2_SHD_b Same LCD_HSYNC_o LCD_HSYNC_oAFE2_DIN_b[15:0] AFE2_DIN_i[15:0] LCD_DO_b[15:0] LCD_DO_b[15:0]CIS2_MODE_o Same LCD_VSYNC_o LCD_VSYNC_oCIS2_GLED_b CIS2_GLED_o LCD_DE_o LCD_DE_oCIS2_RLED_b CIS2_RLED_o LCD_DCSEL_o LCD_DCSEL_oCIS2_BLED_b CIS2_BLED_o LCD_WRN_SCL_o LCD_WRN_SCL_oCIS2_IRLED_b CIS2_IRLED_o LCD_RDN_o LCD_RDN_oCIS2_UVLED_b CIS2_UVLED_o LCD_SDA_b LCD_SDA_bCIS2_IR2LED_b CIS2_IR2LED_o LCD_SDO_i LCD_SDO_iVO_INT_o Same Same SameVO_CSN_b Same Same SameVO_SCK_b Same Same SameVO_SDO_b Same Same Same

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PinCIS CMOS (*)

2 input & 1 output2 input 1 input & 1 outputVO_SDI_b Same Same Same

Note: * These three modes are selected by setting register 0x402D3044[1:0].“Same” means same as the original pin function listed in the Pin column.

Register MapStart Address End Address Peripheral Bus0x4000_0000 0x4000_0FFF UART0

APB0

0x4000_1000 0x4000_1FFF UART20x4000_2000 0x4000_3FFF Reserved0x4000_4000 0x4000_4FFF EPI0x4000_5000 0x4000_9FFF Reserved0x4001_0000 0x4001_0FFF ADC0x4001_1000 0x4002_1FFF Reserved0x4002_2000 0x4002_2FFF AFIO0x4002_3000 0x4002_3FFF Reserved0x4002_4000 0x4002_4FFF EXTI0x4002_5000 0x400F_FFFF Reserved0x4010_0000 0x4013_FFFF Reserved

APB1

0x4014_0000 0x4014_0FFF UART10x4014_1000 0x4014_1FFF UART30x4014_2000 0x4014_3FFF Reserved0x4014_4000 0x4014_4FFF SPI10x4014_5000 0x4014_5FFF SPI20x4014_6000 0x4014_7FFF Reserved0x4014_8000 0x4014_8FFF I2C00x4014_9000 0x4014_9FFF I2C10x4014_A000 0x4016_7FFF Reserved0x4016_8000 0x4016_8FFF WDT0x4016_9000 0x4016_DFFF Reserved0x4016_E000 0x4016_EFFF GPTM00x4016_F000 0x4016_FFFF GPTM10x4017_0000 0x4017_0FFF GPTM20x4017_1000 0x4017_1FFF GPTM30x4017_2000 0x4017_5FFF Reserved0x4017_6000 0x4017_6FFF BFTM00x4017_7000 0x4017_7FFF BFTM10x4017_8000 0x401F_FFFF Reserved

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Start Address End Address Peripheral Bus0x4020_0000 0x4028_7FFF Reserved

AHB

0x4028_8000 0x4028_9FFF CKCU/RSTCU0x4028_A000 0x4028_FFFF Reserved0x4029_0000 0x4029_1FFF PDMA 0x4029_2000 0x4029_3FFF EDMA0x4029_4000 0x4029_5FFF VIU0x4029_6000 0x4029_7FFF DDR0x4029_8000 0x4029_9FFF Reserved0x4029_A000 0x4029_BFFF VOU0x4029_C000 0x402A_FFFF Reserved0x402B_0000 0x402B_1FFF GPIOA0x402B_2000 0x402B_3FFF GPIOB0x402B_4000 0x402B_5FFF GPIOC0x402B_6000 0x402B_7FFF SDIO0x402B_8000 0x402B_FFFF Reserved0x402C_0000 0x402C_7FFF HWE0x402C_8000 0x402C_9FFF AES0x402C_A000 0x402C_BFFF SHA0x402C_C000 0x402C_CFFF CSIF00x402C_D000 0x402C_DFFF CSIF10x402C_E000 0x402C_FFFF SF_CTRL0x402D_0000 0x402D_2FFF Reserved0x402D_3000 0x402D_3FFF SYS_CTRL0x402D_4000 0x402F_FFFF Reserved

Absolute Maximum RatingsSupply Voltage .........................VSS-0.3V to VSS+4.3V

Input Voltage ...........................VSS-0.3V to VDD+0.3V

Output Voltage ........................VSS-0.3V to VDD+0.3V

Analog supply power ................................ 3.0V~3.6V

Storage Temperature .......................... -40°C to 150°C

Operating Temperature ........................ -25°C to 70°C

Digital supply power ................................. 3.0V~3.6V

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect de-vice reliability.

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Recommended Operating ConditionsTA=25 °C, unless otherwise specified

Symbol Parameter Test Conditions Min. Typ. Max. UnitVCC3IO Input / Output Operating Voltage — 3.0 3.3 3.6 VVCC3IO_ADC ADC Input / Output Operating Voltage — 3.0 3.3 3.6 VVCC3A_ADC ADC Operating Voltage — 3.0 3.3 3.6 VVCC3A_CMP Comparator Operating Voltage — 3.0 3.3 3.6 VVCC3IO_OSC Oscillator Operating Voltage — 3.0 3.3 3.6 VVCC10A_DLL DLL Operating Voltage — 0.9 1.0 1.1 VVCC10A_PLL PLL Operating Voltage — 0.9 1.0 1.1 VVCCK Core Operating Voltage — 0.9 1.0 1.1 VVCC15O_DDR DDR Input / Output Operating Voltage — 1.425 1.500 1.575 VVCC15O_DDRCK DDR Clock Operating Voltage — 1.425 1.500 1.575 V

D.C. CharacteristicsVCC3IO=3.3V, no load

Symbol Parameter Test Conditions Min. Typ. Max. UnitVIL Input Voltage Low — — — 0.8 VVIH Input Voltage High — 2 — — VVOL Output Voltage Low — — — 0.4 VVOH Output Voltage High — 2.4 — — VIWC Working Current — — 68.5 — mAVT- Input Schmitt trigger Low Voltage — 0.8 1.1 — VVT+ Input Schmitt trigger High Voltage — — 1.6 2.0 VRI Input Pull-up / Pull-down Resistance VIL=0 or VIH=VCC — 75 — kΩIVCC3IO IO Operating Current VCC3IO=3.3V, VIU ADCK @ 60MHz — 10.27 — mAIADC ADC Operating Current VCC3A_ADC=3.3V, VCC3IO_ADC=3.3V — 2.22 — mAICMP Comparator Operating Current VCC3A_CMP=3.3V — 0.07 — mAIVCCK Core Operating Current fSYS_CLK=240MHz, fAHB_CLK=120MHz — 400 — mAIVCC3IO_OSC Oscillator Operating Current Reference clock 32MHz — 2.1 — mAIVCC10A_PLL- PLL Operating Current fSYS_CLK=240MHz, fDDR_CLK=400MHz — 1.29 — mAIVCC10A_DLL- DLL Operating Current fCIS_CLK=20MHz — 3.59 — mAIVCC15O_DDR- DDR Operating Current fDDR_CLK=400MHz — 83.5 — mA

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Functional DescriptionThe main features of the HT82V82 include dual DSP processors with L1/L2 Memory and cache, AHB-Lite bus architecture, Multi-layer bus matrix, powerful AHB peripherals such as HWE and EDMA to offload the DSP processor loading, and rich APB peripherals such as a 16-ch ADC, Timers, I2C, SPI and UART interfaces. After Power-on, the HT82V82 provides an extremely flexible boot sequence which can be user modified. After the program code and the complete system is ready, sensor data input to VIU, processed by dual DSPs & HWE, is then output through VOU.

There are 3 ways provided to update program code in the external Nor Flash for the DSP to execute: ISP, IAP and ICE. The HT82V82 also includes a strong security mechanism to protect customer’s program codes located in the external Nor Flash from being copied or cracked.

Bus ArchitectureThe HT82V82 consists of 12 masters and many slaves within the bus architecture. Each DSP core IBus & DBus, PDMA, EDMA and HWE are masters while the internal L1 and L2 SRAM access buses, the AHB peripherals access bus, and the AHB to APB bridge are slaves. All of the master buses are based on the 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The DSP processor includes two AHB-Lite buses: IBus & DBus. All memory accesses of the DSP processor are executed on the two buses according to the different purposes and the target memory spaces. The memory organisation uses a Harvard architecture, pre-defined memory map and up to 4GB of memory space, making the system flexible and extendable.

The IBus is used for instruction and vector fetches from the Code region (0x0000_0000~0x1FFF_FFFF) to each DSP core. The DBus is used for loading/storing of data and also for debug access of the Code region. Figure shows the bus architecture of the HT82V82.

AHBdevices

PDMA AHB2APBbridge

APB

APB devices

ILM ILM

DBus IBUS

DLM DLMDSP0

Icache DcacheFPU

DBus IBUS

Multi-layer AHB

L2 SRAMBootROM

DSP1

Icache DcacheFPU

Bus Architecture

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ResetThe Reset Control Unit consists of three reset sources: power-on reset, external reset and Watchdog reset. The power-on reset, known as a cold reset, resets the full system during a power up. The power-on reset unit contains a POR reset, a brown-out reset and LVR reset. The POR reset contains 2 sources, one is the 3.3V POR to detect the IO Power line and the other is the 1.0V POR to detect the Core Power line. The generated reset outputs are Global reset, AHB/APB unit reset and JTAG reset. The Global reset resets the processor core and the AHB/APB peripheral IP components. Each functional IP connected to the AHB and APB buses can be reset individually through the associated software reset bits in the registers.

ClockThe Clock Control unit, CKCU, provides the func-tions of High speed external crystal oscillator (HSE), Phase Lock Loop (PLL), clock prescaler, clock mul-tiplexer and clock gating. The AHB, APB and DSP clocks are derived from the system clock (CK_SYS) which can be sourced from either the HSE or PLL. The Watchdog Timer uses 1/2048 of HSE as its clock source. The DSP clock fCK_DSP can be up to 250MHz, the AHB clock fCK_AHB can be up to 125MHz and the DDR clock fCK_DDR can be up to 400MHz for the DDR3 memory. The features are listed below:

• 32MHz external crystal oscillator – HSE• 2 programmable PLLs for AHB system clock, DSP

clock, DDR clock and sensor clock

DSP CoreThe dual-core DSP processors offer performance up to 250MHz each, applying to IEEE 754 Compliant single-precision floating-point operations and single- instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. Each core contains the following features:

• Up to 250MHz• 5-stage pipeline• Dynamic branch prediction• I/D Caches, 2-way set-associative, up to 32KB each• IEEE 754 compliant single precision floating-point • Nested interrupt controller with programmable

priority levels• 16/32-bit instructions• SIMD instructions• General DSP instructions• Rich featured Video instructions

Instruction SetCommon DSP instructions are encoded into 32-bit opcodes representing fully featured multifunction in-structions. The instruction set has been optimised so that 16-bit opcodes represent the most frequently used instructions resulting in excellent compiled code den-sity. A 32-bit instruction can be issued in parallel with two 16-bit instructions allowing the programmer to use many of the core resources in a single instruction cycle.

The instruction set also provides fully featured video instructions that allow the programmer to use many of the processor core resources in a single instruction for video processing. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code.

L1/L2 Memory StructureEach core implements a two-level memory architecture.

L1 memory system supporting the Harvard architecture is the highest-performance memory available to the DSP cores. Each core consists of a L1 32KB instruc-tion cache and a L1 32KB data cache. Each core also contains one 32KB block of L1 data local memory and one 16KB block of L1 instruction local memory.

Outside of the L1 domain, one 256KB block of L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design, which is arranged using a Von Neumann topology. There is one 8KB block of single-bank ROM connected on the AHB bus in the L2 do-main which contains boot code and safety functions.

Bus MatrixThe HT82V82 Multi-layer bus matrix accepts requests from AHB masters and dispatches the transactions to the target AHB slaves. The transactions from multiple masters can proceed simultaneously as long as there is no resource conflict. If both Master and Slave objects are different, both channels can be transferred inde-pendently. As shown below, Master 1 ↔ Slave 3, and Master 2 ↔ Slave1 can be transferred independently.

Bus Matrix Multi-layer Diagram

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AHB PeripheralsSome peripherals are connected to the AHB bus directly such as VIU, EDMA, DDR Controller, VOU, PDMA, Nor Flash Memory Controller and GPIO. The clocks of the AHB peripherals are always enabled after a system reset. Access to registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral registers in the AHB bus only support word access.

Video Input Unit – VIUThis contains the image capture interface to receive the CIS/CMOS data generated from sensor modules, and then implement further image signal processing. With a universal embedded Timing Generator it can be easily connected to commercial CMOS and CIS modules.

• CIS module ♦ Must operate together with Analog Front End

(AFE) ICs such as the HT82V48 ♦ Supports 3~6 ch sensors ♦ Provides Timing Generator ♦ Provides Image sensor shading correction ♦ Provides Image line information ♦ Provides integrated voltage comparator for roller

input signal• CMOS module

♦ Directly connected to CMOS sensor modules ♦ Up to 2048×2048 input resolution ♦ Supports 8-bit YUV422 and Raw RGB formats ♦ Up to 24MHz input pixel clock frequency ♦ V/HSYNC various settings for image capture ♦ Hardware window capture function ♦ Fractional hardware sub-sample function

CIS System Connection Diagram

Timing GeneratorThis is a programmable 96-step precision timing generator embedded with a DLL to execute timing fine tuning and generate signals for internal AFE sampling. The timing generator can also provide the CIS sensor related control timing. The device supports up to 6 lamps, CIS_RLED, CIS_GLED, CIS_BLED, CIS_IRLED, CIS_IR2LED and CIS_UVLED. The on and off points are individually programmed for each LED output. The LEDs can be on simultaneously if desired and permitted by the CIS and system design. The features are listed below:

• Up to 12 LED Light sequences and up to 6 LED light combinations Example: LED Light sequence R G B IR R G B UV → sequence is 8, combination is 5

• Programmable position for LED on-off• Programmable total pixels per line• Programmable sensor data captured position

CIS_CLK

CIS_SP

CIS_RLED

ʃʃ ʃʃʃʃ

CIS_GLED

ʃʃ ʃʃʃʃ

CIS_BLED

CIS_UVLED

ʃʃʃʃʃʃʃʃ ʃʃ

ʃʃ ʃʃ

TG CIS Timing

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Auto Dark & White CorrectionThe device provides hardware shading correction. The shading correction includes dark and white cor-rection and up to 1584 elements with 6 independent coefficients for different colour LED lights. There is an embedded memory for coefficient storage which is pre-loaded by the SPI or EMIF interfaces.

The shading correction formula is as follows, New Element(n)=(Element(n)+Offset(n))×Gain(n), where Offset is 8-bit from 0 to -255, Gain is 10-bit from 0.00x~8.00x and where n is the number of sensor elements.

Line InformationThe device provides 80 bytes of line information for further signal processing. This includes maximum, minimum, summation and line Histogram. It also includes line index and roller information which is often used in computing the roller speed. A left and right boundary is provided which is necessary information when implementing image slant correction.

Frame Start MechanismA mechanism to control the image scan procedure is provided in the device. Users can choose a suitable control mechanism between frames (Images) either from the FRM_START pin or by setting the register to start a frame based on the system requirements.

CIS Applications VIU Frame Control Flow

Video Output Unit – VOUThis can be output to a standard ARM IC through a high speed up to 40MHz SPI interface and a LCD panel through the i80 and VGA modes.

VOU 4-wire Serial SPI features are listed below:

• Supports Master and Slave for Raw Data or JPEG compressed data.

• VO_SCK can be up to 40MHz.• SPI_INT is an interrupt output to inform ARM that

HT82V82 is ready to transfer data.• ROLLER_OUT is a square wave output through

the HT82V82 internal comparator from the sine wave ROLLER_IN input. This is optional.

• V82_RSTn is used to reset HT82V82 by ARM. This is optional.

VOU System Connection for CIS Application

Hardware EngineThis includes Video processor and Neural Processing Unit, NPU, providing hardware implementation of signal and image processing algorithms to offload the dual-core DSP’s loading and accelerate video processing, as listed below:

• Scale Down• Rotation• Flip/Mirror/RT180• JPEG Encoder• Image Dilate and Erode• Split Character• Image Histogram• Image Binarization • Convolution• Neural Network

Enhanced Direct Memory Access – EDMAThis is used to transfer data within memory spaces or between a memory space and a peripheral. It supports two separate transfer channels where each channel consists of source and destination register sets.

It supports two types of DMA transfers, descriptor-based or register-based. Register-based DMA al-lows the processor to directly program DMA control registers to initiate a DMA transfer. On completion,

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the control registers may be automatically updated with their original setup values for continuous trans-fer. Descriptor-based DMA transfers require a set of parameters stored within the memory to initiate a DMA sequence, and allow multiple DMA sequences to be chained together and a DMA channel can be programmed to automatically set up and start another DMA transfer after the current sequence completes.

An EDMA transfer is defined in terms of three dimen-sions, defined as:

• 1st Dimension or Array (A): The 1st dimension in a transfer consists of ACNT contiguous bytes.

• 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of BCNT arrays of ACNT bytes.

• 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT ar-rays of ACNT bytes.

Peripheral Direct Memory Access – PDMAThe Peripheral Direct Memory Access circuitry, PDMA, provides 8 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfers. The memory-to-memory data transfer such as the SRAM-to-SRAM type is also supported and requested by the application program. Each PDMA channel configuration is independent. The PDMA channel transfer is split into multiple block transactions and the size of a block is equal to the block length multi-plied by the data width.

Features:

• 8 unidirectional PDMA channels• Memory-to-peripheral, peripheral-to-memory and

memory-to-memory data transfer• 8-bit, 16-bit and 32-bit width data transfer• Software and hardware requested data transfer with

configurable channel priority• Linear, circular and non-increment address modes• 4 transfer event flags – Transfer complete, Half

Transfer, Block End and Transfer Error• Auto-Reload function• ARMB AHB burst type can be: INCR_NONSEQ,

INCR, INCR4, INCR8

DDR2/3 SDRAM16/32-bit DDR2/DDR3 SDRAM Memory Controller with 512-Mbyte Address Space.

• Supports 16-bit DDR2/DDR3 SDRAM chips• Supports 16-bit and 32-bit LPDDR SDRAM chips

NOR Flash MemoryThis is used to store the user program code which can be encrypted by the security mechanism. It features a four-wire, SPI-compatible interface which occupies up to 16M bits.

SDIOThe SDIO HOST Controller supports Multi-Media Cards (MMC), SD Memory Cards and SD I/O cards. SDIO communication is based on an advanced 6-pin interface composed of one clock line, one command line and four data lines. The SDIO supports single block and multi-block data transfers and is compatible with the PDMA, minimising processor intervention for large data transfers.

General Purpose I/O – GPIOThere are up to 40 General Purpose I/O ports, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC7, for the device to implement the logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications.

The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the AF input or output pins.

The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI).

APB PeripheralsAn APB to AHB bridge provides the access capability between the DSP and APB peripherals. Some peripherals are connected to the APB bus such as BFTM, GFTM, WDT, I2C, SPI, UART, ADC and EPI. Additionally, the clocks of each APB peripherals are disabled after a system reset.

Basic Function Timer – BFTMThe Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate singe shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and single shot modes. The repetitive mode restarts the counter at each compare match event which is generated by the internal comparator. The BFTM also supports a single shot mode which will force the counter to stop counting when a compare match event occurs.

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General-Purpose Function Timer – GPTMThe General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.

Watchdog Timer – WDTThe Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value. Therefore, the software should reload the counter value before a Watchdog timer underflow occurs. In addition, a reset is also generated if the software reloads the counter before it reaches a delta value. This means that the Watchdog timer prevents a software deadlock that continuously triggers the Watchdog, the reload must occur when the Watchdog timer value has a value within a limited window of 0 and WDTD. The register write protection function can be enabled to prevent an unexpected change in the Watchdog timer configuration.

I2CThe I2C Module is an internal circuit allowing com-munication with an external I2C interface which is an industry standard two-line serial interface used for connection to external hardware. These two serial lines are known as the serial data line, SDA, and the serial clock line, SCL. The I2C module provides three data transfer rates: (1) 100kHz in the Standard mode, (2) 400kHz in the Fast mode and (3) 1MHz in the Fast-mode plus. The SCL period generation register is used to setup different kinds of duty cycle implemen-tation for the SCL pulse.

The SDA line which is connected to the whole I2C bus is a bi-directional data line between the master and slave devices used for the transmission and reception of data. The I2C module also has an arbitration detec-tion function to prevent situations where more than one master attempts to transmit data on the I2C bus at the same time.

SPIThe Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL. One SPI device acts as a master

which controls the data flow using the SEL and SCK signals to indicate the start of the data communication and the data sampling rate. To receive the data bits, the streamlined data bits which range from 1 bit to 16 bits specified by the DFL field in the SPICR1 register are latched on a specific clock edge and stored in the data register or in the Rx FIFO. Data transmission is carried in a similar way but in the reverse sequence. The mode fault detection provides a capability for multi-master applications.

UARTThe Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces and is also commonly used for RS232 standard communication. The UART peripheral function supports a variety of interrupts.

The UART module includes a transmit data register TDR, a transmit shift register TSR, a receive data register RDR and a receive shift register RSR. Software can detect a UART error status by reading the UART Status & Interrupt Flag Register, URSIFR. The status includes the condition of the transfer op-erations as well as several error conditions resulting from Parity, Overrun, Framing and Break events.

The UART includes a programmable baud rate gen-erator which is capable of dividing the UART clock of the CK_APB (CK_UART) to produce a baud rate clock for the UART transmitter and receiver.

Analog to Digital Converter – ADCA 10-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 16 exter-nal channels on which an external analog signal can be supplied. If the input voltage is required to remain within a specific threshold window, the Analog Watch-dog function will monitor and detect the signal. An interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D conversion can be operated in single shot, continuous and discontinuous conversion mode. A left-aligned or right-aligned 16-bit data regis-ter is provided to store the data after conversion.

External Parallel Interface – EPIThe External Parallel Interface, EPI, is used to trans-fer parallel data between the external device and in-ternal memory through the GPIO interface using the internal DMA engine. The EPI supports both Master mode and Slave modes, selected by the EPICR1 reg-ister. The EPI supports an 8/16-bit data bus, the clock input SCLK pin for Slave Mode, the WRN/RDN out-

Rev. 1.00 20 November 19, 2019

HT82V82

put pin for Master Mode and handshaking pins with DREQ input pin and DACK output pin. To receive the data bits, the 8/16-bit data bus specified by the EPICR1 register is latched on a specific clock edge and stored in the data register or in the Rx FIFO. Data transmission is carried in a similar way but in the reverse sequence.

Voltage ComparatorThe comparator deals with an analog roller signal and converts it into a digital signal for internal use or outputs it onto the ROLLER_OUT pin for external usage. The reference voltage to be compared is pro-grammed using a 5-bit register.

Boot Sequence The boot sequence is a process by which the device’s memory is loaded with program and data sections and by which some of the device’s internal registers are programmed with predetermined values. The boot sequence is started automatically after a device-level global reset. The bootloader is divided in two parts. These are the Boot code Starter in internal boot ROM and the Main boot code in the external NOR flash to make the boot sequence more flexible.

Program Code UpdateThere are 3 ways to update the program code for the DSP to execute:

• ISP: UART In te r face ; Burn code for the development and validation of programs

• IAP: SPI or I2C Interface; Burn code for a product online update

• ICE: JTAG Interface; Download or Burn code for development of programs using AICE

Development System Block Diagram

Boot Security The program code is encrypted when located in external NOR flash memory and is decrypted and authenticated when loaded during a secure boot. This protects customer’s IP and allows them to securely set up the system and begin device operation with trusted program code.

The Basic Secure Boot uses an AES-128 and/or pro-prietary simple data scramble method for program code encryption, and uses an SHA-256 for program code validation.

A 128-bit security key can be freely generated by users and then written to the embedded one-time-programming non-volatile memory. For more details on the supported security features or the Basic Secure Boot, refer to the related document.

Security System Block Diagram

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HT82V82

Timing Diagram

SPI Interface Timing

SCK(CPOL=0)

SCK(CPOL=1)

MOSI

MISO

MOSI

MISO

tSCK

tSCK(H) tSCK(L)

DATA VALID DATA VALID DATA VALID

tSU(MI)

tV(MO) tH(MO)

tH(MI)

DATA VALID DATA VALID DATA VALID

tV(MO) tH(MO)

DATA VALID DATA VALID DATA VALID

DATA VALID DATA VALID DATA VALID

tSU(MI) tH(MI)

CPHA=1

CPHA=0

SPI Timing Diagram – SPI Master Mode

SCK(CPOL=0)

SCK(CPOL=1)

MOSI

MISO

tSCK

tSCK(H) tSCK(L)

MSB/LSB IN

tH(SI)

tSU(SEL) tH(SEL)

tSU(SI)

LSB/MSB IN

MSB/LSB OUT LSB/MSB OUT

tA(SO) tV(SO) tH(SO)tDIS(SO)

SEL

SPI Timing Diagram – SPI Slave Mode with CPHA=1

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HT82V82

Symbol Parameter Conditions Min. Typ. Max. UnitSPI Master Mode

fSCK(1/tSCK) SPI Master Output SCK Clock Frequency

Master mode, SPI peripheral clock frequency fAPB_CLK

— — fAPB_CLK/2 MHz

tSCK(H)

tSCK(L)SCK Clock High and Low Time — tSCK/2-2 — tSCK/2+1 ns

tV(MO) Data Output Valid Time — — — 5 nstH(MO) Data Output Hold Time — 2 — — nstSU(MI) Data Input Setup Time — 5 — — nstH(MI) Data Input Hold Time — 5 — — nsSPI Slave Mode

fSCK(1/tSCK) SPI Slave Input SCK Clock Frequency Slave mode, SPI peripheral clock frequency fAPB_CLK

— — fAPB_CLK/3 MHz

DutySCK SPI Slave Input SCK Clock Duty Cycle — 30 — 70 %tSU(SEL) SEL Enable Setup Time — 3×tAPB_CLK — — nstH(SEL) SEL Enable Hold Time — 2×tAPB_CLK — — nstA(SO) Data Output Access Time — — — 3×tAPB_CLK nstDIS(SO) Data Output Disable Time — — — 10 nstV(SO) Data Output Valid Time — — — 25 nstH(SO) Data Output Hold Time — 15 — — nstSU(SI) Data Input Setup Time — 5 — — nstH(SI) Data Input Hold Time — 4 — — ns

I2C Interface Timing

tSU(STA)

tH(STA)

tFALL

tSCL(L)

tRISE

tSCL(H)

tH(SDA) tSU(SDA)tSU(STO)

SCL

SDA

tVD(SDA)

I2C Timing Diagram

Symbol ParameterStandard Mode Fast Mode Fast Plus Mode

UnitMin. Max. Min. Max. Min. Max.

fSCL SCL Clock Frequency — 100 — 400 — 1000 kHztSCL(H) SCL Clock High Time 4.500 — 1.125 — 0.450 — µstSCL(L) SCL Clock Low Time 4.500 — 1.125 — 0.450 — µstFALL SCL and SDA Fall Time — 1.300 — 0.340 — 0.135 µstRISE SCL and SDA Rise Time — 1.300 — 0.340 — 0.135 µstSU(SDA) SDA Data Setup Time 500 — 125 — 50 — ns

tH(SDA)SDA Data Hold Time (1) 0 — 0 — 0 — nsSDA Data Hold Time (2) 100 — 100 — 100 — ns

tVD(SDA) SDA Data Valid Time — 1.600 — 0.475 — 0.250 µstSU(STA) START Condition Setup Time 500 — 125 — 50 — nstH(STA) START Condition Hold Time 0 — 0 — 0 — nstSU(STO) STOP Condition Setup Time 500 — 125 — 50 — ns

Note: 1. This characteristic parameter of the I2C bus timing is based on: COMB_FILTER_En=0 and SEQ_FILTER=00.2. This characteristic parameter of the I2C bus timing is based on: COMB_FILTER_En=1 and SEQ_FILTER=00.

Rev. 1.00 23 November 19, 2019

HT82V82

Application Circuit

DQ

[8:1

5]

DQ

[8:1

5]

DQ

[16

:23

]D

Q[2

4:3

1]

DQ

[16

:23

]D

Q[2

4:3

1]

VOU_SPI

DQ

[0..7

]

DM

[0:1

]

DQ

S_

P0

DQ

S_

N0

DQ

S_

P1

DQ

S_

N1

DQ

[0:7

]

DQ

S_

P0

DQ

S_

N0

DQ

S_

P1

DQ

S_

N1

DQ

S_

P2

DQ

S_

N2

DQ

S_

P3

DQ

S_

N3

DM

[2:3

]

DQ

S_

P2

DQ

S_

N2

DQ

S_

P3

DQ

S_

N3

CIS

1_

RL

ED

CIS

1_

BL

ED

CIS

1_

GL

ED

CIS

1_

IRL

ED

CIS

1_

UV

LE

D

CIS

2_

UV

LE

DC

IS2

_IR

LE

DC

IS2

_G

LE

DC

IS2

_B

LE

DC

IS2

_R

LE

D

CIS

1_

RL

ED

CIS

1_

BL

ED

CIS

1_

GL

ED

CIS

1_

IRL

ED

CIS

1_

UV

LE

D

CIS

2_

RL

ED

CIS

2_

BL

ED

CIS

2_

GL

ED

CIS

2_

IRL

ED

CIS

2_

UV

LE

D

DM

[0:3

]

+3

.3V

CIS

2_

IR2

LE

D

+3

.3V

_C

MP

+3

.3V

PL

L_

+1

.0V

+1

.0V

+1

.0V

DD

R_

+1

.5V

DD

R_

+1

.5V

AD

C_

+3

.3V

VC

C3

3_

OS

C

DD

R_

+1

.5V

+3

.3V

VO

U_

SD

O

VO

U_

SD

I

UA

RT

_R

X

VO

U_

SC

K

VO

U_

CS

N

VO

U_

INT

UA

RT

_T

X

RO

LL

ER

_IN

FR

M_

ST

AR

TF

RA

ME

_E

N

GP

IO[0

:15

]

HT

82

V8

2D

R_D

Q[0

:7]

DR

_D

Q[8

:15]

DR

_D

Q[1

6:2

3]

DR

_D

Q[2

4:3

1]

DR

_A

[0:1

4]

DR

_B

A[0

:2]

DR

_C

K0

DR

_C

KB

0

DR

_C

K1

DR

_C

KB

1

AF

E1_D

IN[0

:15]

AF

E2_D

IN[0

:15]

AF

E1_A

DC

K

AF

E1_S

HD

CIS

1_M

OD

E

AF

E2_A

DC

K

AF

E2_S

HD

CIS

1_R

LE

D

CIS

1_G

LE

DC

IS1_B

LE

D

CIS

1_IR

LE

D

CIS

2_R

LE

D

CIS

1_IR

2LE

DC

IS1_U

VLE

D

CIS

2_G

LE

DC

IS2_B

LE

D

CIS

2_IR

LE

D

CIS

2_IR

2LE

DC

IS2_U

VLE

D

GND

VCC3IO

VCCK

VCC15O_DDR

VCC15O_DDRCK

VCC10A_DDR

VCC10A_PLL

VCC3IO_OSC

VCC3A_CMP

XIN

XOUTC

MP

_IN

AF

E_M

DA

T

AF

E1_M

CS

NA

FE

2_M

CS

N

AF

E_M

CK

CIS

_C

LK

CIS

_S

P

DR

_C

SN

DR

_W

EN

DR

_R

AS

ND

R_C

AS

N

DR

_C

KE

DR

_D

QS

B1

DR

_D

QS

1

DR

_D

QS

2D

R_D

QS

B2

DR

_D

QS

B0

DR

_D

QS

B3

DR

_D

QS

0

DR

_D

QS

3

DR

_O

DT

0

DR

_O

DT

1

DR

_R

ES

ET

N

VCC10A_DLL

VCC3IO_ADCVCC3A_ADC

PA

[0:1

5]

DR

_V

RE

F[0

:3]

DR

_D

M[0

:3]

PB

[0:1

5]

TEST

VO_SDI

VO_SDO

VO_SCK

VO_CSN

BO

OT

_E

N

UR0_TX

UR0_RX

VO_INT

FR

M_S

TA

RT

FR

M_E

N

RS

TN

GND3IO_OSC

CIS

2_M

OD

E

3.3

Vac

0V

dc

10

0K

1M

DD

RIII1

DQ

[0:7

]A

[0:1

4]

DQ

[8:1

5]

CK

EC

KP

CK

N

BA

[0:2

]

/CS

/WE

/RA

S/C

AS

DM

[0:1

]

OD

T

RE

SE

Tn

DQ

S_P

0

DQ

S_P

1

DQ

S_N

0

DQ

S_N

1

32

MH

z

V4

8

D[1

5:0

]

AD

CK

SH

SC

K

SD

SE

B

VIR

1

VIR

2

VIG

1

VIG

2

VIB

1

VIB

2

V4

8-1

D[1

5:0

]

AD

CK

SH

SC

K

SD

SE

B

VIR

1

VIR

2

VIG

1

VIG

2

VIB

1

VIB

2

1K

±1

%

CIS

_S

EN

SO

R

CLKSI

SE

L

SIG

[1:5

]

RLE

DB

LE

DG

LE

DIR

LE

DU

VLE

D

1K

±1

%

0.1

uF

12

pF

CIS

_S

EN

SO

R1

CLK SI

SE

L

SIG

[1:5

]

UV

LE

DIR

LE

DG

LE

DB

LE

DR

LE

D

12

pF

0.1

uF

0.1

uF

DD

RIII

DQ

[0:7

]A

[0:1

4]

DQ

[8:1

5]

CK

EC

KP

CK

N

BA

[0:2

]

/CS

/WE

/RA

S/C

AS

DM

[0:1

]

OD

T

RE

SE

Tn

DQ

S_P

0

DQ

S_P

1

DQ

S_N

0

DQ

S_N

1

Rev. 1.00 24 November 19, 2019

HT82V82

Package Information

Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information.

Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page.

• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)

• Packing Meterials Information

• Carton information

Rev. 1.00 25 November 19, 2019

HT82V82

256-pin TFBGA (11mm×11mm) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A 0.036 0.041 0.045

A1 0.006 0.008 0.010A2 0.030 0.032 0.035b 0.010 0.012 0.014D 0.429 0.433 0.437

D1 — 0.384 BSC —E 0.429 0.433 0.437

E1 — 0.384 BSC —e — 0.026 BSC —

SE — 0.013 BSC —SD — 0.013 BSC —

SymbolDimensions in mm

Min. Nom. Max.A 0.91 1.03 1.15

A1 0.16 0.21 0.26A2 0.75 0.82 0.89b 0.25 0.30 0.35D 10.90 11.00 11.10

D1 — 9.75 BSC —E 10.90 11.00 11.10

E1 — 9.75 BSC —e — 0.65 BSC —

SE — 0.325 BSC —SD — 0.325 BSC —

Rev. 1.00 26 November 19, 2019

HT82V82

Copyright© 2019 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.