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HT45F4050 NFC Function Application Note
AN0491E V1.00 1 / 12 October 11, 2018
HT45F4050 NFC Function Application Note
D/N: AN0491E
Introduction This application note will introduce various aspects of the HT45F4050 device NFC
function including the hardware circuit, antenna design, antenna layout, antenna
measurement, NFC memory description, software description, program flowchart and
operating instructions.
Functional Description The HT45F4050 NFC core consists of four main parts, the modulation circuit, NFC state
machine, NFC memory and a HT-8Bit MCU. The specific architecture is shown in the
figure below.
Operating Principles NFC, which is an acronym for Near Field Communication, is a technology allowing
wireless connection between devices using a simple touch. NFC technology operates at a
frequency of 13.56MHz with an operating distance within 10cm. It has three data rates of
106Kbit/s, 212Kbit/s and 424Kbit/s, and supports three operating modes. These are card
emulation, card read/write and P2P. Its operating standard is compatible with Sony’s
FeliCa standard (Type F) and Philips’ MIFARE standards (ISO 14443A – Type A; ISO
14443B – Type B).
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The HT45F4050 supports a data rate of 106Kbit/s and is mainly used for card emulation.
It follows the ISO14443A Type A standard.
Hardware Description
MCU電路 天線電路 主動設備MCU Circuit Antenna Circuit Active Device
Application Circuit The application circuit is composed of two main sections which are the MCU circuit
and the antenna circuit.
C3 and C4 are the antenna matching capacitors.
Communication can only be initiated by the active device which implements data
exchange with the HT45F4050 via the antenna.
Antenna Design Step 1: Decide upon an antenna layout method. Holtek has provided four layout methods, for
more information refer to the attachment “HT45F4050 Antenna pcb”.
Rectangular antenna double-layer layout. For example, the top and bottom layers
each contain three turns.
Rectangular antenna single-layer layout. For example, the top layer contains six turns
with an outer size of 29mm × 29mm.
;
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Round antenna double-layer layout. For example, the top and bottom layers each
contain five turns.
Round antenna single-layer layout. For example, the top layer contains twelve turns
with an outside diameter of 19.05mm.
Step 2: Calculate the NFC antenna inductance. Open the “HT45F4050 NFC antenna calculator
v1.2” excel file enclosed in the Attachment section.
Open the NFC Antenna Inductance Value page. Determine the antenna size, track width,
track gap, track thickness and number of turns and then enter these parameters into the
following table. When this is done an inductance value will be generated automatically, as
shown below.
Rectangular Antennas (Single-layer Layout) Overall dimensions of the coil(ao) in mm 45 Overall dimensions of the coil (bo) in mm 65 Track width (w) in mm 0.3048 Track thickness (t) in mm 0.035 Cap between tracks (g) in mm 0.3048 Number of turns (Na) 4 Inductance (La) in µH 2.51634317
Inductance Calculation Table for Rectangular Antennas Single-layer Layout
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Step 3: Enter the generated inductance value into the red box shown in the following Calculator
1 table, where the resonant frequency is fixed at 13.56MHz. After this a matching
capacitance value will be generated automatically. In the following example, the
calculated matching capacitance is 54.75pF.
Capacitance Calculator 1 Inductance in µH 2.51634317 Resonant Frequency in MHz 13.56 Capacitance in pF 54.74582639
Matching Capacitance Calculation Table
Antenna Layout
NFC Antenna Board Single-layer Rectangular Layout – 45mm × 65mm
This NFC antenna test board is designed following the above steps. It adopts the
rectangular antennas single-layer layout method and has an outer size of 45mm×65mm.
C1, C2 and C3 are matching capacitors. J2 and J3 are connected to the HT45F4050 LA
and LB pins respectively. For more PCB layout details, refer to the enclosed file
“HT45F4050 Antenna pcb”.
Antenna Measurement The designed NFC antenna board should be measured.
Equipment
An oscilloscope, a signal generator and two loop antenna boards are required to make
the measurements.
There are two kinds of loop antenna test boards as follows. Their PCB files are
enclosed in the Attachment section.
HT45F4050 NFC Function Application Note
AN0491E V1.00 5 / 12 October 11, 2018
ISO 10373-7 Standard Loop Antenna Test Board
Receiver Loop Antenna Test Board
Test Environment
The oscilloscope’s probe is connected to the ISO 10373-7 loop antenna or
receiver loop antenna depending on the antenna size to be measured. If the
antenna size is small, the oscilloscope’s probe is connected to the receiver loop
antenna. If the antenna size is large, the oscilloscope’s probe is connected to the
ISO 10373-7 loop antenna.
The two ends of the signal generator are connected to the ISO 10373-7 standard
loop antenna test board.
The antenna to be measured is placed between the two loop antenna test boards.
Test Environment Diagram
Measure Steps
Set the signal generator to output a 5V peak-to peak sine wave.
Adjust the signal generator frequency. Increase the frequency starting from 5MHz,
then use the oscilloscope to find the frequency that has the maximum voltage
amplitude.
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Measure Result Evaluation
If the measured maximum amplitude frequency is 13.56MHz, it means that the
matching capacitance is matched. The antenna measurement is now complete.
If the measured maximum amplitude frequency is not 13.56MHz, for example,
15MHz, this means that matching capacitance tuning is required.
Capacitance Tuning
Open the “HT45F4050 NFC antenna calculator v1.2” excel file.
Open the Antenna Measure page, substitute the resonant frequency value of
15MHz and the capacitance which is equal to the PCB capacitance plus a
parasitic capacitance of 10pF, into Calculator 2 to calculate the inductance value.
Capacitance Calculator 2 Capacitance in pF 42 Resonant Frequency in MHz 15 Inductance in µH 2.680454594
Calculator 2 Inductance Calculation Table Substitute the calculated inductance and the fixed resonant frequency value of
13.56MHz into Calculator 1 to calculate the matching capacitance value.
Capacitance Calculator 1 Capacitance in pF 2.680454594 Resonant Frequency in MHz 13.56 Capacitance in pF 51.3940011
Calculator 1 Matching Capacitance Calculation Table Solder a capacitor, which is equal to the calculated capacitance minus the
parasitic capacitance of 10pF, to the PCB. Capacitance tuning is now complete.
NFC Memory Description
HT45F4050 NFC Memory Table
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The HT45F4050 NFC memory is organized into 80 pages with each page containing 4
bytes, resulting in a total of 320 bytes. The first 16 bytes are reserved for the
programmer while the remaining 304 bytes are available for use by the user.
The first 16 bytes from Page 0 to Page 3 contain the serial numbers, lock bytes, etc.,
which are provided for program initialisation. For more detailed definition of these 16
bytes, refer to the Near Field Communication chapter in the HT45F4050 datasheet.
The 240 bytes from Page 4 to Page 63 belong to the EEPROM, and are available for
use by the user. The user-defined data in this section will be retained after power off.
The 64 bytes from Page 64 to Page 79 belong to the SRAM, and are available for use by
the user. However, the user-defined data in this section will not be retained after power off.
Software Description
Software control involves several registers, which are the NFCCTRL, NFC_INTE,
NFC_STATUS, and INTC3 registers. For a detailed NFC register introduction, refer to the
Near Field Communication chapter in the HT45F4050 datasheet. Detailed program
examples are provided in the “NFC_Example V1.0” file enclosed in the Attachment section.
Program Flowchart Start
System crystal initialisation
Configure NFCCTRL register
Configure NFC_INTE register
Enable global interrupt and NFC interrupt
Wait for NFC_STATUS register setup finished
Configure NFC Memory first 4 pages
Main loop
Enter the NFC interrupt subroutine
Enter the NFC interrupt subroutine
Active device reads from or writes to the
NFC Memory?
MCU reads from or writes to
NFC Memory?
YY
NN
Program Flowchart
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Operating Instructions
Use a mobile phone which supports an NFC function to install the
“NFCTestTool_20180306.apk” file provided in the Attachment section. After installation,
the interface will appear as follows.
Addr indicates the NFC memory page address. Enter a value in decimal format.
The four bytes, D0, D1, D2 and D3 should also be entered with values in decimal
format.
Construct a hardware circuit demo as shown below. Note that this demo can be made
according to the user’s requirements.
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Page write operation. For example, write data 1, 2, 3, 4 to Page 64.
Fill in the data to be written and then click “WRITE”:
Place the phone’s NFC sensor close to the NFC antenna board:
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Page read operation. For example, read data from Page 64.
Fill in the page address to be read and then click “READ”:
Place the phone’s NFC sensor close to the NFC antenna board:
Page read operation reads 16 bytes once. The first 4 bytes, 0x01, 0x02, 0x03 and 0x04,
is the data in Page 64.
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Attachment
HT45F4050 NFC antenna calculator v1.2.zip
ISO_10373-7_antenna.7z
Receiver_loop_antenna.7z
HT45F4050 Antenna pcb.7z
NFCTestTool_20180306.7z
NFC_Example V1.0.7z
Conclusion This application note has introduced how to use the HT45F4050 NFC function, from the
aspects of the hardware circuit, antenna design, antenna layout, antenna measurement,
NFC memory description, software description, program flowchart and APP operating
instructions. By providing users with a comprehensive understanding of the hardware
architecture and software procedure of the HT45F4050 NFC function as well as
considerations regarding NFC function development, this application note should help
users complete their development of NFC function applications faster.
Versions and Modification Information Date Author Issue Release and Modification
2018.5.8 陈烁烨(Albert, Chen) First version
Reference File
Reference file: HT45F4050 datasheet.
For more information refer to the Holtek’s official website www.holtek.com.
HT45F4050 NFC Function Application Note
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