How to Design a GaN PA MMIC

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Technology Overview

How to Design aGaN PA MMIC

This white paper describes how todesign a custom GaN PA MMICusing a commercially availableGaN-on-SiC foundry process. Ituses an X-band PA requirementas the design example, and runsthrough the design process step-by-step to the point of having acompleted MMIC layout readyfor manufacture. It commenceswith selection of the mostappropriate GaN MMIC processthen moves on to transistor levelsimulations including load-pullanalysis to determine theoptimum impedances at bothfundamental and harmonics. Thisleads on to the detailed schematicdesign and MMIC layout method-ology. Finally the approach forperforming electromagnetic (EM)simulation and layout optimis-ation is described.

Figure 1: Active phased array radars need a solid-state PA for eachelement

PA applicationThe example PA used to illustrate thedesign process is an X-band (8 –12GHz) PA for a phased array radar ap-plication. X-band radar applications in-clude weather surveillance radar, milit-ary radar, and those used for air-trafficcontrol. Increasingly these are activeaperture phased array radars, for whichmultiple solid-state PAs are needed, asshown on the right-hand side in Figure1. The active array approach enablesthe radar to position the beam muchmore rapidly using electronic steeringrather than traditional mechanicalsteering, and can generate multiple in-dependent beams.

There may be hundreds or even thou-sands of elements in an active phasedarray, so even a small improvement inPA efficiency or a reduction in size andweight will have a massively beneficialeffect on the performance of the entiresystem. Realising the PA as a GaN

MMIC offers advantages in all of theseareas.

Advantages of GaN-on-SiCGaN-on-SiC has become the techno-logy of choice for high-power solidstate amplifiers. In addition to highpower density and high efficiency, us-ing GaN devices in a PA also enablesoperation at a high voltage, whichmeans that it can be matched to higheroutput impedances compared to otherdevice technologies such as GaAs. Thismeans that matching networks can besimpler, reducing transmission linelosses. The higher voltage also meansthat they can operate at lower currentlevels, reducing I²R losses. The powerdensity of GaN is four to five timeshigher than that of GaAs, which meansthat the MMICs can be smaller, result-ing in a compact, lightweight finaldesign with good reliability. The SiCsubstrate has high thermal conductivity,making it easy to remove heat from the



with a target small-signal gain of 25dB.For a phased array radar application,the power amplifier is run highly com-pressed, so the output power is spe-cified at 4dB compression with a targetof +40dBm and power added efficiency(PAE) of greater than 30%. Input returnloss should be better than 10dB, and theoperating voltage is set at 28V.

Selecting the most appropriate MMICprocess for the intended application isvery important if optimum PA perform-ance is to be obtained. The maximumoperating frequency of the process, therequired gain, operating voltage andpower density must all be assessed. An-other consideration is to ensure that theProcess Design Kit (PDK) models for

the transistors and passive componentsprovided by the foundry are valid andaccurate over the required frequencyrange so that the final PA will give agood agreement with the simulation.

Having established that GaN-on-SiC isvery well suited for the planned applic-ation, and for microwave PAs in gen-eral, there are a number of commer-cially available processes that could beconsidered. For this design the Wolf-speed V5 process was selected. Table 2summarises the process capabilities;GMAX and power density figures arequoted at 30GHz and will be signific-antly better at 10GHz. The MTTF(Mean Time To Failure) is quoted as106 hours at 225°C. To achieve the

device, and allows the device to operateat higher channel temperatures for thesame mean time to failure (MTTF).

Design stepsThe design begins with the selection ofthe process and then moves onto devicelevel simulations, selecting the tran-sistor unit cell size, the bias point, andthe load and source impedances. Thispreliminary transistor analysis data isthen used to determine the number ofstages needed to meet the specification,the number of transistors in the outputstage, and the ratio between the drivertransistor(s) and the output transistors.From here, the detailed schematicdesign can be performed with optimisa-tion of bias networks and matching net-works. A preliminary layout can thenbe produced from the schematic designand EM simulations are conducted tooptimise and finalise the design. Thelayout is run through a design rulechecker (DRC) to make sure that thefoundry will be able to fabricate thedesign.

Specification and process selectionTable 1 gives a top level specificationfor a PA, which was used as the designexample. The amplifier requires a2GHz bandwidth centred on 10GHz,

Table 1: Example PA specification for phased array radar application

Table 2: Wolfspeed V5 process capability overview

the same 10W power output. The GaAsIC would require eight transistors, witha complex arrangement of transmissionlines to combine the power, which addsloss. In contrast the GaN-on-SiC designrequires only two transistors, reducingloss and increasing PAE and making iteasier to pass the bias evenly to thetransistors. Because there are fewerloops, there is less chance of odd-mode

instabilities occurring. It also clearlyresults in a MMIC with a much smallerdie area, which simplifies the designprocess and gives a higher probabilityof a ‘right first time’ design.

Design ApproachHaving decided on a suitable process,device-level simulations can begin. TheV5 transistors have high gain and are

same reliability from a GaAs device itwould need to be running at about150°C, so there is a significant advant-age in using GaN-on-SiC for this ap-plication, as it reduces the cooling re-quirements of the radar system. Theavailability of device models that arevalid between VDS values of 10V and28V and 10 – 300mA/mm means thatsimulations can be carried out over awide range of bias conditions with theconfidence that the resulting MMICwill be ‘right first time’ and that itsmeasured performance will be well-represented by the design simulations.

A cross-section of the V5 process is de-picted in Figure 2. It has a 0.15µm gatelength and breakdown voltage of 84V,an RF power density of 3.75W/mm at30GHz, and a SiC substrate thicknessof 75µm. The process offers the stand-ard MMIC passive components (resist-ors, MIM capacitors and through-holesubstrate vias) and benefits from thehigh thermal conductivity SiC sub-strate.

GaAs vs GaN-on-SiCThe inherent performance advantagesof GaN-on-SiC also help to simplifypower combining. Figure 3 comparesthe circuit required on GaAs with theequivalent on GaN-on-SiC to achieve



Figure 2: Wolfspeed G28V5 GaN-on-SiC process

Figure 3: (a) GaAs PA versus (b) GaN PA power combining to achieverequired power



tion of a practical number of transist-ors.

The quiescent bias of the transistor im-pacts the small signal gain, the powertransfer characteristics and the linear-ity. These different performance re-quirements must be considered whendeciding on the optimum bias point.Figure 4 shows the maximum availablegain for an 8 x 150µm transistor at 28VVds with the bias current increasingfrom 10mA/mm up to 50mA/mm. Theeffect of the quiescent bias on the gaincompression can be evaluated usingload pull simulations at a later stage.

Thermal considerationsBecause of the high power density inGaN-on-SiC it is very important to en-sure that the heat can be dispersed effi-ciently. The silicon carbide substrate isan excellent thermal conductor, with aconductivity of around 450W/mK,which is around three times that of sil-icon and nine times that of GaAs. Thethermal conductivity is however tem-perature-dependent, so as it heats up itbecomes less efficient at removing the

conditionally stable at X-band. At theoutset of the design process it is normalto introduce resistive losses at the tran-sistor input to ensure that the transistoris unconditionally stable across the de-sired operating band, plus some guardband. The resistive losses can be re-duced as the detailed design progressesand practical losses of matching andcombining networks are introduced.Stability at lower frequencies must alsobe addressed as the design progresses,often during the design of the bias net-work. It is also important to confirm un-conditional stability at frequenciesabove the operating band.

To select the optimum unit gate width,different sizes can be compared. Tran-sistors with shorter unit gate width willbenefit from higher available gain butwill have a lower output power. The se-lection of the most appropriate tran-sistor size is one of the likely earlysteps in designing a microwave PA.The transistor needs to be small enoughto provide adequate gain but largeenough to allow the desired outputpower to be achieved by the combina-

Figure 4: Quiescent bias selection

heat. Although this happens in othersemiconductor materials, it is morepronounced in SiC, so this needs to betaken into consideration.

The die-attach material, usually solderor silver loaded epoxy, used to attachthe MMIC to the package or module isalso important thermally. Not only doesit need to have good thermal conductiv-ity, but the bond line thickness needs tobe kept as small as possible, and atten-tion needs to be paid to avoid gaps inthe die attach material after assembly, aphenomenon known as voiding.

It is also necessary to consider thethermal impact of the package and forSMT packaged parts the PCB. Keepingthe transistor’s operating temperatureas low as possible improves the reliab-ility of the amplifier.

One advantage of designing for radarapplications is that the PA will gener-ally be operating in pulsed mode, per-haps with a 10% duty cycle, whichmeans that less heat needs to be dissip-ated than with CW operation. However,as pulse widths get longer, the thermalconditions tend towards those of CWoperation. Thermal resistance stillneeds to be kept low to reduce pulsedroop – the phenomenon where the out-put power drops off towards the end ofthe pulse due to heating effects, whichcan affect the radar performance.

Transistor size selectionSmall-signal device-level simulationsare performed to evaluate availablegain in the intended operating band.For this design these simulations resul-ted in the selection of an 8 x 150µmtransistor with intra-source vias at anIDS of 20mA/mm, 28V bias point. The



on either side. Although this layout isslightly more compact, it is not quite asgood thermally. For this design theslightly larger intra-source transistorwas selected.

Load pullThe next stage of the design process isto carry out load pull simulations to de-termine how the selected transistor sizeperforms under large-signal operation.Within Keysight ADS there is a stand-ard test bench for transistor load pull. Ithas the advantage of being easy to setup, but it is also flexible, so it is pos-sible to tune the harmonics and set the

conditions to drive the transistor into asuitable mode of operation.

The area of the Smith Chart over whichto perform the load pull is first spe-cified, and the number of impedancepoints to simulate is chosen as a bal-ance between simulation time and ac-curacy. It is also important to ensure thetransistor is driven far enough intocompression, as this is where it is inten-ded to be used in its end application,but it must not be driven too hard as thismight cause simulation convergence is-sues. It can sometimes require someoptimisation to get the balance right.

Figure 6 shows the load pull simula-tions at 9GHz, which result in a set ofcontours that can be used to determinethe optimum impedances for PAE, out-put power and gain. In practice a com-promise between these three paramet-ers is selected as the design impedance.The control panel allows the selectionof the input power that corresponds tothe desired gain compression, and thenthe optimum impedance as well as theperformance figures can be read off. Inthis particular simulation the transistoris delivering almost 7W output power

layout of the transistor is shown on theright in Figure 5, and it can be seen thatthe intrasource via style of transistorhas vias in between the pairs of gate fin-gers. The yellow ovals represent thevias and the thin red lines show the gatefingers. There is a pair of gate fingerswith a via either side. Spacing out thesepairs of gate fingers means that they arefurther apart, which has thermal ad-vantages. Having more vias reduces theelectrical inductance, which is also fa-vourable for the performance. An al-ternative layout is an edge via layout,where the gate fingers are evenlyspaced and there are only two vias - one

Figure 6: Load pull simulations at 9GHz

Figure 5: Transistor size selection



Figure 7(a), top: Second harmonic load pull, and (b), bottom: Thirdharmonic load pull

on the left of Figure 7a for a funda-mental frequency of 10GHz; these sim-ulations can of course be repeated forother frequencies. The effect of secondharmonic load on power and PAE isshown on the right of Figure 7a. At aphase of 0°, corresponding to an opencircuit, the PAE (in red) is just less than60% and the delivered power (in blue)is around 38.3dBm. Both power and ef-ficiency can be increased by tuning thesecond harmonic to around 120°, butcare is needed to avoid the regionaround 150° where there is a dramaticdip in power and efficiency. It is alsoworth remembering that any secondharmonic tuning implemented on theMMIC should not adversely affect thefundamental load.

The effect of the third harmonic imped-ance on the power and efficiency canalso be simulated, as shown in Figure7b. Unlike the second harmonic, thereis not much performance advantage tobe gained by tuning the third harmonic,but the performance dip around 150°needs to be avoided.

PA Topology ConsiderationsAfter the device level simulations, thetopology of our PA can be determined.By estimating the gain per stage usingGMAX simulations and the losses as-sociated with the matching networks,splitting and combining networks andany other relevant components such asgain flattening networks, we can workout how many gain stages are required.

with an efficiency of around 60%. Itshould be noted that this is the perform-ance for the transistor alone, so it doesnot include any matching network orpower combining losses or the impactof the driver stage. The overall effi-ciency of the PAwill therefore be lowerthan that shown.

The simulation also allows the gaincompression to be inspected. The gatecurrent and the drain current can alsobe examined to look at the effects onthe power supply design. The reasonfor simulating at different frequenciesis to see how these impedances shiftwith frequency – one challenge ofdesigning matching networks is to tryto present the optimum impedance ateach frequency, and so this is some-thing that becomes increasingly diffi-cult the greater the design bandwidth.Load pull plots were also produced at10GHz and 11GHz. At 11GHz the op-timum output impedance is between15Ω and 20Ω. This is much higher thanan equivalent GaAs transistor deliver-ing the same power.

Further load-pull simulations can berun across a variety of different operat-ing conditions but in this case thesesimulations give us enough informationto assess the number of transistorsneeded at the output as well as the re-quired number of gain stages.

Harmonic Load-PullThe harmonic impedances must also beconsidered, particularly if the PA is op-erating heavily into compression. Tooptimise power and efficiency har-monic tuning of the load can be con-sidered, and to do this the phase of thesecond harmonic is swept around theedge of the Smith chart. This is shown



Figure 8: PA layout

too small, it will start compressing be-fore the output stage, and will not beable to supply sufficient power to drivethe output stage. This would then limitthe overall output power of the PA.

Detailed Schematic DesignThe PA design is progressed using theselected topology to the point of beingfully realised using all PDK componentmodels. Key considerations during theschematic design are matching, bias-ing, RF power combining/splitting andensuring broadband unconditional sta-bility.

The matching networks aim to presentthe desired impedances to the transist-ors for maximum performance. Shuntinductive elements at the transistor out-puts are frequently used to help com-pensate for the intrinsic drain-sourcecapacitance (CDS), whilst a low pass

structure transforms the output imped-ance. For the power-combined outputdevices, it is very important to preservethe symmetry of the load that is presen-ted to each output transistor.

The matching networks must also passgate and drain bias to the transistors.Drain bias is often injected via a shuntmatching inductor at its RF short point(capacitor to ground). Gate bias net-works include biasing resistance tolimit forward gate current whilst avoid-ing degradation of large signal per-formance that could occur if the resist-ors are too large.

The power combining of the outputtransistors should be integral to thematching network design, as this ap-proach minimises both the die area andassociated losses. When multiplepower combined transistors are used

Given the high gain of this process, ourtarget of 25dB small signal gain shouldbe achievable using just two stages.

Similarly, we can determine the num-ber and size of the transistors that mustbe combined in each stage of the ampli-fier to generate the required power. Ourdesign example uses two transistors inthe output stage with their outputspower combined to achieve the 10Woutput power target.

The size of the driver stage transistoralso needs to be carefully considered.Although there is always a lot of atten-tion devoted to the efficiency of theoutput stage, the driver stage efficiencywill also contribute to the overall PA ef-ficiency. If we make the driver stagetransistor too large, it will be inefficientand thus will degrade the overall PA ef-ficiency. However, if the driver stage is



Figure 10: Large signal PA performance

Low frequency stability must also beensured and suitable components canoften be added to the gate and drain bi-asing networks to ensure this. Aboveband stability must also be ensured upto the Fmax of the transistors.

LayoutThe schematic design must be trans-lated to an MMIC layout for fabrica-tion. This will include the addition ofinterconnect tracks that may have notbeen in the schematic simulation as

well as proximity and discontinuity ef-fects. These can be accounted for byEM simulation, discussed later. Thelayout tends to be a compromisebetween die size and risk. The smallerthe die size the lower the cost and thecommercial team will push for thesmallest possible die size. However, themore compact the design the greater thediscontinuities and circuit interactions.

Figure 8 shows a representative layoutof the two stage X-band GaN PA underconsideration with the RF input to theleft and the RF output to the right. Bothinput and output include Ground-Sig-nal-Ground (GSG) pads to allow RFOn Wafer (RFOW testing). The twopower combined output transistors canbe seen towards the output of the diefollowed by the matching and powercombing network. Odd-mode stabilisa-tion resistors are included between thetwo output transistors. The single tran-sistor used for the input stage can beseen to the left with its output matchingnetwork splitting into two to drive thetwo output devices. DC-blocking andstabilisation networks are included onchip. The DC and RF pads are all la-belled and their function can be easily

the possibility of odd-mode stability is-sues arise and loop stability analysisshould be performed to identify and re-solve any potential issues.

The input resistance added to the tran-sistors in the early stages of the designto ensure unconditional stability can bereduced as the practical losses of PDKmatching components are introduced.At microwave and mmWave frequen-cies additional resistive losses to ensurein-band stability are often unnecessary.

Figure 9: Small signal PA performance



Table 3: Phased array radar application

For PAs the EM network is normallybuilt up from output to input. This is anecessarily iterative process and can betime consuming but it is vital if bestperformance is to be obtained.

Simulated ResultsFigure 9 shows the simulated small-signal performance for the PA withgreater than 25dB gain across the inten-ded 9 – 11GHz band with some guardband both above and below band. Inputreturn losses are around 10 – 15dB. Asexpected for a PA, the output returnloss is lower than the input return lossas the output is matched for best largesignal performance resulting in a com-promise between PAE, output powerand gain.

Large-signal simulated performance isshown in Figure 10 and indicates anoutput power of greater than 40 dBm(10 W) across 8.5 – 11.5GHz andgreater than 40.5dBm in the designband. PAE is greater than 42.5% at 4dB

compression, which is particularly not-able for a two-stage design. Table 3compares the simulated performance tothe original target specification andshows that the target performance ismet.

SummaryActive phased-array radar is a key ap-plication for X-band power amplifiersand GaN-on-SiC technology has beenshown to have several key advantagesover other compound semiconductorprocesses. The G28V5 GaN-on-SiCprocess from Wolfspeed has inherentlyhigh gain which can reduce the re-quired number of gain stages in a radarsystem line-up and thus simplify thesystem design and increase PAE. Thedesign of a representative 9 – 11GHz10W PA has been outlined in this whitepaper and the simulated performanceindicates high output power and PAEacross the design band.

identified. The overall die size is 2.80 x1.60mm. For components intended forassembly into packages the layoutshould be optimised with the packagein mind and the IC to PCB transitions,including bondwire parasitics, must besimulated and accounted for.

EM SimulationEM simulation of the MMIC layout isvital to ensure best agreement betweenmodelled and measured performance.The foundry supplies an EM stack-upalong with the PDK that allows EMsimulation of all passive components tobe performed. The PDK transistormodels are then added to the EM simu-lated passive circuitry. It would be amistake to try and EM simulate the en-tire structure of a first pass MMIC lay-out in one go. The best approach is toEM simulate the MMIC a piece at atime, gradually increasing the extent ofthe EM simulation. The layout and theschematic design can be optimised asthe EM simulated network builds up.

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How to Design a GaN PA MMIC