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How Does FPGA Work
Arnaud TaffanelPeyman Pouyan
Advanced Digital IC Design
2008-2-19
Outline
FPGA Basics Virtex 5Power Consumption in FPGAsLow Power Approaches
FPGA Basics
CMOS Design Styles
STANDARDIC
FULLCUSTOM
SEMI-CUSTOM
ProgrammableLogic
STANDARDCELL
GATE ARRAY,SEA OF GATES CPLDFPGA
ASIC
Programmable Logic Main IdeaBasic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure
The interconnection between the logic blocksThe function of each block.
Different Programmable Logic Devices
Types of programmable logicProgrammable Logic Array (PLA)
Programmable AND Logic (PAL)
Complex Programmable Logic Device (CPLD)
Field Programmable Gate Array (FPGA)
Programmable Logic Array (PLA)
Two programmable planesAny combination of ANDs / OrsSharing of AND terms across multiple OrsProgrammable switches between horizontal and vertical lines
A B C D
Q0 Q1 Q2 Q3
ProgrammableAND array
ProgrammableOR array
Programmable AND Logic (PAL)One programmable plane - AND / fixed ORFinite combination of ANDs / OrsFewer switch countFaster than PLAs
A B C D
ProgrammableAND array
Fixed OR
Q0
Q1
Q2
Q3
Complex Programmable Logic Devices (CPLD)
Logic Block contains
PAL / PLARegisters
Interconnect includes
Full crossbarPartial interconnect
Prog
ram
mab
lein
terc
onne
ct
LogicBlock
LogicBlock
LogicBlock
LogicBlock
I/O
LogicBlock
LogicBlock
LogicBlock
LogicBlock
I/O
Why FPGAs?
Why FPGAs? (Contd.)Custom ICs sometimes designed to replace the large amount of glue logic
Reduced system complexity and manufacturing cost, improved performanceCustom ICs are very expensive to developCustom ICs have a long delay to fabricate (time to market)
Need to worry about two kinds of costsDevelopment cost sometimes called non-recurring engineering (NRE)Manufacturing Cost
Why FPGAs? (Contd.)Custom IC approach suitable only for products
With very high volume (which decrease the NRE)
Not time to market sensitive
FPGAs introduced as an alternative to custom ICs
Improved density relative to discrete SSI/MSI components
With the aid of computer aided design (CAD) tools circuits could be implemented in a short amount of time relative to ASICs
No physical layout process, no mask making, no IC manufacturing
Lowers NRE
Shortens TTM
Why FPGAs? (Contd.)FPGAs
Compete with custom ICs
Compete with microprocessors in dedicated and embedded applications
performance NREsUnitcost TTM
ASIC ASIC ASICFPGA
MICROFPGA
MICROFPGA
MICRO
FPGA
ASICMICRO
Summary
Programmable Elements Overview
Computer Aided Design
Programmable Elements Overview (Contd.)
AntifuseProgrammable Elements Overview
(Contd.)SRAM
Read or WriteData
Configuration Memory Cell
Routing Connections
LowMedium
Yes(in-system) No
Yes No
Field Programmable Gate Arrays
Configurable Logic Block (CLB)Look-up table (LUT)
Register
Or any kind of logicAdder, Multiplier, Memory, Microprocessor
Input/Output Block (IOB)Special logic blocks at periphery of device for external connections
Programmable interconnectWires to connect inputs andoutputs to logic blocks
Field Programmable Gate Arrays (Contd.)
Other FPGA building blocksClock distribution
Embedded memory blocks
Special purpose blocksDSP blocks
Hardware multipliers, adders and registers
Embedded microprocessors/microcontrollers
High-speed serial transceivers
LUT based Logic Block:
A transmission gate-based LUT 2-Input MUX as A Programmable Logic
FA 0
B
S
1
ConfigurationA B S F=0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X + Y1 0 X1 0 Y1 1 1 1
XYXY
XY
MUX –based Logic Block:
a&b
c
Programmable InterconnectFast local interconnectHorizontal and vertical lines of various lengthsSwitch matrixes
Switch Matrix StructureSwitch matrix programming illustration
Switch Matrix Interconnect
Switch Matrix Structure (Contd.)6 pass transistors per “switch matrix interconnect point”
Pass transistors act as programmable switchesPass transistor gates are driven by configuration memory cells
FPGA Variations
Families of FPGA’s differ inPhysical means of implementing user programmability
Arrangement of interconnection wires
Basic functionality of the logic blocks
Most significant difference is in the method for providing flexible blocks and connections
Sea-Of-Module Architecture Sea-Of-Module Architecture Routing
Computer Aided Design
Channel Architecture Actel FPGA8 input, single output combinational logic blocks
Rows of programmable logic building blocks
rows of interconnect
Anti-fuse Technology
I/O Buffers, Programming and Test Logic
Logic Module Wiring Tracks
I/O Buffers, Programming and Test Logic
I/O B
uffe
rs, P
rogr
amm
ing
and
Test
Log
ic I/O B
uffers, Programm
ing and Test Logic
Actel Logic moduleBasic module is a modified 4:1 multiplexer
2:1 MUXD0
D1
SOA
2:1 MUXD2
D3
SOB
2:1 MUX
S0
Y
S1
Actel Logic module (Contd.)Implementation of S-R Latch using actel FPGA
2:1 MUX"0"
R
2:1 MUX"1"
S
2:1 MUX Q
"0"
Actel Interconnect
Logic Module
Horizontal Track
Vertical Track
Anti-fuse
XC4000 FPGA Architecture
SRAM cells throughout the FPGA determine the functionality of the device
XC4000E CLB2 Four input function Generators(LUTS)1 Three-input function2 RegistersPossible functions:Any fct of 5 varTwo fcts of 4 var+one Fct of 3 var
Example
Implement the following functions on a singleCLB of the XC4000 FPGA:X = A’B’ (C + D)Y = AK + BK + C’D’K + AEJL
Use look up table F to implement XUse look up table G for AEJLUse F, G and H for Y:
Y = K(A+B + C’D’) + AEJL= KX’ + AEJL= KF’+G
Example
Virtex 5
Virtex 5
High end of the Xilinx FPGA's FamilyHigh performance (550MHz) Low-power conception65nm CMOS process
CLBs
2 slices per CLBSlices
4 Register4 LUTCarry logic
6-input LUT : More efficients logic (ie. 4->1 Mux)
CLBs Slices
Slices (contd) SLICEL
Many configuration possible
64x1 Single port RAM32x1 Dual port RAM
32 stages Shift Register64x1 ROM
LUT
64x1 Single port RAM32x1 Dual port RAM
32 stages Shift Register64x1 ROM
LUT
Slices (contd)
SLICEMOnly Rom or LUT
6 Input LUT
Optimize common logic implementation
DSP Slices
High-performances DSP-SlicesUp to 250 GMACs!Single precision float optimized40 Operating mode adaptable dynamically
RAM2 Types of RAM usable
Distributed RAMUsed the LUTs as RAM
Closed to the logicLess RAMUse CLBs
Global RAMMore RAM555MHzFar from the logic
Routing problemSpeed problem
Power Consumption In FPGAs
Power Consumption in FPGAs
1-Static power (5% to 20% )Leakage current: reverse biased diode leakage current Sub-threshold conduction of transistors
2-Dynamic power (80% to 95% )PD =1/2*C*Vdd^2*α* fclk
It is consumed at the time of outputswitching of a CMOS circuit
Dynamic power consumption inFPGA design
Clock frequencySupply voltageSwitching activityResource utilization
Power dissipation distribution in Xilinx Virtex-II FPGA
Low Power Approaches in FPGAs
Ways to Reduce Dynamic PowerFrequency Reduction Voltage Scaling Capacitance Reduction
Input capacitance of the fan-out gates, Capacitance associated with Programmable interconnectsParasitic capacitance of the gate.
Switching Activity Reduction Switched Capacitance Reduction Resource Utilization Reduction
Using Built-in Macro Functions for Low Power
Idea: Alternative techniques which use less routing resources than the traditional techniques
1- Low power implementation of register files
2- Low power implementation of shift registers
Xilinx SRLUT input and output ports
3-Low power implementation of multiplier and accumulators
Virtex 5 – Low Power
65nm CMOS processPotentially more leakage current
Solved by Triple Oxide Process TechnologyGain in dynamic power
Many hard IP blockDSP slices
Virtex 5 – Triple Oxide
65nm process -> more static powerTens of millions static configurations transistors
Virtex 5 – Triple Oxide (contd)
3 oxide ThicknessThin oxide for high speed partlarge oxide for 3.3v I/O“midox” for static configuration part
Virtex 5 – hard IP block
Rocket IO : Low power serial IO hard IP bloc
SATA (Serial Ata) Gigabyte EthernetPCI ExpressConsume 100mW at 3.2 Gbps
Tri-mode Ethernet MAC (10/100/1000)
ReferencesThe Design Warriors Guide to FPGASLow Power FPGA Design Techniques for Embedded Systems(PHD Thesis by Anurag Tiwari )WWW.XILINX.COMArchitecture of FPGAs and CPLDs: A Tutorial by Stephen Brown and Jonathan Rose Department of Electrical and ComputerEngineering University of TorontoPeter.Nilsson: Slides of Advanced Digital IC Design
Arnaud Taffanel - Peyman Pouyan