How Chips Are Designed

8/22/2019 How Chips Are Designed

1/46

Introduction to ASIC Design

How chips are designed?

Muhammad Ali Raza Anjum


2/46

How Chips Are Designed

Old-Style Design Process

New-Style Design Process Verifying the Design Works

Using Outside IP Getting to Tape Out and Film

Current Problems and Future Trends


3/46


the first semiconductor chips were assembled, literally, byhand

New chips today are designed in a completely differentmanner from those of just 10 years ago it's almost certain that the job description will change again

in another 10 years.

The computers that chip-design engineers use are notfundamentally different from a normal PC, and even thespecialized software would not look too alien to a casualPC user.

That software is breathtakingly expensive, however, andsupports a multibillion-dollar industry all by itself. Calledelectronic design automation (EDA)

Chip-design engineers rely on their computers and their

EDA software "tools" the way a carpenter relies on acollection of specialized tools


4/46


There are a handful of large EDA vendors, notably: Synopsys (Mountain View, California),

Mentor Graphics (Portland, Oregon), and Cadence Design Systems (San Jose, California)

There are also numerous smaller "boutique" EDAvendors that supply special-purpose software tools to

chip designers in niche markets. Regardless of the tools a chip designer uses, the goal is

always the same: to create a working blueprint for a newchip and get it ready for manufacturing.

The film (which is really not film any more, as we shallsee) is used by chip makers in their factories to actuallymanufacture the chip


5/46


Before personal computers, EDA, and automated tools,engineers originally used rubylith, a red plastic film sold

by art-supply houses that is still used today by signmakers and graphic artists Early chip designers would cut strips of rubylith with X-

acto knives and tape them to large transparent sheets

hanging on their wall Each layer of silicon or aluminum in the final chip

required its own separate sheet, covered with a criss-crossing pattern of taped-on stripes

By laying two or more of these transparent sheets atopone another and lining them up carefully, you couldcheck to make sure that the rubylith from one touchedthe rubylith from another at exactly the right points.


6/46


Or, you'd make sure the tape strips didn't touch, creatingan unwanted electrical short in the actual chip

This was painstaking work, to be sure, but such are thetribulations of the pioneers.

The whole process was a bit like designing a tall buildingby drawing each floor on a separate sheet and stackingthe sheets to be sure the walls, wiring, stairs, andplumbing all match up precisely.

This task was called taping out, for reasons that are fairlyobvious

Once you'd taped out, you were nearly done. About the only thing left to do was to wait for the chip to

be made


7/46


One last step remained, however, before you could getexcited about waiting for silicon

You had to make film from your oversized rubylith layers This was a simple photographic reduction process. Each rubylith-covered layer was used as a mask, projecting

criss-crossed shadows onto a small film negative. It works just like a slide projector showing vacation

snapshots on a big screen, but instead of making theimages bigger, the reduction process makes them smaller.

Each separate rubylith layer is projected onto a differentfilm negative that is exactly the size of the chip itself, lessthan one inch on a side.

Now you have a film set that you can send for fabrication.


8/46

New-Style Design Process

Today the process is radically different Modern chip-design tools have done away with the error-

prone manual work of taping up individual layers, but theyonly shift the workload Modern multimillion-transistor chips supply more than

enough new challenges to make up the difference

Modern chips are far too complex to design manually No single engineer can personally understand everything

that goes on inside a new chip Even teams of engineers have no single member who truly

understands all the details and nuances of the design. One person might manage the project and command the

overall architecture of the chip, but individual engineers willbe responsible for portions of the detailed design


9/46


They must work together as a team, and they must rely onand trust each other as well as their tools

Those tools are all computer programs No single EDA tool can take a chip design from start to

finish The assortment is important, and using a mixture of EDA

tools is part of an engineer's craft Schematic diagrams are the time-honored way of

representing electrical circuits Schematics, or wiring diagrams, are like subway maps They draw, more or less realistically, the actual

arrangement of wires and components (lines and stations). Schematics are accurate maps of circuit connections


10/46


schematics are drawn on a computer screen usingschematic-capture software.

The schematic-capture software takes care of the simplerannotation chores like labeling each function and makingsure no wires are left dangling in midair

Schematic-capture software is a bit like word-processing

software in that it won't provide inspiration or talent orcreate designs from nothing, but it will catch commonmistakes and keep your workspace free from embarrassingerasure marks.

number of companies supply schematic-capture software,but most vendors are small firms and their ranks aredwindling

Modern chips are too complex to be designed this way, not

because the schematic-capture programs can't handle it,but because the engineers can't


11/46


Designing a multimillion-transistor chip using schematic-capture software would be like painting a bridge with a

tiny artist's brush and palette There's just far too much area to cover and not enough

time.

To alleviate some of the tedium of designing a chip bit bybit, engineers have turned to a new method, calledhardware synthesis

Chips are not magically synthesized from thin air

Instead, engineers feed their computers instructionsabout the chip's organization and the computergenerates the detailed circuit designs


12/46


The engineer still has to design the chip, just not at sucha detailed level

It's like the difference between describing a brick wall,brick by brick and inch by inch

Or telling an assistant, "Build me a brick wall that's threefeet high by 10 feet long." If you have an assistant youtrust who is skilled in bricklaying, you should get thesame result either way

Theoretically, that's true of hardware synthesis as well,but the reality is somewhat different

Although today's chip designers have overwhelminglyadopted hardware synthesis for their work, they stillgrumble about the trade-offs


13/46


For example, synthesized designs tend to run about 20to 30 percent slower than "handcrafted" chip designs

Instead of running at 500 MHz, a synthesized chip mightrun at only 400 MHz

Another drawback of hardware synthesis is that the

resulting chips are often about 30 to 50 percent larger interms of silicon real estate

More silicon means more cost

Bigger chips mean lower manufacturing yields Once again, there are certain chip makers that don't use

hardware synthesis because they're shaving everypenny of cost possible.


14/46


Third, chips made from synthesized designs tend to usemore electricity than do manually designed chips

That's a side effect of the larger silicon size previouslymentioned

More silicon means more power drained, and thedifference can be 20 percent or more.

For extremely low-power chips, such as the ones used incellular telephones, handcrafted chips are still popular

Despite all these serious drawbacks, most new chips are

created from synthesized designs simply becausethere's no other way It takes a long time to finish a cathedral if you're laying

every brick by hand


15/46


Companies will often use both design styles, synthesis andhandcrafting.

The first generation of a new chip will usually be designedwith hardware-synthesis languages (described later) to getthe chip out the door and onto the market as quickly aspossible

After the chip is released (assuming that it sells well), thecompany might order its engineers to revise or redesign thechip, this time using more labor-intensive methods to shrinkthe silicon size, reduce power consumption, and cut

manufacturing costs. This "second spin" of the chip will often appear six to ninemonths after the first version.

When microprocessor makers announce faster, upgraded

versions of an existing chip, this is often how the new chipwas created


16/46


Schematics are fine, up to a point, but they're too detail-oriented for large-scale designs, which modern chips have

become. Instead, engineering teams need something that's morehigh-level and more abstract; something that allows them tothink big

Enter hardware-description languages (HDLs), the nextstep up the evolutionary ladder from schematic-captureprograms.

HDLs also enable hardware synthesis

Using an HDL, engineering teams can design the behaviorof a circuit without exactly designing the circuit itself indetail

The HDL tool will translate the engineers' wishes into a

circuit design


17/46


Instead of drawing figures on a screen (schematic-capture),using an HDL is more like writing

If schematics are blueprints, HDLs are recipes For a large chip, this procedural description can be

hundreds of thousands of lines long, as long as a novel The two most common HDLs are called VHDL and Verilog

Both of these languages were developed in the UnitedStates

Interestingly, there is a definite geographic divisionbetween VHDL users and Verilog users.

Verilog aficionados seem to be clustered around thewestern United States and Canada, whereas VHDL holdssway in Europe and New England


18/46


Verilog is a few years older than VHDL. First developed in1983, Verilog was for some time a proprietary HDL

belonging to Cadence Design Systems VHDL, on the other hand, was created as an openlanguage and became an Institute for Electrical andElectronics Engineering (IEEE) standard in 1987

Sensing that VHDL's standard status would jeopardize itsinvestment in Verilog, Cadence put its HDL in the publicdomain in 1990 and applied for IEEE approval, which itgained in 1995

Because of their age and rapid increases in chipcomplexity, both languages have begun to crack a little bitunder the strain of modern chip design

Some engineers argue that designing a 10-million-

transistor chip using VHDL or Verilog is little better than therubylith methods from the 1970s


19/46


HDLs come and go, but a few that seem to havereached critical mass in the EDA market are Superlog,

Handel-C, and SystemC. Superlog, as the name implies, is a pumped-up version

of Verilog. It's a superset of the language that adds somehigher lever, more abstract features to the language

Superlog allows designers experienced in Verilog tohandle larger chip designs without going crazy withdetails

Handel-C and SystemC are both examples of a moreradical approach to HDLs

they use the C programming language to definehardware as well as software.


20/46


They take the heretical stance that, because popularHDLs like Verilog and VHDL are already programming

languages, why not use an actual programminglanguage in their place? This has the advantage that millions of programmers

already know C programming, and thousands more

students learn it every year. Programming languages such as C, BASIC, Java, and

the rest were never designed to createor evenadequately describehardware

Even the strongest backers of the C-as-hardware-language movement realize that the original Cprogramming language isn't well suited to the job


21/46


For example, the ability of electronic circuits to

perform multiple functions simultaneously, whichprogramming languages like C can't describe

They've all added various extensions to the

language to help express parallelism Many have also added "libraries" of common

hardware functions so that engineers don't haveto create them from scratch


22/46

Verifying the Design Works

Assuming the chip eventually makes it through place androute in one piece, it would normally be ready to send to

the foundry for manufacturing However, because the cost of tooling up a foundry to makea new chip is so expensive (in the neighborhood of$500,000)

it's vitally important that everyone involved in its designconvince themselves that there are no remaining bugs There are few things more expensiveor more damaging

to one's careerthan a brand new chip that doesn't work

The enormous costs of chip manufacturing have spawneda sub industry of companies providing tools and tests toverify complex chips without actually building them


23/46


The business opportunity for these companies lies incharging only slightly less than the cost of a bad chip

All these verification tools work by simulating the chipbefore it's built.

As with many things, the quality of the simulation

depends on how much you're willing to spend. There are roughly three levels of simulation and some

engineering teams make use of all three

Others make do with just the simplest verification, notbecause they want to but because they can't affordanything more complete.


24/46


The first and easiest type of simulation is called Cmodeling

As you might guess, this consists of writing a computerprogram in C that attempts to duplicate the features andfunctions of the chip's hardware design.

The holes in this strategy are fairly obvious If the program isn't really an accurate reflection of the chip

design, then it won't accurately reflect any problems, either.

This strategy also requires essentially two parallel projects: the

actual chip design, and the separate task of writing a programthat's as close to the chip as the programmer can make it.

The major upside of this approach, and the reason somany engineering teams use it, is its speed


25/46


It's quick to compile a C program (a few minutes at most)and it's quick to run one.

Within an hour or so, the engineers could have a goodidea of whatever shortcomings their chip might have.

Many chip-design teams create a new C model every

day and run it overnight; the morning's results determinethe hardware team's task for the rest of the day.

There aren't really any commercial C verification tools

they're simply standard computer programs that happento model the behavior of a chip under development.

They're written, compiled, and run on entirely normalPCs or workstations.


26/46


A significant step up from software simulation of the chipis hardware simulation

Despite the name, hardware simulation doesn't usuallyrequire any special hardware. Instead, a computer picks through the original hardware

description of the chip (usually written in VHDL or

Verilog) and attempts to simulate its behavior This process is painfully slow but quite accurate.

Because it uses the very HDL description that will beused to create the chip, there's no quibbling over thefidelity of the mode

Unfortunately, hardware simulation is so slow that largechips are often simulated in chunks, instead of all atonce, and this introduces errors


27/46


If there are problems when Part A of the chipcommunicates with Part B, and these two chunks aresimulated separately, the hardware simulator won't findthem

The alternatives are to let the simulation run for many

days or to buy a faster computer.

Regrettably, the larger the chip, the greater the need foraccurate simulation, but the longer that simulation will

take


28/46


The non plus ultra of chip verification is an emulator box This is a relatively large box packed full of reprogrammable

logic chips, row after row To emulate a new chip under development, you first

download the complete netlist of the chip into the emulatorbox

The box then acts like a (much) larger and (much) slowerversion of the chip

The advantages of this system are many. First, the emulator is real hardware, not a simulation, so it

behaves more or less like the new chip really will. The major exception is speed: Emulator boxes run at less

than 1 percent of the speed of a real chip, but that's stillmuch faster than a hardware simulator.


29/46


Third, emulator boxes generally emulate an entire chip,not just pieces of it

Naturally, emulating larger chips requires a larger box,and commensurately more expense, but at least it'spossible

Because the emulator box is real hardware, you can

connect it to other devices in the "real" world outside thebox.

For example, you can connect an emulated video chip toa real video camera to see how it works

Finally, the emulator can be used and reused at differentstages in the chip's development, or even for differentchips

Emulator boxes are so expensive that they generally aretreated as company resources


30/46

Using Outside IP

One of the quickest ways to design a new chip is to notdesign it at all.

Most big new chips include a fair amount of reused,borrowed, licensed, or recycled circuitry; not physicallyrecycled silicon, of course, but recycled design ideas

Like a musician composing new variations on an old

theme it's often better to borrow and adapt than to create from

scratch.

In engineering circles this is called design reuse orintellectual property (IP) reuse IP is a high-sounding name for intangible assets that can

be sold, borrowed, or traded


31/46

Using Outside IP

Lawyers use IP to refer to trademarks, logos, musicalcompositions, software, or nearly anything else that's

valuable but insubstantial. Engineers use IP to refer to circuit designs. Since the mid-1990s there has been a growing market for

third-party IP: circuit designs created by an independent

engineering company solely for the purpose of selling toother chip designers As chip designs have grown ever more complex, the

demand for this IP has grown and encouraged the supply.

There are a few profitable "chip" companies that not onlydon't have their own factories, they don't even have theirown chips. They license partial chip designs to others andcollect a royalty.


32/46

Using Outside IP

To makers of large chips, it's an attractive alternative tobuy parts of the design from outside IP suppliers.

There are dozens of large IP vendors and hundreds ofsmaller ones

Some IP houses specialize in large (and valuable) types

of circuit designs, such as entire 32-bit microprocessors,for which customers gladly pay more than $1 million inlicensing fees, plus years of royalties down the road

There are also sources of free IP on the Internet, just asthere are for free software

Although outside IP is a great boon to productive chipdesign, it isn't all smooth sailing


33/46

Using Outside IP

First, customers often balk at the prices

Outside IP is designed to appeal to the largest possible

audience, so it's naturally somewhat generic Potential customers might be looking for something more

specific that outside IP doesn't offer.

It's also possible that the IP won't be delivered in a formthat the customer can use

If the bulk of the chip is being designed using Verilog,

but the IP is delivered in VHDL, it's probably not usable. For IP firms that deliver their products as HDL, there'sabout a 50 percent chance of getting it wrong.


34/46

Using Outside IP

If the chip design fails its final verification, does the fault liewith the licensed IP or with the original work surrounding it

Neither side will be eager to admit liability Usually these problems have their root in ambiguous or

insufficient specifications or a misunderstanding between

engineers on either side. Among IP vendors and customers, one of the firstquestions asked is, "Does this IP come in hard or softform?

What the customer is asking is whether the circuit designwill be delivered in a high-level HDL such as Verilog orVHDL, or as an already-synthesized "hard" design readyfor manufacturing


35/46

Using Outside IP

IP that's delivered in "soft" form (i.e., as an HDLdescription) is generally easier for the customer (the

chip-design team) to work with But it will have all the same drawbacks that allsynthesized hardware suffers: larger size, slower speed,and higher cost when it's manufactured.

On the plus side, the HDL is probably easier to integrateinto the rest of the chip design, especially if the rest ofthe chip is also being designed with the same HDL

IP vendors sometimes don't like to provide their wares inHDL form for two reasons.

First, the usual drawbacks of synthesized hardwaremight make their product look bad


36/46

Using Outside IP

The IP vendor can't guarantee, for example, that itscircuit will run at 500 MHz because it can't control the

synthesis process. Consequently, the vendor winds up being very

conservative and cagey about promising hard

performance numbers. Unlike chip companies, IP companies rarely advertiseMHz numbers (or power usage) in their literature

Another aspect of soft IP that gives the vendorsheadaches is the possibility of piracy and IP theft

Many IP vendors simply do not offer synthesizable IPcores for exactly that reason.


37/46

Using Outside IP

The alternative to soft IP is, of course, hard IP.

A "hard" IP product (often called a core) isn't really hard.

It's just the same as a soft core after it's beensynthesized, placed, and routed.

It's film, or the electronic equivalent of film.

A hard core is nearly ready for manufacturing All it needs is to be dropped into the rest of the chip

design at the last minute.

There are good and bad aspects to using hardIP.They're generally faster, smaller, and use less powerthan synthesized soft cores because they've beenextensively hand-tuned


38/46

Using Outside IP

On the other hand, hard IP cores are much more difficultto incorporate into the rest of the chip, especially if that

chip is being synthesized. Essentially, the chip's designers have to leave arectangular hole in their design that exactly fits the hardIP core.

Then, during the late stages of preparation beforemanufacturing, the hard IP core is inserted.

Hard IP cores prevent the customer's engineers fromaltering or modifying the core in any way, which is

partially the point. IP vendors like delivering hard IP cores because they

know their customers won't have access to the "recipe"for the IP.


39/46

Using Outside IP

Early IP vendors in the mid-1990s almost alwaysdelivered hard IP cores.

The trend has moved more toward soft IP in recentyears, however. As more and more engineering teams use hardware-

synthesis and HDLs for their own chips, they demand

the same from their outside IP vendors. IP vendors might cringe because of the performance and

security issues that soft IP raises, but the alternative is tolose business.

Various industry groups have looked at ways to protectsoft IP by "watermarking" the circuit design or throughpublic-key encryption of the data files, but so far theseefforts have produced little


40/46

Using Outside IP

Another form of IP, although a much less glamorous one(if that's possible), is the physical library.

These fit in toward the end of a chip's design, as it'sbeing synthesized, placed, and routed.

As such, these libraries change from one semiconductor

manufacturer to another, and often from one building orsite to another within the same company.

In the later stages of a chip's design, the EDA tools needto know exactly how thick, how wide, and how high eachsilicon transistor will be, and these characteristics varyslightly from maker to maker


41/46

Getting to Tape Out and Film

After the design, synthesis, testing, simulation, andverification are all done, the final steps are almost

anticlimactic Once the engineering team is satisfied that the chip

design will work, it's simply a matter of pressing a button

to tape out the new chip Far from the old days when each layer of silicon andmetal was literally taped out by hand, tape out nowconsists of a few moments for a computer to produce a

file and store it on a CD-ROM Often engineers will print out these files and hang up the

colorful poster-sized prints of the chip's design


42/46

Getting to Tape Out and Film

Film is no longer really film anymore.

The file produced by the EDA software is called a GDS-IIdatabase, and it takes the place of actual film.

Transporting a film box to the foundry is passed

Uploading the GDS-II database is as simple as sendingan e-mail.


43/46

Current Problems and Future

Trends Moore's Law provides us with a rich 58 percent

compound annual interest rate on our transistor budgets

That's the same as doubling every 18 months Given that it frequently takes more than 18 months to

design a modern chip

Chip designers are presented with a daunting challenge Take the biggest chip the world has ever seen and

design something that's twice that big. Do it using

today's tools, skills, and personnel, knowing that nobodyhas ever done it before.

When you're finished, rest assured your boss will askyou to do it again


44/46


Trends The modern EDA process is running out of steam Humans are not becoming noticeably more productive, but

the tasks they are given (at least, those in thesemiconductor engineering professions) get more difficultat a geometric rate

Faster computers will help run the current EDA tools faster.

Faster synthesis, simulation, modeling, and verification willall speed up chip design by a little bit.

However, even if computers were to get 58 percent fasterevery year (they don't), that would only keep pace with the

increasing complexity of the chips they're asked to design. At best, we'd be marking time. In reality, chip designers are

falling behind

C


45/46


Trends A change to testing and verification would provide a

small boost

Testing now consumes more than half of some chips'project schedules. To cut this down to size, some companies have strict

rules about how circuitry must be designed, in such a

way that testing is simplified. Better still, these firms encourage their engineers to

reuse as much as possible from previous designs, theassumption being that reused circuitry has already been

validated. Unfortunately, reused circuitry has only been validated in

a different chip; in new surroundings the same circuitmight behave differently

C P bl d F


46/46


Trends IP is another angle on the problem. Instead of helping

designers design faster, this helps them design less

Reuse, renew, and recycle is the battle cry of manyengineering managers Engineers tend to design larger and more complex chips

than they otherwise might have if they know they don't

have to design every single piece of it themselves Although that makes the resulting chips more powerful

and feature-packed, it doesn't shorten the design cycleat all

With no clear winner and no clear direction to follow, thefuture of chip design will be determined largely by herdinstinct, Engineers will always choose what they feelmost comfortable with

Documents

How Chips Are Designed