Hot ThreadsInvestigating Multi-Core and

Cell Processor Security

Dr. Jim Alves-Foss

Jessica SmithRachel Bonas

Andrew GroenewaldXiaohui He

Mufaddal TajMike Beery

Jessica Smith, University Of Idaho 2

Cell Processor Creation

Power PC (Power Processing

Element) +8 Synergistic Processing

Elements

Jessica Smith, University Of Idaho 3

Cell BE Architecture

Jessica Smith, University Of Idaho 4

HistoryAir Force Research Lab – “We want

to know more about multicore before we use it – send it to Raytheon!”

Raytheon – “We don’t know enough, either – let’s send it to UI!”

Dr. Alves-F – “I don’t have enough time – let’s get some kids to research it!”

Jessica Smith, University Of Idaho 5

Three General Areas

Covert Channels “Once by land, Twice by sea”

Publicized Security Features• Secure Processing Vault• Hardware Encryption Key• Secure Boot

Direct Channels Hello, how are you?

Jessica Smith, University Of Idaho 6

Security Concerns

EIB◦ Can anybody read it?◦ Can one SPE control the flow amounts?

BEI◦ Can a linked-in unit access the EIB?◦ How much data can we route out?

Jessica Smith, University Of Idaho 7

Security ConcernsRegisters

◦Who can access (read/write) them?◦SPE registers◦BEI registers

Memory and Memory Flow Controllers◦Mailbox program◦Privileged memory

Jessica Smith, University Of Idaho 8

A Workable SetWhat we are worrying about

◦Rouge SPEs◦Rouge external components◦Secure Processing Vault

What we aren’t worrying about◦Duplication with Raytheon – PPE ◦Anything slower than a human◦Hardware Encryption Key, Secure

Boot

Jessica Smith, University Of Idaho 9

Next Step – Designing Tests

Feasibility: Time Requirements Risk Analysis

Includes:•What is being tested•What equipment is needed•What programs will be written•Methodology & procedure•Analysis methods•Results

Jessica Smith, University Of Idaho 10

Designing A Test HarnessPurpose – To enable a user to easily

run different tests with a wide range of variables.

Features◦Updateability◦Configurable Tests◦Reporting◦RAM control option

Jessica Smith, University Of Idaho 11

Creating the Tests and Harness

The tests will be written in C and assembler, designed to run on the PPE and SPEs.

The harness will be written in C or C++, designed to run on the PPE.

Jessica Smith, University Of Idaho 12

Timeline

15 November – Initial Report Due

15 December - Tests Written

15 February – Basic Tests Coded, Harness

Designed

15 March – Harness Coded

15 April – Basic Tests Run, Documentation

Finished

25 April – Engineering Expo

Jessica Smith, University Of Idaho 13

Questions, Comments or Suggestions?

Hot Threads Site:

http://seniordesign.engr.uidaho.edu/2008_2009/hot_threads/

IBM Cell Processor Site: http://www.research.ibm.com/cell/