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Harold Convey: March 2006 1University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

University of Bolton

Managing and Specifying

Microcontroller Projects

Harold Convey

Technical Manager

Fuse Programme

Technology Development UnitTDU!

Faculty of Technology"

Bolton #nstitute.

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What is a Microcontroller

• It is a microprocessor integrated into a

single IC package with a range of useful

functions

• Has the ability to execute a stored set of

instructions to carry out user defined task

• General purpose hardware constantly

reconfigured by software

• Can perform many different tasks

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Harold Convey: March 2006 #University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


Oeriew of !"I#$ chip family

• %hese are all user programmable

• "ifferent leels of complexity

•"ifferent leels of engineering charges& 'ower for microcontrollers

• "ifferent costs for deelopment systems

& Cheaper for microcontrollers

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Harold Convey: March 2006 $University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


%he !"I#$ Chip (amily)*IC

'ogic based

Customised by

end user

+e,programmable

-'"s

One time

programmable

-'"s

Customised by

silicon endor

Gate array

Cell based

full custom

-rocessor based

/microcontrollers0

+e,programmable

microcontrollers

One time

programmable

microcontrollers

Masked

microcontrollers

Customised by

end user

Customised by

silicon endor

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What is a Microcontroller

• ) microprocessor aimed at computationally

intense task

& 1eeds large fast memory

• Microcontroller self contained

& -rogram memory2 +)M and Input3Output

•Can hae expansion !hooks$& 4xternal memory2 +)M and Input3Output

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What is a 5-6

CPU Memory I/O

Bus

microprocessor $ey characteristic % processing speed

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What is a 5C6

CPU Memory I/O

Bus

Microcontroller un%e&panded!

i i f

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What is a 5C6

Microcontroller e&panded mode!

CPU Memory I/O

Bus

U i it f B lt

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What is a 5C6

Microcontroller e&panded mode!

CPU Memory I/O

Bus

U i it f B lt

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7ey considerations for 5C

• (lexibility

& same hardware can carry out different tasks

•-rocessing power & complex algorithms and numeric calculations

• *oftware complexity

& can be complex , harder to understand• 4stimating deelopment time

& can be difficult to do with any accuracy

U i it f B lt

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Choosing a Microcontroller

-ro8ect , possible application

• *oft specification

• Complex user interface

•Complex heuristic algorithms

• Most re9uirements met in unexpanded mode

Uni ersit of Bolton

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-ro8ect , not adised• High speed and numerically intensie

& "*-

• 'arge memory re9uirements

& 5-

• Complex but well defined function

& C-'" or (-G)

• 'arge memory or additional I3O which usesexpanded mode

& 5- or embedded controller


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Harold Convey: March 2006 1#University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


*oftware 4ngineering

• Microcontroller pro8ects contain software

• *oftware can carry complex functions

• 1eed to manage this complexity

• *oftware flexible , can add extra features

• 1eed control to preent bugs

• *oftware system deliered : year late• Only :; finish on time

•

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Harold Convey: March 2006 1$University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


*oftware 'ife Cycle and

+eliabilityCost or time e&pended per phase

+e9uirements

"esignCoding

%esting

Maintenance />?,@?;0

+e9uirements +eiew/C+I%IC)' )C%IAI%#0/=,:?;0

/:?;0

/:?;0/

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Harold Convey: March 2006 1%University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


*oftware 4ngineering• 1eeds good documentation

• Clear specifications

• Clear configuration control

• *oftware easy to change , results can be

difficult to predict

• May fail some time in future

• 1ot proen to improe good programmer

output , but does with aerage programmer


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"esign flow in a typical system

)e*+ire!entecification)e*+ire!entecification

yste! -rchitect+re.Hard/are oft/are ss+es

yste! -rchitect+re.Hard/are oft/are ss+es

3+nctionalecification.Hard/are oft/are ss+es

3+nctionalecification.Hard/are oft/are ss+es

Technicalecification.soft/are

Technicalecification.soft/are

Hard/are+45syste!ecification

Hard/are+45syste!ecification

Codeoft/areCodeoft/are

oft/are -rchitect+reoft/are -rchitect+re

High5levelDesign.Hard/are oft/are

High5levelDesign.Hard/are oft/are

Hard/are+45syste!Design

Hard/are+45syste!Design

Detailed

Design.oft/are

Detailed

Design.oft/are

Mod+leecification.oft/are

Mod+leecification.oft/are

ecificationriting -ctivity

ecificationriting -ctivity

Design!le!entation -ctivity

Design!le!entation -ctivity

The stes sho/n are ill+strative"They sho/ that in racticesecification and design flo/ inarallel, /ith lo/er levelsecification arising fro! so!einter!ediate designi!le!entations has ta7enlace" The flo/ follo/s thetyical 8aterfall9 !odel"

The stes sho/n are ill+strative"They sho/ that in racticesecification and design flo/ inarallel, /ith lo/er levelsecification arising fro! so!einter!ediate designi!le!entations has ta7enlace" The flo/ follo/s thetyical 8aterfall9 !odel"


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Harold Convey: March 2006 1&University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


4stimating time scales

• )lgorithmic cost model

• 4xpert 8udgment

•4stimation by analogy

• -arkinson$s law

• -ricing to win

• %op down estimation

• Eottom up estimation


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Harold Convey: March 2006 1'University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


4stimating time scales

• 1o method is superior to any others

• choose one techni9ue and iterate until

arious cost conerge

• *oftware costing is experience


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Harold Convey: March 2006 1(University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"


"ocumentation and

*pecification

• 4ach phase of life cycle has documentation

• 4ach phase builds on preious

documentation

• Gies consistency , alidation process

• %hree strands to the documentation

& (or the deelopment& (or testing of the system under deelopment

& (or planning and monitoring


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"eeloping a re9uirements model

discoer

the

problem

weigh

re9uirements

s. constraintsre9uirements

more,explicitspecifications

describe theconceptual

modeldocumentedmodel

customerreisions

CustomerFsneed

show model tocustomer

"ocumentedand agreed

+e9uirements

Model


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+e9uirements *pecification

• :. Introduction•

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y

+e9uirements *pecification

• >. Goals

& , Operational

& , "esign

• =. *ummary


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Harold Convey: March 2006 2#University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

y

(unctional *pecification

• :. Introduction

•

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Harold Convey: March 2006 2$University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

y

(unctional *pecification

• B. (unctional "escription

& , (unctional partitioning

& , (unctional description

& , Control description

• >. Eehaioral "escription

& , *ystem states

& , 4ents and actions /inc. timing0

• =. *ummary


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Harold Convey: March 2006 2%University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

y

%echnical *pecification• :. Introduction

•

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y

%echnical *pecification

• >. "esign *pecification

& , (unctional descriptions :

& , (unctional descriptions <

& , ....

& , (unctional descriptions n

• =. *ummary


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Harold Convey: March 2006 2&University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

y

Module "escriptions

• ) module description describes

& Interface specification

& (unctional summary

& Operational description

& "ata dictionary description

& *tructure chart

& -seudocode description


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Harold Convey: March 2006 2'University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

Module "escription• %he actual source code listing must include

& )uthor2 date2 ersion release

& Interface description

& (unctional summary

& 'ist of data areas accessed& 'ist of procedures defined

& 'ist of procedures accessed

& 'ibraries inoked

& Operational description

& )mendments history


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Harold Convey: March 2006 2(University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

%est *pecification -lanning

• %he build2 integration2 certification and

acceptance test specifications must include

& %est strategy and plan lists

& %est architecture

& %esting and reiew timetable


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Harold Convey: March 2006 #0

University of Botlon, Technology Transfer Node, Technology Develo!ent Unit"

%est *pecification -lanning• %he test plans as summarised in the test

specifications will include

& %est system configuration

& %est list summary

& %ests , (unction of the test

, Input definitions

, 4xpected outputs

, +ecord of actual output

, *ign,off and data

, )mendments history


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+eal %ime *ystems

• Microcontrollers well suited to real time

applications

• Characteristics

& -roblem deried from engineering or science

& *ystem contains sensors2 e.g.. thermocouples

& +e9uire concurrent processing

& 'oop timings in order of milli seconds

& -recision timing


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+eal %ime *ystems

• +e9uire real time operating systems

• %hese proided for -C based platforms

• 1ot usually aailable for microcontrollers

• 1eed to deelop them for each

microcontroller application


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Harold Convey: March 2006 ##


*oftware "esign Methodologies

• Central to life software cycle

• Method of transforming the user

re9uirements into detailed design

• *hould identify series of steps

& -rocess iew , processing components and

interactions

& "ata iew , structures and inter,relationships

& 4ent iew , time critical se9uences


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Harold Convey: March 2006 #$


*oftware "esign Methodologies

• %ypes design methodologies suitable for

real time systems

& *" * /ackson systems design0

& M)*CO%

& ")+%*

& #ourdon

& HOO"


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Choosing the correct technology

• 1eed to specify hardware and software split

• 1eed to balance increased software

complexity against increased3decreased

component count

• Jse of on board system resources

•Jse of (-G)s for glue logic to reduce chipcount


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Infrared 'aser %ransmitter

MicrocontrollerPre-amplifer

ToneGenerator

High Voltage

Poer !upply

"aser #io$e

Pie%o !pea&er

Collimating

Pie%o 'ccelerometerIn(


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Harold Convey: March 2006 #&



• )pplications are aried• 1o single microcontroller will be applicable to

all applications

• 1eed to assess microcontroller strength andweakness

& -rogram memory siKe

& +)M siKe

& *peed

& I3O resources


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• 1eed to specify olumes

• %ype of deelopment system

•%ype of programming language& assembler

& High leel language2 e.g.. )1*I C

•-ortability of software between members offamily and different manufactures


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Harold Convey: March 2006 #(


)rchitectural Issues

• Wide range of 5C architectures exist• Most of the differences are to do with high speed

performance

• Jnless you need to push a 5- family of a gien

bus width to its speed limits2 architectures will

probably not be your prime reason for selection

• )rchitecture also affects how easily H''s can be

used and the efficiency of manipulating embeddeddata /storage location and table indexing0


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)ccumulator,based architecture

)'M

BU!

'CCUMU"'TO)

'"U

*

**


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)egister-+ase$

architecture)'M

BU!

'"U

T, T,MPO)')- ),GI!T,)

),GI!T,) .I",

/


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What is +I*C

• *ingle,cycle operation

• 'oad3store design

•Hardwired control

• +elatiely few instructions

• *imple instruction format

• More compile time effort• Often Harard type architecture

& *eparate program and data maps


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Characteristics of CI*C

• Multi,cycle instructions• Many instructions and addressing modes

• Micro,coded )'J control

• Instructions for extended arithmetic and otherspecial features

• Often implemented in a memory mapped I3O

structure

• Aon 1eumann structure

& same memory map for program and I3O


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Harold Convey: March 2006 $$


Eus Widths 3 bandwidths

• >3@3:3B< bit 5Cs exists with > bit on the

way

• %he width is usually taken from the data path

for operands

• @ bit 5Cs often hae instructions for dealing

with : bit words

• an @ bit 5C could hae : bit address

/e.g.. @HC::0


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Eus Widths 3 bandwidths

• a : bit 5C could hae an @ bit address bus

/e.g. @?D0

• %he bandwidth limiting bus depends on the

5C and the application


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-rogram "ata Memory *iKe

• ) key issue in un,expanded 5Cs

• (or @ bit 5Cs typically

& , few hundred bytes +)M

& , few 7bytes +OM

• *torage of parameter tables /especially non,

olatile0 needs inestigating

• )ailability of stacks /for H''s2 interrupts2

subroutines0 data storage for ariables is akey trade off0


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Memory %ype /1A2 O%-2

44-+OM2 etc.0

• *eeral different types of memory /for data

storage0 are aailable

& masked +OM& 4-+OM /JA erasable -+OM0

& O%- /One %ime -rogrammable0

& 44-+OM /4lectrically 4rasable , :??2??? cyclemax typical L timing problems0

• Combination of seeral types possible


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Memory %ype /1A2 O%-2

44-+OM2 etc.0

• Considerable price ariations between types

thus type used in production may differ

from that used in deelopment


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Interrupt handling

• 5Cs often hae to deal with many interrupts

with considerable ariations in priority

& precedence of safety critical function oer

general operator input could be one

example

• Often little opportunity to control the

scheduling of these eents as they arise from

real,world asynchronous single,shot eents


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Interrupt handling

• Gien limited amounts of +)M stacks

different 5Cs use different techni9ues to

deal with the situation

• *ome are much better at context switching

than others2 some offer lowest latency


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Interrupt Handling)eset

)eset /atchdog ti!er

+4ro+tines to 4e eec+ted onceeach ti!e aro+nd the loo

nitialisation

Mainrogra!

NT1

ervice ro+tine

)et+rn

NT1

ervice ro+tine

)et+rn

NT1

ervice ro+tine

)et+rn

nterr+t service ro+tines


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-arallel -orts• ) key feature as it allows digital interaction with outside

world• (re9uently heaily multiplexed with other resources. %hus

not all resources are aailable simultaneously

• *ome hae proision for strobe and hardware handshake

features• *ome allow interrupt on change of state

• Jsed with much ingenuity in most 5C designs to allow

analogue measurements at minimum additional component

count


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Harold Convey: March 2006 %#


%imers• Important for many applications

• Jsed in

& ,pulse counters

& ,pulse width measurements

& ,-WM outputs /motor2 temperature2 control2 e.t.c.0& ,with simple A to ( as analogue input

& ,defining changes between time controlled states

& ,many2 many other uses

• "ifferent 5Cs hae different ranges of features


)3" C

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)3" Conerters

•Many applications want analogue inputs

• Mixed analogue3digital increases 5C cost3complexity

• More than @ to :? bit )"C on chip is rare

• (or more demanding applications the )"C

performance needs careful examination

& , on chip sample and hold

& , control oer sample clock2 synchronisation between

channels

& , C-J load at higher sampling fre9uencies


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Harold Convey: March 2006 %%


(amily characteristics /packages2 pin outs2 ariants0

• %rade,off between siKe and aailable pins dictates

how many of the resources are aailable

• 4-+OM generally not possible in surface mount

packages• IC4 and 'ogic )nalyser pods often not aailable

for all package ariants

•*pecial ersions aailable for de,bug

,bond,out chips in IC4

,piggy back 4-+OM ersions


W t hd %i d

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Watchdog %imer and

Malfunction )oidance• Most 5Cs are used in un,superised or safety

critical applications or applications with simple

operator interface

•Often used in difficult 4MC enironment

• Must aoid the use of Ctrl,)lt,"el as a solution to

rouge operation

• Watchdog better than nothing but it is still possible

to get stuck in a regular but unterminating loop

which satisfies the watchdog.


E tt E k ' A lt

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Harold Convey: March 2006 %&


Eattery Eackup or 'ow Aoltage

operation

• Often used in applications where low

oltage operation is desirable2 e.g. battery

and portable operation

• 1eed to be able to maintain control through

power failure

• 1on,olatile storage of key parameters and

current operation state is often important


- d l

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Harold Convey: March 2006 %'


-ower down low power

modes

• (eatures to enable part of the 5C to be

powered down to sae power are often

desirable

• What happens to timers and )"Cs during

such modes

• (lexibility of power down modes dictates

how much use can be made in practice


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Harold Convey: March 2006 %(


Cold,start reset

• Well behaed cold,start circuitry is not

triial to design

• Many 5Cs include clock cycle counting

techni9ues to proide clean reset pulses

• *ometimes there is no external reset pin to

sae on pin count

• *ome users find external management of

reset an essential feature


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Harold Convey: March 2006 60


Communications• *erial communications with other controllers in a network may

be re9uired

• Aarious protocols can be considered

& ,+*@=

& ,C)1

& ,(ieldbus in its arious forms , H)+%

, -rofibus

, World (I-

& ,Eit Eus& , 4thernet


* ft t l il

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*oftware tools2 compilers2

assemblers2 e.t.c.

• %raditionally most @ bit designs hae used

assemblers

• Compatibility of @ bit 5Cs with the

re9uirements of H''s

• More compilers are becoming aailable

• Choice is tied in with debugging tool and

strategy


H d ( h

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Hardware (eatures that support

High 'eel 'anguages /H''0• Memory siKe

• 'inear memory space

• )de9uate stack or temporary ariable storage space

• *upport for frame pointers and other efficient stack ortemporary ariable access

• Indexed memory access for pointers2 e.t.c.

• *upport for extended arithmetic


+ f t i H''

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+easons for not using H''s

such as C

• 4fficiency of resulting op,code

• )ailability of debugging at C leel

•Controlling software timing loops

• Compiler bugs


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4fficiency of resulting op,code

• ) C program will usually re9uire more

program and data memory and execute

slower than an e9uialent program written

by a good assembler programmer

• %he architecture of many small /@ bit

typically0 microcontrollers is not well

matched to the re9uirements of H''s.


) ailabilit of deb gging at C

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)ailability of debugging at C

leel

• If you only hae access to an assembler

language debugger2 you will loose most of

the adantages you gained when writing the

program in C

• Compiler optimisation go beyond statement

boundaries making it hard to follow the

assembler language ersion of the code


Controlling software timing

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Controlling software timing

loops• Critical timing functions are often

implemented directly in software. H''s

destroy the : to : timing relationships

• *oftware timing loops makes the code hard tomodify

• *oftware timing can be aoided if the 5Cs has

a good hardware timer set• Control of hardware specific features can be

cumbersome in C


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Compiler bugs

• Most early C compilers were ery buggy or

only worked properly with certain family

members

• %his problem not confined to Brd party

cheap and cheerful software


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*ystem %est 4nironment

May not 4e ractical d+ring testMay not 4e ractical d+ring test

Testn+tyste!

oft/are Test Harness

Test;+t+tyste!

Test 3ilesTest )es+lts

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In,Circuit,4mulator /IC40

5- based

• Hardware3software deice that connects to

the target system through an absent 5C

• %he 5C is contained within the in,circuit,

emulator along with control hardware and

oerlay memory

• %hey are usually capable of breakpoints and

real time trace


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4mbedded %ools

• In,Circuit,4mulators /IC40 5C based

• In,Circuit,4mulator /IC402 background,debug,

mode /E"M0 or %)G,based

•'ogic )nalyser

• +OM emulator

• +OM monitor

•+OM,based emulator /hardware control0

• +OM,based emulator /software control0

• *imulator

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I i it l t /IC40

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In,circuit emulator /IC40 background debug, mode /E"M0 or %)G, based

• Easically an interlace between the debug hardware

integrated on the u- and a host running debugger.

#ou can perform the basic in,circuit emulation

functions. ) simple connector on the board is allyou need to connect the target

• )ailable mainly on : and B< bit microcontrollers

• Will work with u- in un,expanded mode


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'ogic )nalyser

• )n instrument that records logic leels at

selected time interals

• %he probes can be placed anywhere on the

target

• Many hae u- pods

• 1othing on target replaced

• Only monitors the logic leels

• "oes not proide control


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+OM emulator

• Hardware deice that replaces the +OM or

4-+OM on the target with +)M

• +)M made to look like +OM during

operation and +)M when down loading

code

• Only possible for microcontrollers in

expanded mode or if piggy back 4-+OMaailable


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+OM monitor

•*oftware that runs on the target that allowslimited debugging

• +OM monitors re9uire program runs out of

+)M so they can set breakpoints

• %ool simple and inexpensie

• Monitor usually re9uires serial interface to

communicate with host or terminal

• Only possible for microcontrollers in expanded

mode


+OM based emulator

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+OM based emulator /hardware control0

•Hardware 3 software deice that connects to thetarget ia an absent +OM

• %he u- remains in the target

• %his type of tool allows it to control the target and

iew 3 modify register data

• #ou can down load your code to the +)M that

replaces the target +OM

• Only possible for uC in expanded mode or piggy back 4-+OM ersions


+OM based emulator

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Harold Convey: March 2006 &&


+OM , based emulator /software control0

• Hardware 3 software deice that connects to the target ia

an absent +OM

• %he u- remains on the target

• *ome include hardware that allows debug information to

go from u- to the debugger running on the host2 so you can

iew and modify register data

• "own load your code to the +)M that replaces the target

+OM

• Only possible for uC in expanded mode or piggy back

4-+OM ersions


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*imulator

• *oftware deice that runs on a host and lets

you run your target code as if it were

executing on the target

• 4en though it runs ery slowly2 it$s possibleto simulate real,time eents such as interrupts

and I3O.

• *imulators best for becoming ac9uainted withnew u- or deeloping algorithms

• -ossible for all microcontrollers

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