High Voltage FET-Input Operational Amplifier datasheet ... · features wide-power supply range: ±10v to ±45v high slew rate: 15v/µs low input bias current: 10pa standard-pinout

FEATURES WIDE-POWER SUPPLY RANGE:

±10V to ±45V

HIGH SLEW RATE: 15V/ µs

LOW INPUT BIAS CURRENT: 10pA

STANDARD-PINOUT TO-99, DIP, SO-8PowerPAD , AND SO-8 SURFACE-MOUNTPACKAGES

APPLICATIONS TEST EQUIPMENT

HIGH-VOLTAGE REGULATORS

POWER AMPLIFIERS

DATA ACQUISITION

SIGNAL CONDITIONING

AUDIO

PIEZO DRIVERS

DESCRIPTION

The OPA445 is a monolithic operational amplifier capableof operation from power supplies up to ±45V and outputcurrents of 15mA. It is useful in a wide variety ofapplications requiring high output voltage or largecommon-mode voltage swings.

The OPA445’s high slew rate provides wide power-bandwidth response, which is often required forhigh-voltage applications. FET input circuitry allows theuse of high-impedance feedback networks, thus minimiz-ing their output loading effects. Laser trimming of the inputcircuitry yields low input offset voltage and drift.

The OPA445 is available in standard pinout TO-99, DIP-8,and SO-8 surface-mount packages as well as an SO-8PowerPAD package for reducing junction temperature. Itis fully specified from −25°C to +85°C and operates from−55°C to +125°C. A SPICE macromodel is available fordesign analysis (from www.ti.com).

8

1

2

7

6

53

4

OffsetTrim

OffsetTrim

Output

V+

NC

−In

+In

V−

Case is connected to V−TO−99

OPA445

1

2

3

4 5

6

7

8Offset Trim

V+−In

+In

V−

Output

Offset Trim

NC

DIP−8, SO−8, SO−8 PowerPAD

OPA445

NC = No internal connection;leave NC floating or connect to GND, V+, or V−.

OPA445

SBOS156B − MARCH 1987 − REVISED APRIL 2008

High Voltage FET-InputOPERATIONAL AMPLIFIER

! !

www.ti.com

Copyright 1987−2008, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.

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2

ABSOLUTE MAXIMUM RATINGS (1)

Power Supply ±50V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Voltage ±80V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Range |±VS| − 3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature Range: M −65°C to +150°C. . . . . . . . . . . . . .

P, U, DDA −55°C to +125°C. . . . . . . Operating Temperature Range −55°C to +125°C. . . . . . . . . . . . . . . Output Short-Circuit to Ground (TJ < +125°C) Continuous. . . . . . Junction Temperature: M +175°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction Temperature: P, U, DDA +150°C. . . . . . . . . . . . . . . . . . . . .

(1) Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periodsmay degrade device reliability. These are stress ratings only, andfunctional operation of the device at these or any other conditionsbeyond those specified is not supported.

This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits behandled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.

ORDERING INFORMATION(1)

PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING

OPA445AP DIP-8 P OPA445AP

OPA445AU SO-8 Surface-Mount D OPA445AU

OPA445ADDA SO-8 PowerPAD DDA OPA445

OPA445BM TO-99 8-Pin LMC OPA445BM

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web siteat www.ti.com.

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ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = −25°C to +85°C. VS = ±40V.At TA = +25°C, VS = ±40V, and RL = 5kΩ, unless otherwise noted.

OPA445BM OPA445AP, AU, ADDA

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

OFFSET VOLTAGEInput Offset Voltage VOS VCM = 0, IO = 0 ±1 ±3 ±1.5 ±5 mV

vs Temperature VOS/dT TA = −25°C to +85°C ±10 µV/°Cvs Power Supply PSRR VS = ±10V to ±45V 4 100 ∗ ∗ µV/V

INPUT BIAS CURRENT(1)

Input Bias Current IB VCM = 0V ±10 ±50 ∗ ±100 pAOver Specified Temperature Range ±10 ±20 nA

Input Offset Current IOS VCM = 0V ±4 ±20 ∗ ±40 pAOver Specified Temperature Range ±5 ±10 nA

NOISEInput Voltage Noise Density, f = 1kHz en 15 ∗ nV/√HzCurrent Noise Density, f = 1kHz in 6 ∗ fA/√Hz

INPUT VOLTAGE RANGECommon-Mode Voltage Range VCM VS = ±40V (V−) + 5 (V+) − 5 ∗ ∗ VCommon-Mode Rejection CMRR VCM = −35V to +35V 80 95 ∗ ∗ dB

Over Specified Temperature Range 80 dB

INPUT IMPEDANCEDifferential 1013 || 1 ∗ Ω || pFCommon-Mode 1014 || 3 ∗ Ω || pF

OPEN-LOOP GAIN, DCOpen-Loop Voltage Gain AOL VO = −35V to +35V 100 110 ∗ ∗ dB

Over Specified Temperature Range 97 ∗ dB

FREQUENCY RESPONSEGain Bandwidth Product GBW 2 ∗ MHzSlew Rate SR VO = 70VPP 5 15 ∗ ∗ V/µsFull Power Bandwidth VO = 70VPP 23 70 ∗ ∗ kHzRise Time VO = ±200mV 100 ∗ nsOvershoot G = +1, ZL = 5kΩ || 50pF 35 ∗ %Total Harmonic Distortion + Noise THD+N f = 1kHz, VO = 3.5Vrms, G = 1 0.0002 ∗ %

f = 1kHz, VO = 10Vrms, G = 1 0.00008 ∗ %

OUTPUTVoltage Output VO (V−) + 5 (V+) − 5 ∗ ∗ V

Over Specified Temperature Range (V−) + 5 (V+) − 5 VCurrent Output IO VO = ±28V ±15 ∗ mAOutput Resistance, Open Loop RO dc 220 ∗ ΩShort Circuit Current ISC ±26 ∗ mACapacitive Load Drive CLOAD See Typical Characteristic(2) ∗POWER SUPPLYSpecified Operating Range VS ±40 ∗ VOperating Voltage Range ±10 ±45 ∗ ∗ VQuiescent Current IQ IO = 0 ±4.2 ±4.7 ∗ ∗ mA

TEMPERATURE RANGESpecification Range −25 +85 ∗ ∗ °COperating Range −55 +125 ∗ ∗ °CStorage Range −65 +125 −55 +125 °CThermal Resistance,Junction-to-Ambient JA

TO-99 200 °C/WDIP-8 100 °C/WSO-8 Surface-Mount 150 °C/WSO-8 PowerPAD(3) 52 °C/W

Thermal Resistance, Junction-to-Case JC

SO-8 PowerPAD(3) 10 °C/W

NOTE: ∗ Specifications same as OPA445BM.(1) High-speed test at TJ = +25°C.(2) See Small-Signal Overshoot vs Load Capacitance in the Typical Characteristics section.(3) Test board 1in x 0.5in heat-spreader, 1oz copper.

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TYPICAL CHARACTERISTICS

At TA = +25°C and VS = ±40V, unless otherwise noted.

10 1k100 10k 1M 10M

Frequency (Hz)

0

140

120

100

80

60

40

20

Vol

tage

Gai

n(d

B)

OPEN−LOOP GAIN AND PHASEvs FREQUENCY

100k

Gain

θ

−185

−45

−90

−135

Pha

se(

)10 20 30 40 50

Supply Voltage (±VS)

125

120

115

110

105

100

95

Vol

tage

Gai

n(d

B)

OPEN−LOOP GAIN AND SUPPLY CURRENTvs SUPPLY VOLTAGE

Sup

ply

Cu

rre

nt(m

A)

AVOL

3.0

4.5

4.0

3.5

IQ

GBW

−75 0−50 −25 25 75 100 125

Ambient Temperature (C)

1.4

2.6

2.4

2.2

2.0

1.8

1.6

Ga

inB

and

wid

th(M

Hz)

GAIN BANDWIDTH AND SLEW RATEvs TEMPERATURE

SR

10

16

15

14

13

12

11

50

Sle

wR

ate

(V/µ

s)

GBW

10 20 30 40 50

Supply Voltage (±VS)

1.6

2.2

2.0

1.8

Gai

nB

andw

idth

(MH

z)

GAIN BANDWIDTH AND SLEW RATEvs SUPPLY VOLTAGE

Sle

wR

ate

(V/µ

s)

SR

13

19

17

15

−75 0−50 −25 25 75 100 125

Temperature (C)

0.01pA

100nA

10nA

1nA

100pA

10pA

1pA

0.1pA

Inp

utB

ias

Cur

rent

INPUT BIAS CURRENTvs TEMPERATURE

50 −50 −40 −30 −20 −10

−IB +IB

0 10 20 30 40 50

Common−Mode Voltage (V)

40

35

30

25

20

15

10

5

0

Bia

sC

urre

nt(

pA

)

INPUT BIAS CURRENTvs COMMON−MODE VOLTAGE

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TYPICAL CHARACTERISTICS (continued)


10 100 1k 10k 1M 10M 100M

Frequency (Hz)

0

Pow

erS

upp

lyR

eje

ctio

n(d

B)

POWER SUPPLY REJECTIONvs FREQUENCY

100k

120

100

80

60

40

20

−PSRR

+PSRR

10 100 1k 10k 1M 10M

Frequency (Hz)

Com

mo

n−M

ode

Re

ject

ion

(dB

)

COMMON−MODE REJECTIONvs FREQUENCY

100k

100

90

80

70

60

50

40

−75 0−50 −25 25 75 100 125


90

120

110

100

Vol

tage

Gai

n(d

B)

OPEN−LOOP GAINvs TEMPERATURE

50 −75 0−50 −25 25 75 100 125


130

120

110

100

90

80

70

PS

RR

,C

MR

R(d

B)

POWER SUPPLY REJECTION ANDCOMMON−MODE REJECTION vs TEMPERATURE

50

PSRR

CMRR

10 100 1k 100k

Frequency (Hz)

1

100

10

Vo

ltage

Noi

se(n

V/√

Hz)

10k

INPUT VOLTAGENOISE SPECTRAL DENSITY

20 100 1k 20k

Frequency (Hz)

0.1

0.01

0.001

0.0001

0.00001

TH

D+N

oise

(%)

10k

TOTAL HARMONIC DISTORTION + NOISEvs FREQUENCY

VO = 3.5Vrms

VO = 10VrmsVO = 3.5Vrms

VO = 10Vrms

G = 10

G = 1

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OUTPUT VOLTAGE SWING vs OUTPUT CURRENT(V+)

(V+) − 2

(V+) − 4

(V+) − 6

(V+) − 8

(V+) − 10

(V−) + 10

(V−) + 8

(V−) + 6

(V−) + 4

(V−) + 2

(V−)0 ±5 ±10 ±15 ±20 ±30±25

Output Current (mA)

Out

put

Vol

tage

Sw

ing

(V)

SinkingCurrent

SourcingCurrent

OUTPUT VOLTAGE SWING vs TEMPERATURE(V+)

(V+) − 1

(V+) − 2

(V+) − 3

(V+) − 4

(V−) + 4

(V−) + 3

(V−) + 2

(V−) + 1

(V−)−75 −50 −25 0 25 50 12575 100

Temperature (C)

Out

putV

olta

ge

Sw

ing

(V) Positive Swing

Negative Swing

−75 0−50 −25 25 75 100 125


SUPPLY CURRENT vs TEMPERATURE

50

2

5

4

3

Su

pply

Cu

rren

t(m

A)

−50 −25 0 25 75 100 125

Temperature (C)

0

35

30

25

20

15

10

5

Ou

tput

Cur

rent

(mA

)OUTPUT CURRENT vs TEMPERATURE

50

Output Current

VO = ±35V

Short−Circuit Current

OFFSET VOLTAGEPRODUCTION DISTRIBUTION

Per

cent

ofA

mpl

ifie

rs(%

)

Offset Voltage (mV)

20

18

16

14

12

10

8

6

4

2

0

Typical productiondistribution ofpackaged units.

− 5.0

− 4.5

− 4.0

− 3.5

− 3.0

− 2.5

− 2.0

− 1.5

− 1.0

− 0.5 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

OFFSET VOLTAGE DRIFTPRODUCTION DISTRIBUTION

Per

cent

ofA

mpl

ifie

rs(%

)

Offset Voltage Drift (µV/C)

25

20

15

10

5

0

Typical productiondistribution ofpackaged units.

0 2 4 6 8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

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−50 −25 0 25 75 100 125

Temperature (C)

0

Dis

sipa

tion

(W)

MAXIMUM POWER DISSIPATIONvs TEMPERATURE

50

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Plastic DIP

No Heat Sink

TJ (max)TO−99: 150CDIP, SO: 125C

TO−99

SO−8Surface−Mount

(non PowerPAD)

−50 −25 0 25 75 100 125

Temperature (C)

Dis

sipa

tion

(W)

MAXIMUM POWER DISSIPATIONvs TEMPERATURE

50

2.0

1.5

1.0

0.5

0

TJ (125C max) = TA + [(|VS| − |VO |) IO × θJA]

θJA = 52C/W, SO−8 PowerPAD

(1in × 0.5in heat−spreader, 1oz Copper)

TJ = 25C + (1.93W × 52C/W) = +125C

SO−8 PowerPAD:TJ(max) = +125C

MAXIMUM OUTPUT VOLTAGE SWINGvs FREQUENCY

100k

Frequency (Hz)

1k 10k 1M

90

80

70

60

50

40

30

20

10

Out

putV

olta

ge

(VP

P)

0

Maximum outputwithout slew−rateinduced distortion.

10pF 100pF 1nF 10nF

Load Capacitance

Ove

rsh

oot

(%)

SMALL−SIGNAL OVERSHOOTvs LOAD CAPACITANCE

60

50

40

30

20

10

0

G = −1

G = +1

G = −2

G = 10

SMALL−SIGNAL STEP RESPONSEG = 1, CL = 100pF

50m

V/d

iv

500ns/div

LARGE−SIGNAL STEP RESPONSEG = 1, CL = 100pF

10V

/div

2.5µs/div

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APPLICATIONSFigure 1 shows the OPA445 connected as a basicnoninverting amplifier. The OPA445 can be used invirtually any op amp configuration.

Power-supply terminals should be bypassed with 0.1µFcapacitors, or greater, near the power supply pins. Be surethat the capacitors are appropriately rated for thepower-supply voltage used.

G = 1+R2

R1

ZL

R2R1

OPA445

V−

V+

VIN

0.1µF

0.1µF

VO

Figure 1. The OPA445 Configured as aNoninverting Amplifier

POWER SUPPLIESThe OPA445 may be operated from power supplies up to±45V or a total of 90V with excellent performance. Mostbehavior remains unchanged throughout the full operatingvoltage range. Parameters which vary significantly withoperating voltage are shown in the Typical Characteristics.

Some applications do not require equal positive andnegative output voltage swing. Power-supply voltages donot need to be equal. The OPA445 can operate with as littleas 20V between the supplies and with up to 90V betweenthe supplies. For example, the positive supply could be setto 80V with the negative supply at −10V, or vice-versa.

INPUT PROTECTIONThe inputs of conventional FET-input op amps should beprotected against destructive currents that can flow wheninput FET gate-to-substrate isolation diodes areforward-biased. This can occur if the input voltageexceeds the power supplies or there is an input voltagewith VS = 0V. Protection is easily accomplished with aresistor in series with the input. Care should be takenbecause the resistance in series with the inputcapacitance may affect stability. Many input signals areinherently current-limited; therefore, a limiting resistor maynot be required.

OFFSET VOLTAGE TRIM

The OPA445 provides offset voltage trim connections onpins 1 and 5. Offset voltage can be adjusted by connectinga potentiometer as shown in Figure 2. This adjustmentshould be used only to null the offset of the op amp, not toadjust system offset or offset produced by the signalsource. Nulling system offset could degrade the offsetvoltage drift behavior of the op amp. While it is not possibleto predict the exact change in drift, the effect is usuallysmall.

OPA4453

2

6

1

45

7

V−

10mV TypicalTrim Range

(1)

V+

NOTE: (1) 10kΩ to 1MΩTrim Potentiometer(100kΩ recommended).

Use offset adjust pinsonly to null offset voltageof op amp−see text.

Figure 2. Offset Voltage Trim

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CAPACITIVE LOADS

The dynamic characteristics of the OPA445 have beenoptimized for commonly encountered gains, loads, andoperating conditions. The combination of low closed-loopgain and capacitive load will decrease the phase marginand may lead to gain peaking or oscillations. Figure 3shows a circuit which preserves phase margin withcapacitive load. The circuit does not suffer a voltage dropdue to load current; however, input impedance is reducedat high frequencies. Consult Application BulletinSBOA015, available for download at www.ti.com, fordetails of analysis techniques and application circuits.

VO

CL5000pF

R2

R1

G = 1 +

R2

2kΩ

R1

2kΩ

VIN

NOTE: Design equations and component values are approximate.User adjustment is required for optimum performance.

RC20Ω

CC0.22µF

RC =R2

2CL × 1010 − (1 + R2/R1)

OPA445

CC =CL × 103

RC

Figure 3. Driving Large Capacitive Loads

INCREASING OUTPUT CURRENT

In those applications where the 15mA of output current isnot sufficient to drive the required load, output current canbe increased by connecting two or more OPA445s inparallel as shown in Figure 4. Amplifier A1 is the masteramplifier and may be configured in virtually any op ampcircuit. Amplifier A2, the slave, is configured as a unity gainbuffer. Alternatively, external output transistors can beused to boost output current. The circuit in Figure 5 iscapable of supplying output currents up to 1A.

R1 R2

OPA445

OPA445

Slave

Master

VIN

RS(1)

10Ω

RS(1)

10Ω

RL

NOTE: (1) RS resistors minimize the circulatingcurrent that will always flow between the two devicesdue to VOS errors.

Figure 4. Parallel Amplifiers Increase OutputCurrent Capability

R1 R2

OPA445

TIP30C

TIP29C

VIN

+45V

−45V

VO

R3(1)

100Ω

NOTE: (1) Provides current limit for OPA445 and allows the amplifier todrive the load when the output is between +0.7V and −0.7V.

R40.2Ω

R40.2Ω

LOAD

CF

Figure 5. External Output Transistors Boost Output Current Up to 1 Amp

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SAFE OPERATING AREA

Stress on the output transistors is determined both by theoutput current and by the output voltage across theconducting output transistors, VS − VO. The powerdissipated by the output transistor is equal to the productof the output current and the voltage across the conductingtransistor, VS − VO. The Safe Operating Area (SOA curve,Figure 6 through Figure 10) illustrates the permissiblerange of voltage and current. The curves shown representdevices soldered to a printed circuit board (PCB) with noheat sink. Increasing printed circuit trace area or the useof a heat sink (TO-99 package) can significantly reducethermal resistance ( ), resulting in increased outputcurrent for a given output voltage (see Figure 11,Figure 12, and the Heat Sink section).

The safe output current decreases as VS − VO increases.Output short-circuits are a very demanding case for SOA.A short-circuit to ground forces the full power supplyvoltage (V+ or V−) across the conducting transistor andproduces a typical output current of 25mA. With ±40Vpower supplies, this creates an internal dissipation of 1W.This exceeds the maximum rating and is notrecommended. If operation in this region is unavoidable,a heat sink is required. For further insight on SOA, consultApplication Bulletin SBOA022 (available for download atwww.ti.com).

1 2 5 10

|VS| − |VO| (V)

20 50 100

Out

putC

urre

nt(m

A)

TA = 25C

TA = 120CTA = 85C

TA + [(|VS| − |VO|) IO × θJA] ≤ TJ (max)θJA = 100C/WTJ (max) = 125C

100

10

1

0.1

Figure 6. DIP-8 Safe Operating Area

1 2 5 10

|VS| − |VO| (V)

20 50 100

100

10

1

Out

putC

urre

nt(

mA

)

0.1

TA = 25C

TA = 85C

TA = 125C

TA + [(|VS| − |VO|) IO × θJA] ≤ TJ (max)θJA = 200C/W (No Heat−Sink)TJ (max) = 150CNOTE: Simple clip−on heat−sinks canreduce θ by as much as 50C/W.

Figure 7. TO-99 Safe Operating Area

1 2 5 10

|VS| − |VO| (V)

20 50 100

100

10

1

Out

put

Cur

rent

(mA

)

0.1

TA = 85CTA = 120C


TA = 25C

Figure 8. SO-8 (non PowerPAD) Safe OperatingArea

1 10

|VS| − |VO| (V)

100

100

10

1

Out

put

Cur

ren

t(m

A)

0.1

TA = 25C

TA = 85CTA = 120C


Figure 9. SO-8 PowerPAD Safe Operating Area(no heat-spreader, no airflow)

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1 10

|VS| − |VO| (V)

100

100

10

1

Out

put

Cur

rent

(mA

)

0.1

TA = 25C

TA = 85C

TA = 120C


1in x 0.5in, 1oz Cu

Figure 10. SO-8 PowerPAD Safe Operating Area(with heat-spreader, no airflow)

0 0.5 1.0 1.5 2.5 3.0

Air−Flow (meters/sec)

Th

erm

alR

esis

tanc

e,θ JA

(C

/W)

2.0

120

100

80

60

40

20

0

With Heat−Spreader, 1in x 0.5in, 1oz Cu

No Heat−Spreader

Figure 11. SO-8 PowerPAD Thermal Resistance(with and without heat-spreader)

0 0.5 1.0 1.5 2.0 2.5 3.0

Copper Area (inches2)

Th

erm

alR

esis

tanc

e,θ JA

(C

/W)

100

90

80

70

60

50

40

30

No Airflow

Figure 12. Thermal Resistance vs Circuit BoardCopper Area

POWER DISSIPATIONPower dissipation depends on power supply, signal, andload conditions. For dc signals, power dissipation is equalto the product of the output current times the voltageacross the conducting output transistor, PD = IL (VS − VO).Power dissipation can be minimized by using the lowestpossible power-supply voltage necessary to assure therequired output voltage swing.

For resistive loads, the maximum power dissipation occursat a dc output voltage of one-half the power supply voltage.Dissipation with ac signals is lower. Application BulletinSBOA022 explains how to calculate or measuredissipation with unusual loads or signals.

The OPA445 can supply output currents of 15mA andlarger. This would present no problem for a standard opamp operating from ±15V supplies. With high supplyvoltages, however, internal power dissipation of the opamp can be quite large. Operation from a single powersupply (or unbalanced power supplies) can produce evenlarger power dissipation since a large voltage is impressedacross the conducting output transistor. Applications withlarge power dissipation may require a heat-sink.

HEAT SINKINGPower dissipated in the OPA445 will cause the junctiontemperature to rise. For reliable operation junctiontemperature should be limited to 125°C, maximum (150°Cfor TO-99 package). Some applications will require aheat-sink to assure that the maximum operating junctiontemperature is not exceeded. In addition, the junctiontemperature should be kept as low as possible forincreased reliability. Junction temperature can bedetermined according to the following equation:

TJ TA PD JA

Package thermal resistance, JA, is affected by mountingtechniques and environments. Poor air circulation and useof sockets can significantly increase thermal resistance.Best thermal performance is achieved by soldering the opamp into a circuit board with wide printed circuit traces toallow greater conduction through the op amp leads.Simple clip-on heat sinks (such as a Thermalloy 2257) canreduce the thermal resistance of the TO-99 metal packageby as much as 50°C/W. The SO-8 PowerPAD package willprovide lower thermal resistance, especially with a simpleheat-spreader—even lower with a heat-sink. Foradditional information on determining heat-sink require-ments, consult Application Bulletin SBOA021.

(1)

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12

PowerPAD THERMALLY-ENHANCEDPACKAGE

In addition to the SO-8, DIP-8, and TO-99 packages, theOPA445 also comes in an SO-8 PowerPAD. The SO-8PowerPAD is a standard-size SO-8 package where theexposed leadframe on the bottom of the package can besoldered directly to the PCB to create an extremely lowthermal resistance. This architecture enhances theOPA445’s power dissipation capability significantly andeliminates the use of bulky heatsinks and slugstraditionally used in thermal packages. This package canbe easily mounted using standard PCB assemblytechniques. NOTE: Since the SO-8 PowerPAD ispin-compatible with standard SO-8 packages, theOPA445 can directly replace operational amplifiers inexisting sockets. Soldering the PowerPAD to the PCB isalways required, even with applications that have lowpower dissipation. Soldering the device to the PCBprovides the necessary thermal and mechanicalconnection between the leadframe die pad and the PCB.

The PowerPAD package is designed so that the leadframedie pad (or thermal pad) is exposed on the bottom of theIC; see Figure 13. This design provides an extremely lowthermal resistance (JC) path between the die and theexterior of the package. The thermal pad on the bottom ofthe IC can then be soldered directly to the PCB, using thePCB as a heatsink. In addition, plated-through holes (vias)provide a low thermal resistance heat flow path to the backside of the PCB.

Mold Compound (Plastic)Leadframe Die Pad

Exposed at Base of the Package(Copper Alloy)

Leadframe (Copper Alloy)

IC (Silicon) Die Attach (Epoxy)

Figure 13. Section View of a PowerPAD Package

GENERAL PowerPAD LAYOUT GUIDELINES

The OPA445 is available in a thermally-enhancedPowerPAD package. This package is constructed using adownset leadframe upon which the die is mounted. Thisarrangement results in the lead frame being exposed as athermal pad on the underside of the package. This thermalpad has direct thermal contact with the die; thus, excellentthermal performance is achieved by providing a goodthermal path away from the thermal pad.

The PowerPAD package allows for both assembly andthermal management in one manufacturing operation.During the surface-mount solder operation (when theleads are being soldered), the thermal pad must besoldered to a copper area underneath the package.Through the use of thermal paths within this copper area,heat can be conducted away from the package into eithera ground plane or other heat-dissipating device. Solderingthe PowerPAD to the PCB is always required, even withapplications that have low power dissipation. Follow thesesteps:

1. The PowerPAD must be connected to the mostnegative supply voltage on the device, V−.

2. Prepare the PCB with a top-side etch pattern. Thereshould be etching for the leads as well as etch for thethermal pad.

3. Place recommended holes in the area of the thermalpad. Recommended thermal land size and thermal viapatterns for the SO-8 DDA package is shown inFigure 14. These holes should be 13 mils in diameter.Keep them small, so that solder wicking through theholes is not a problem during reflow. The minimumrecommended number of holes for the SO-8PowerPAD package is five.

4. Additional vias may be placed anywhere along thethermal plane outside of the thermal pad area. Thesevias help dissipate the heat generated by the OPA445IC. These additional vias may be larger than the 13-mildiameter vias directly under the thermal pad. They canbe larger because they are not in the thermal pad areato be soldered; thus, wicking is not a problem.

5. Connect all holes to the internal power plane of thecorrect voltage potential (V−).

6. When connecting these holes to the plane, do not usethe typical web or spoke via connection methodology.Web connections have a high thermal resistanceconnection that is useful for slowing the heat transferduring soldering operations, makeing the soldering ofvias that have plane connections easier. In thisapplication, however, low thermal resistance isdesired for the most efficient heat transfer. Therefore,the holes under the OPA445 PowerPAD packageshould make the connections to the internal plane witha complete connection around the entirecircumference of the plated-through hole.

7. The top-side solder mask should leave the terminalsof the package and the thermal pad area exposed.The bottom-side solder mask should cover the holesof the thermal pad area. This masking prevents solderfrom being pulled away from the thermal pad areaduring the reflow process.

8. Apply solder paste to the exposed thermal pad areaand all of the IC terminals.

""#


www.ti.com

13

9. With these preparatory steps in place, the PowerPADIC is simply placed in position and run through thesolder reflow operation as any standard surfacemountcomponent. This preparation results in a properlyinstalled part.

For detailed information on the PowerPAD package,including thermal modeling considerations and repairprocedures, see technical brief SLMA002 PowerPADThermally-Enhanced Package available for download atwww.ti.com.

OPTIONAL:

REQUIRED:

Thermal Land(Copper)

Minimum Size4.8mm x 3.8mm

(189 mils x 150 mils)

Additional four vias outsideof thermal pad area butunder the package.

Thermal pad area 2.286mm x 2.286mm(90 mils x 90 mils) with five vias(via diameter = 13 mils)

Figure 14. 8-Pin PowerPAD PCB Etch and ViaPattern

TYPICAL APPLICATIONS

OPA445

R1

Compliance Voltage Range = ±35V

NOTE: R1 = R3 and R2 = R4 + R5

+40V

100kΩR2

10kΩ

R3100kΩ

R49.9kΩ

−40VR5

100Ω

ILLoad

IL = [(V2 − V1)/R5] (R2/R1)= (V2 − V1)/1kΩ

V2

V1

Figure 15. Voltage-to-Current Converter

OPA445

0−2mA

+60V

25kΩ

−12V

VO = 0V to +50Vat 10mA

0.1µF

0.1µF

Protects DACDuring Slewing

DAC8811or

DAC7811

Figure 16. Programmable Voltage Source

+45V

160V

Piezo(1)

Crystal

−45V

Master

R2

9kΩR1

1kΩ

VIN±4V

OPA445

+45V

−45V

Slave

R4

10kΩ

R3

10kΩ

OPA445

NOTE: (1) For transducers with large capacitance the stabilizationtechnique described in Figure 6 may be necessary. Be certain that theMaster amplifier is stable before stabilizing the Slave amplifier.

Figure 17. Bridge Circuit Doubles Voltage for Piezo Crystals

PACKAGE OPTION ADDENDUM

www.ti.com 8-Apr-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA445ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS& no Sb/Br)

CU NIPDAUAG Level-2-260C-1 YEAR -55 to 125 OPA445

OPA445ADDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS& no Sb/Br)


OPA445ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS& no Sb/Br)


OPA445AP ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)

CU NIPDAU N / A for Pkg Type -55 to 125 OPA445AP

OPA445APG4 ACTIVE PDIP P 8 50 Green (RoHS& no Sb/Br)

CU NIPDAU N / A for Pkg Type -55 to 125 OPA445AP

OPA445AU ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR OPA445AU

OPA445AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -55 to 125 OPA445AU

OPA445AUG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -55 to 125 OPA445AU

OPA445BM ACTIVE TO-99 LMC 8 20 Green (RoHS& no Sb/Br)

AU N / A for Pkg Type OPA445BM

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

http://www.ti.com/product/OPA445?CMP=conv-poasamples#samplebuy









http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 8-Apr-2016

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA445ADDAR SOPower PAD

DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA445AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA445ADDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0

OPA445AU/2K5 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

DDA 8 PowerPAD TM SOIC - 1.7 mm max heightPLASTIC SMALL OUTLINE

4202561/G

www.ti.com

PACKAGE OUTLINE

C TYP6.2

5.8

1.7 MAX

6X 1.27

8X 0.510.31

2X3.81

TYP0.250.10

0 - 80.150.00

2.62.0

3.12.5

0.25GAGE PLANE

1.270.40

A

NOTE 3

5.04.8

B 4.03.8

4221637/B 03/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008JPLASTIC SMALL OUTLINE

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MS-012, variation BA.

PowerPAD is a trademark of Texas Instruments.

TM

18

0.1 C A B

54

PIN 1 IDAREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.400

EXPOSEDTHERMAL PAD

4

1

5

8

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

0.07 MAXALL AROUND

0.07 MINALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)NOTE 9

(4.9)NOTE 9

(2.6)

(3.1)SOLDER MASK

OPENING

( ) TYPVIA

0.2

(1.3) TYP

(1.3)TYP

4221637/B 03/2016


SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLESCALE:10X

1

4 5

8

SOLDER MASKOPENING

METAL COVEREDBY SOLDER MASK

SOLDER MASKDEFINED PAD

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).9. Size of metal pad may vary due to creepage requirement.

TM

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.6)

(3.1)BASED ON

0.127 THICKSTENCIL

4221637/B 03/2016


2.20 X 2.620.1752.37 X 2.830.150

2.6 X 3.1 (SHOWN)0.1252.91 X 3.470.1

SOLDER STENCILOPENING

STENCILTHICKNESS

NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design.

TM

SOLDER PASTE EXAMPLEEXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREASCALE:10X

SYMM

SYMM

1

45

8

BASED ON0.125 THICK

STENCIL

BY SOLDER MASKMETAL COVERED SEE TABLE FOR

DIFFERENT OPENINGSFOR OTHER STENCILTHICKNESSES

IMPORTANT NOTICE

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High Voltage FET-Input Operational Amplifier datasheet ... · features wide-power supply range: ±10v to ±45v high slew rate: 15v/µs low input bias current: 10pa standard-pinout