High-temperature CVD silicon films for crystalline silicon

High-temperature CVD silicon films forcrystalline silicon thin-film solar cells

Dissertation

zur Erlangung des

akademischen Grades des

Doktors der Naturwissenschaften(Dr. rer. nat.)

an der Universität KonstanzFakultät für Physik

vorgelegt von

Sandra Bau

Fraunhofer Institut für Solare Energiesysteme

Freiburg

2003

Referenten: Priv. Doz. Dr. Gerhard WillekeProf. Dr. Wolfram Wettling

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Contents

1 Introduction 1

2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells 3

2.1 Principle of CSiTF solar cells ..................................................................................................... 32.1.1 General .............................................................................................................................. 32.1.2 CSiTF solar cell components ............................................................................................ 4

2.2 Thin Film Concepts ..................................................................................................................... 52.2.1 Low-temperature approach................................................................................................ 62.2.2 High-temperature approach............................................................................................... 72.2.3 Transfer techniques ........................................................................................................... 7

3 Chemical vapor deposition (CVD) of silicon 9

3.1 Silicon deposition techniques ...................................................................................................... 93.1.1 Liquid Phase Epitaxy (LPE).............................................................................................. 93.1.2 Physical Vapor Deposition (PVD) .................................................................................. 103.1.3 Chemical Vapor Deposition (CVD) ................................................................................ 103.1.4 Overview on deposition techniques and applications ..................................................... 12

3.2 Deposition principle of silicon by thermal CVD....................................................................... 133.2.1 Transport ......................................................................................................................... 133.2.2 Thermal equilibrium conditions ...................................................................................... 133.2.3 Reaction kinetics ............................................................................................................. 153.2.4 Chemical yield................................................................................................................. 19

3.3 Reactor design for APCVD....................................................................................................... 20

3.4 APCVD at Fraunhofer ISE........................................................................................................ 213.4.1 Reactor design ................................................................................................................. 213.4.2 RTCVD100 ..................................................................................................................... 223.4.3 RTCVD160 ..................................................................................................................... 273.4.4 Continuous CVD (ConCVD) .......................................................................................... 28

3.5 Summary ................................................................................................................................... 30

4 Process Optimization for RTCVD100 33

4.1 Metrology .................................................................................................................................. 334.1.1 Thickness measurement .................................................................................................. 334.1.2 Doping control................................................................................................................. 364.1.3 Impurity concentration measurements by SIMS ............................................................. 414.1.4 Defects............................................................................................................................. 424.1.5 Lifetime measurement by MW-PCD............................................................................... 42

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4.2 Epitaxial deposition................................................................................................................... 424.2.1 Pre-epitaxial sample cleaning.......................................................................................... 434.2.2 Thickness uniformity....................................................................................................... 434.2.3 Doping of epilayers ......................................................................................................... 464.2.4 Crystal quality ................................................................................................................. 484.2.5 Lifetime measurements ................................................................................................... 494.2.6 Chemical analysis............................................................................................................ 504.2.7 Surface morphology of multicrystalline layers ............................................................... 52

4.3 Silicon deposition on foreign substrates.................................................................................... 544.3.1 Thickness uniformity....................................................................................................... 544.3.2 Doping of seeding layers................................................................................................. 56

4.4 Layer growth in RTCVD160..................................................................................................... 56

4.5 Summary ................................................................................................................................... 58

5 Doping of epitaxial silicon layers 61

5.1 Dopant incorporation................................................................................................................. 61

5.2 Doping profiles of epitaxial layers ............................................................................................ 65

5.3 Experimental carrier concentration profiles .............................................................................. 665.3.1 Boron diffusion and evaporation..................................................................................... 665.3.2 Background doping and memory effect .......................................................................... 685.3.3 Doping profile of intrinsic epilayers................................................................................ 715.3.4 Standard epitaxy .............................................................................................................. 765.3.5 Deposition with pre-epitaxial diffusion........................................................................... 805.3.6 High-low deposition ........................................................................................................ 81

5.4 Effect of doping profile on solar cell performance.................................................................... 82

5.5 Improved gas system design...................................................................................................... 84

5.6 Summary ................................................................................................................................... 85

6 Epitaxial thin-film solar cells 87

6.1 Solar cell concept ...................................................................................................................... 876.1.1 Silicon substrate materials............................................................................................... 886.1.2 Efficiency ........................................................................................................................ 896.1.3 Epitaxial deposition systems ........................................................................................... 906.1.4 Efficiency table for epitaxial thin-film solar cells ........................................................... 90

6.2 Solar cells on Cz-Si substrates .................................................................................................. 916.2.1 Solar cell processing........................................................................................................ 926.2.2 RTCVD-process A vs. B ................................................................................................. 936.2.3 Epilayer quality ............................................................................................................... 956.2.4 Comparison of solar cell technologies ............................................................................ 966.2.5 Overview on solar cell efficiencies ............................................................................... 1016.2.6 Characterization by lock-in thermography.................................................................... 1026.2.7 Summary ....................................................................................................................... 104

6.2.8 Solar cell simulation...................................................................................................... 105

6.3 Solar cells on mc-silicon substrates......................................................................................... 111

6.4 Solar cells on reclaimed silicon wafers ................................................................................... 116

6.5 Front surface texturing for epitaxial cells................................................................................ 119

6.6 Innovative solar cell technology by CVD ............................................................................... 1206.6.1 Emitter epitaxy .............................................................................................................. 1206.6.2 Boron BSF epitaxy and diffusion.................................................................................. 1206.6.3 In-situ HCl texturing ..................................................................................................... 121

6.7 Summary ................................................................................................................................. 121

7 Silicon thin-film solar cells on insulating substrates 123

7.1 Solar Cell principle and technology ........................................................................................ 1237.1.1 Layer system ................................................................................................................. 1237.1.2 Cell technology ............................................................................................................. 124

7.2 Silicon thin-film solar cells on ceramic substrates .................................................................. 1257.2.1 Material and solar cell preparation ................................................................................ 1267.2.2 Silicon thin-films on silicon-infiltrated silicon carbide ceramics (SiSiC)..................... 1287.2.3 Silicon thin-films on hot-pressed silicon nitride ceramics ............................................ 1327.2.4 Silicon thin-films on tape cast silicon nitride ceramics................................................. 1367.2.5 Silicon thin-films on SiAlON ceramics......................................................................... 141

7.3 Summary ................................................................................................................................. 143

8 Summary 145

Deutsche Zusammenfassung 149

Appendix A Abbreviations 153

Appendix B Solar cell fundamentals 155

Bibliography 159

Publications 171

Acknowledgements 173

1

1 Introduction

The development of renewable energies is motivated by the wish to avoid the problems associated tonuclear and fossil energy production and to use environment-friendly energy sources instead. Duringthe last decade the photovoltaic (PV) market has experienced a steady growth of 15-25% with thegrowth rate even exceeding 40% in 2000 [1]. In the near future a further increase in growth rate isexpected. Despite this rising trend, energy production by photovoltaic sources only plays a minor rolewith respect to the world’s energy production. At present, PV electric energy is still more costly thangrid electricity and government subsidies programs are running to support the application of PVsystems.

Today’s PV module market is dominated by crystalline silicon solar cells. In 2001, about 91% of thePV market share were held by crystalline silicon, the major part being provided by polycrystalline(48%) and single-crystal (35%) material (Figure 1.1). Silicon solar cell manufacturing benefits from amature technology and expertise available from microelectronics, non-toxicity, long-term stability andlarge material abundance of silicon. Thin-film technologies like amorphous silicon (a-Si:H), CIS(CuInGaSe2) and CdTe make up for only a small fraction of the world’s module market. While theefficiency of a-Si:H modules still ranges on a comparatively low level of 8%, and CIS solar cells haveto deal with a possible indium bottleneck, CdTe is the least attractive material due to the high toxicityof Cd and Te. The latter two technologies have just about started pilot-line production.

Polycrystal Si47.54%

Single Crystal Si35.17%

Si Film0.26%

Ribbon Si3.5%

a-Si on Cz Slice4.63%

Amorphous Si8.3%

CIS0.18%

Cadmium Telluride0.42%

Figure 1.1: Market shares of photovoltaic materials (after [2]).

About 40% of the silicon module cost are made up by the silicon wafer [3]. With increasing growth ofthe photovoltaic market, the demand for crystalline silicon material will rise. Currently, the PVindustry obtains silicon wafers and raw material from microelectronic production: off spec, pot-scrap,tops and tails from electronic grade silicon production are used as silicon sources for solar cellmanufacturing [4]. The price for a silicon wafer and with that the module price is therefore highlydependent on the microelectronic market. With growing PV industry the need for crystalline silicon

1 Introduction2

wafers will permanently rise, while in microelectronics the trend goes to smaller devices and higherdevice density per wafer i.e. lower material consumption and production. The two counteracting trendsled to an imminent silicon feedstock bottleneck for PV applications. Today’s research activities seekto avoid or diminish this shortage by the development of alternative silicon solar cell concepts withreduced silicon consumption and by the establishment of an independent solar grade siliconproduction [5]. In the long term, thin-film cells (silicon or other materials) are assumed to become themarket dominating technology.

The concept of crystalline silicon thin-film (CSiTF) solar cells can substantially reduce siliconmaterial consumption and has the potential to reach high efficiencies comparable to wafer silicon solarcells. During the past decade a lot of research has been done on this subject and a large variety ofsilicon thin-film solar cell concepts have been investigated. At present, none of the approaches hasmade a final breakthrough to industrial production and the neck-and-neck race continues to pushresearch activities further on.

This work deals with the deposition of silicon films for CSiTF solar cells and the realization of thiscell concept by different approaches. The following chapter explains the basic components of acrystalline silicon thin-film solar cell and gives an overview on current approaches.

In the third chapter, silicon deposition techniques are reviewed and the potential of atmosphericpressure chemical vapor deposition (APCVD) for an application in CSiTF solar cell technology ismotivated. The silicon deposition process by chemical vapor deposition is theoretically explained andan example for a silicon growth model is given. Subsequently the silicon deposition and reactor designpursued at Fraunhofer ISE is presented. The APCVD reactor concept is adapted to the needs ofphotovoltaic industry an therefore differs from commercial reactor configurations. Technical detailsare discussed and key features of the reactor design are explained.

The characterization and optimization of silicon epitaxial layers (epilayers) and silicon layers onforeign substrates (seeding layers) by APCVD is presented in chapter four. Silicon films grown underdifferent process conditions are analyzed and standard processes are defined, which allow for adeposition of silicon layers with well defined properties. The controlled growth of silicon films is aprerequisite for a successful preparation of any device based on these layers and the results obtainedduring the optimization process are therefore of great importance for the entire work.

The detailed characterization of carrier concentration profiles in silicon epilayers by SpreadingResistance Profiling is subject of chapter five. Important insight on the effect of the gas system oncarrier concentration profiles and on the mechanisms of boron incorporation during silicon depositioncan be obtained from this analysis.

Chapter six deals with the preparation of epilayers on different electrically inactive silicon substratesfor a preparation of epitaxial silicon thin-film solar cells. The application of industrial type solar cellprocessing techniques on epitaxial material is a main topic of this work and an extensive investigationof possible interactions between epilayers and different solar cell process steps is carried out. The useof multicrystalline and potential low-cost reclaimed silicon wafers as substrates is studied.

In the last chapter, silicon thin-film solar cells on non-conductive ceramic substrates are investigated.Silicon films are prepared on four different ceramic substrates by silicon layer deposition,recrystallization and epitaxy of the base layer. Sample structure and solar cell performance arecharacterized in detail and the suitability of the applied ceramic substrates is evaluated.

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2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells

Reduction in final module cost is one of the basic motivations in silicon solarcell research today. Main focus is put on a reduction in electronic gradesilicon usage and solar cell concepts consuming less silicon material andways to bypass the silicon feedstock bottleneck are currently investigated.The concept of crystalline silicon thin-film solar cells tackles this problem byusing an active device region which is reduced to a thin layer, only aboutone tenth of conventional wafer cells. The fundamental principles anddifferent approaches for CSiTF solar cells are reviewed in this chapter.

2.1 Principle of CSiTF solar cells

2.1.1 GeneralCost-saving is the key word associated to most solar cell research subjects today. Considering the costbreakdown for a commercial silicon PV module, the silicon wafer makes up for 42% of the finalmodule cost, while the remaining 58% are shared by module fabrication and solar cell technology [3].With increasing growth of silicon module production the consumption of electronic grade silicon forPV applications rises and silicon feedstock is assumed to get short in the future, leading to an increasein material cost. The largest cost-saving potential in silicon module production can be expected fromthe silicon wafer. Reducing silicon feedstock cost and lowering silicon consumption are two ways toreduce the price for silicon solar cell material. The latter solution is addressed in the following.

Conventional silicon solar cells are prepared on silicon wafers of 250-300 µm thickness. Thetechnology used for wafering and the need for mechanical stability of the device determine the waferthickness. With respect to solar cell performance thinner base layers have the potential to yield similaror even higher efficiencies compared to conventional “thick” wafer cells and therefore many researchgroups follow a “thin silicon film” approach to reduce material consumption.

- Thin wafers

Wire sawing of silicon ingots is state-of-the-art technology for the production of silicon wafersresulting in wafer thickness of 250-300 µm with a kerf loss in the range of 200 µm. From atechnical point of view a reduction of kerf loss is difficult to realize, due to an increased danger ofwire breakage with decreasing saw wire thickness. Reducing the wafer thickness and thereforeincreasing wafer output is more feasible and can substantially lower material cost [6], [5] withoutsuffering from efficiency losses. While the production of thin wafers (~100 µm thickness) isalready technically feasible, solar cell processing of these wafers is still a problem due to theincreased fragility of the material. At present, research activities in this area deal with thedevelopment of new wafering technologies and the development of solar cell processes adapted tothe properties and needs of thin wafers.

2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells4

- Silicon ribbons

Silicon ribbon technologies bypass the necessity for ingot production and the associated loss insilicon material. The edge-defined film-fed growth (EFG) by ASE is the most mature ribbontechnology. Following this approach, silicon sheets with a thickness of 250-300 µm are directlypulled from the melt, laser cut and used as silicon wafer material. The String Ribbon technique byEvergreen Solar, the Dendritic Web by Ebara, RGS (ribbon growth on substrate) by ECN(Netherlands Energy Research foundation) and SSP (silicon sheets from powder) by FraunhoferISE constitute other important silicon ribbon techniques. Higher throughput and further decreasein film thickness are two major issues in silicon ribbon development to become industriallyrelevant technologies. An overview on this issue can be found in [7].

- Silicon thin-film solar cells

The concept of silicon thin-film solar cells is based on the deposition of a thin (<50 µm) activesilicon layer on a low-cost substrate. Within this approach the manufacturing of silicon ingots andwafering is avoided and material loss is mainly determined by the chemical yield of the depositionprocess. Moreover, silicon deposition from a gaseous source is used in most approaches with thesilicon-containing source gas being an early element in the chain of silicon ingot production. Thebenefit from using a crystalline silicon thin-film concept compared to conventional wafertechnology is the potential to reach high efficiencies at low material consumption. A detailedoverview on crystalline silicon thin-film concepts is given in [8] and [9].

The cost per MWp photovoltaic electric power production is determined by module manufacturingcost, module efficiency and up-time. Therefore the choice of the solar cell concept to be followed isactually a trade-off between the two first aspects.

2.1.2 CSiTF solar cell componentsThe working principle of a solar cell is extensively discussed in various textbooks and shall not bedescribed here [10], [11]1. Instead, the essential features of a CSiTF solar cell will be explained toenable an understanding of the device structure.

Efficiency potential

Reducing the thickness of a solar cell results in an increase in open-circuit voltage, if the short-circuitcurrent can be maintained and surface recombination velocities are sufficiently low [12]. So, ifefficient light trapping and surface passivation schemes can be provided, a solar cell with reducedthickness can even yield higher efficiencies compared to a corresponding “thick” wafer cell, assumingequal bulk diffusion lengths. This holds especially for low quality material featuring low minoritycarrier diffusion lengths. The potential of crystalline silicon thin-film solar cells and similarly thincrystalline silicon solar cells is based on these interrelations.

An indicator which is often used to qualitatively estimate the potential of a solar cell is the ratio of cellthickness W to bulk diffusion length Ln. Assuming zero surface recombination velocities and activebase thickness substantially smaller than bulk diffusion length, the saturation current density is

1 A short introduction to solar cell device physics is given in the appendix.

2.2 Thin Film Concepts 5

proportional to the ratio W/Ln i.e. the lower the base thickness at constant diffusion length, the lowerthe saturation current [12]. For low quality material, a reduction in base layer thickness is therefore ofadvantage. As a rule of thumb the effective minority carrier diffusion length in the base should exceed2-3 times the layer thickness to achieve reasonable efficiencies for CSiTF solar cells. In the appendix,the correlation between saturation current, open-circuit voltage and the ratio W/Ln is derived.

Light trapping

Silicon is an indirect semiconductor and a wafer thickness exceeding 140 µm is needed to absorb 90%of the incident photons of the solar spectrum (AM1.5)2. Reducing the active base thickness to 20 µm afraction of about 75% of the incident photons can be used for photocurrent generation [13]. Thephoton absorption capacity in a thin film can be increased by increasing the optical path length in thelayer. Features leading to such an enhancement are commonly referred to as light trapping schemes. Insilicon thin-film solar cells an efficient light trapping is mandatory to achieve high photocurrentsdespite the reduced absorber thickness.

Surface texturing combined with a diffuse back side reflector effectively confines the incident light tothe active device region. Apart from increasing the optical path length, the surface texturing alsoreduces reflection. Similarly, antireflection coatings deposited on the surface of the solar cell decreasethe fraction of reflected light which is coupled into the bulk of the device instead.

Surface and bulk passivation

With decreasing device thickness surface recombination losses gain in importance and surfacepassivation schemes are indispensable. While the front surface can be well passivated by oxide ornitride layers, the rear surface of the active base region is given by the highly recombinative substratesurface for thin-film solar cells. Minority carriers reaching this surface quickly recombine and are lostfor photocurrent generation. The implementation of a back surface field (BSF), a highly doped regionat the back of the base, confines the minority carriers to the lower doped base region, thereby reducingthe rear surface recombination losses.

Recombination on grain boundaries dominates minority carrier lifetime in polycrystalline silicon thin-film solar cells. Passivation of grain boundaries e.g. by hydrogen is often used to reducerecombination and increase bulk minority carrier lifetime.

2.2 Thin Film ConceptsTraditionally, the solar cell concepts for crystalline silicon thin-film cells are divided into the so-calledhigh-temperature and low-temperature approach, according to the maximum temperature the devicecan tolerate during processing. The threshold temperature is usually determined by the temperaturestability of the substrate to be used. Within this classification the transfer (or lift-off) techniques takean exceptional position. Using this approach, epitaxial silicon films are grown at high or mediumtemperatures on ideal silicon wafers and subsequently transferred to low-cost, mechanicallysupporting substrates. So, with respect to the host substrate used for silicon deposition, this technique

2 AM1.5: Air Mass 1.5, standard solar spectrum used for terrestrial solar cell calibration. The sunlight passes anair mass which is by factor 1.5 larger compared to vertical incidence.


belongs to the high-temperature approach although the final supporting substrate is in general a low-temperature material. In the following, the transfer techniques are discussed in a separate section.

Common to all approaches is the need for a suitable high-rate silicon deposition tool to satisfy theneed for high throughput imposed by industrial production.

2.2.1 Low-temperature approachWithin the low-temperature approach, glass is the most prominent and most attractive substratematerial. Borosilicate glasses and soda lime glasses are mechanically stable up to 650°C and 550°Crespectively, and can be produced on a large scale at comparatively low cost. In addition, plastic filmsand steel have been investigated as potential low-cost substrates. Silicon deposition and solar cellprocessing have to be adjusted to the temperature limit imposed by these substrate materials.

PECVD, IAD, and HWCVD3 are widely used for the deposition of silicon layers at low temperaturesin silicon thin-film solar cell R&D. These techniques are characterized by growth rates in the range ofseveral ten nm/min and the deposited silicon films feature a crystal structure from microcrystalline4 toamorphous. The latter characteristic represents a major drawback of the low-temperature approach,since the minority carrier lifetime in these materials is limited by recombination at grain boundaries.

The application of recrystallization steps allows an enlargement of the grain size and therefore anincrease in bulk diffusion length. However, due to the temperature restriction, the recrystallizationprocess is confined to few low-temperature techniques e.g. solid-phase crystallization [14], aluminum-induced crystallization [15] or laser-beam crystallization [16]. Up to now, no satisfactory results couldbe achieved using these methods and therefore only few routes are still pursued.

The concept of micromorph silicon tandem cells was introduced by the research group at the Institutefor Microelectronics at the University of Neuchâtel [17]. The micromorph tandem structure iscomposed of a high-bandgap amorphous top and a low-bandgap intrinsic microcrystalline bottomlayer, deposited by VHF-PECVD5. Stable solar cell efficiencies of 10.7% and integrated module(24 cm2) efficiencies of 9.8% have been achieved using a 2 µm bottom cell, demonstrating thepotential of this concept [18]. Compared to a-Si:H solar cells, the micromorph tandem cells feature anenhanced stability and the potential for higher efficiencies.

Using a similar concept, the Kaneka research group achieved initial efficiencies of 14.5% for a 1 cm2

solar cell and 12.3% for an integrated solar cell module with an aperture area of 3738 cm2 [19].However, only little details concerning deposition or recrystallization techniques and growth rates aredisclosed.

3 PECVD: Plasma-Enhanced Chemical Vapor Deposition, IAD: Ion-Assisted Deposition, HWCVD: Hot-WireChemical Vapor Deposition. All silicon deposition techniques will be explained in the following chapter.4 The notation of silicon crystal structures is classified according to the grain size: nanocrystalline (nc) with 1-100 nm grain size, microcrystalline (µc) with 100 nm-1 µm grain size, polycrystalline with grain size exceeding1 µm and multicrystalline (mc) with grain size in the mm and cm-range.5 VHF-PECVD: Very High Frequency Plasma-Enhanced Chemical Vapor Deposition.

2.2 Thin Film Concepts 7

2.2.2 High-temperature approachTemperatures up to the melting point of silicon can be applied within the high-temperature approach.This enables the use of fast silicon deposition techniques like APCVD and liquid-phaserecrystallization e.g. by zone-melting, yielding large grain sizes in the mm or even cm-range.Moreover, conventional diffusion and metallization processes are feasible and common silicon solarcell technologies can be used.

The large variety of solar cell concepts in the high-temperature approach can be classified according tothe substrate in use. The need for high temperature stability restricts the choice of potential substratematerials to few candidates like low-cost silicon and high-temperature ceramics.

Using low-cost silicon as substrate material the active silicon base layer can be deposited by epitaxy(epitaxial solar cell) at high temperatures. Potential low-cost silicon materials are e.g. reclaim wafersfrom microelectronic industry or cast metallurgical-grade (MG) silicon wafers. The epitaxial solar cellrepresents a silicon wafer equivalent which can be processed by conventional techniques and cantherefore be directly introduced into standard industrial production lines, making this structure a veryattractive concept. The preparation of epitaxial thin-film solar cells is one of the major subjects of thiswork and is therefore discussed in detail in chapter 6.

Silicon deposition on foreign substrates results in a microcrystalline grain structure and the applicationof recrystallization steps to increase the grain size becomes indispensable. Low-cost substrates ofteninhibit high impurity concentrations and diffusion barriers between substrate and active silicon layerare necessary to prevent a contamination of the base layer. At the same time, the diffusion barrier canact as backside reflector, thereby increasing the optical path length and photocurrent generation. Usingelectrically conductive substrate and barrier layer, a conventional 2-side contact scheme can beapplied. Otherwise, alternative contact designs have to be developed e.g. with both contacts located onthe front side of the cell. The potential of this concept has been demonstrated by the MitsubishiElectric Corporation, where an efficiency of 16.45% could be achieved for a silicon thin-film solar cellbased on a recrystallized silicon layer on SiO2 encapsulated silicon substrate [20].

The main drawbacks of the high-temperature approach is the lack in adequate high throughput silicondeposition reactors and the substrate and barrier layer question.

2.2.3 Transfer techniquesThe general concept of transfer techniques is based on the formation of a high-quality single-crystalsilicon thin-film on a host-substrate by epitaxy, contact and emitter formation on the epitaxial layer,attachment of the epilayer to a mechanically supporting substrate and separation of the device from thehost substrate. To make the transfer technique cost-effective, the host substrate has to be recycled toenable multiple use. Thin silicon films of excellent crystal quality can be prepared by this method andhigh efficiencies have already been demonstrated. Critical issues of this concept are the detachmentprocedure, recycling of the host substrate and the need for high throughput silicon deposition.

The Epilift technique

The Epilift concept has been introduced by the PV research group at The Australian NationalUniversity (ANU). A single-crystal silicon wafer covered with a mesh-like oxide layer is used as hostsubstrate. LPE is applied for silicon deposition and selective epitaxial growth occurs on the exposed


silicon area leading to an epitaxial silicon waffle-grid. Using an interdigitated grid design, solar cellprocessing is carried out with the epilayer still being attached to the substrate. The epilayer is detachedfrom the substrate by laser cutting, wet-chemical etching or by applying a mechanical force. Adetailed description of this method can be found in [21]. Efficiencies of up to 13% have been recentlyreported on a 1 cm2 solar cell [22].

Porous silicon

Several research groups focus on the application of single-crystal substrates with sacrificial porouslayer for thin-film formation. In general, at least two layers of different porosity are formed on thesubstrate surface, with the top and bottom layer featuring low and high porosity respectively. Thermalannealing of the sample under hydrogen leads to a closing of the pores in the top porous layer, whichis subsequently used as substrate for epitaxial deposition of a thin silicon film. After epitaxy, emittercontact formation is accomplished on the epilayer surface, a superstrate (usually glass) is attached tothe surface and separation of the semi-finite device from the host wafer is done via the second, weakporous layer. After lift-off the host substrate can be reused.

Using this approach, the research group at the Bavarian Center of Applied Energy Research (ZAE)introduced the Ψ-process (Ψ: psi for perforated silicon) [23] and the PSI-process (porous silicon) [24].Solar cells based on so-called QMS-layers (quasi-monocrystalline, referring to the structure of the topporous layer) [25], [26] were presented by the Institute of Physical Electronics and the University ofStuttgart leading to efficiencies up to 16.6% for silicon thin-films transferred to glass superstrates [27].Using a similar process route, the Sony Corporation (Japan) reported 12.5% efficiency for siliconfilms transferred to transparent plastic films [28].

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3 Chemical vapor deposition (CVD) of silicon

With the advent of silicon based electronic devices the deposition of siliconlayers became a key technology in microelectronic production.Polycrystalline and especially epitaxial silicon layers are widely used e.g. inbipolar and MOS applications. Silicon thin-film solar cells are based on theuse of a thin active silicon layer for photocurrent generation and thereforethe deposition of silicon films on various substrate materials has alsobecome a major issue in this research area. The silicon depositiontechniques used for photovoltaic applications greatly benefit from theexpertise in microelectronic industry.

An overview on silicon deposition techniques and applications is given inthis chapter. The principles of thermal CVD are explained in more detail interms of transport phenomena and chemical reactions and common reactordesigns for APCVD systems are presented. The chapter closes with atechnical description of the APCVD systems developed at Fraunhofer ISEfor photovoltaic applications.

3.1 Silicon deposition techniquesFor the deposition of silicon a large variety of techniques exists which can be roughly categorized bythe silicon source in use. In liquid-phase epitaxy (LPE) a melt consisting of silicon and a metal solventis used as silicon source. The deposition from vapor phase can be split up in two groups: physicalvapor deposition (PVD) and chemical vapor deposition (CVD). Physical vapor deposition refers totechniques very similar to evaporation where solid silicon is transferred into the gas phase under highvacuum conditions. Solid-source molecular beam epitaxy (MBE) is the most prominent example to bementioned in this context. Chemical vapor deposition denotes deposition processes which are based onchemical reactions with the silicon-containing reactants being supplied by a gaseous source. Commonmethods to activate the chemical reaction are thermal heating of the samples (resistive heating,radiofrequency induction, high-intensity lamps, lasers), plasma and catalytic activation. In plasma-enhanced chemical vapor deposition (PECVD) the activation energy is provided by thermal heatingsupported by plasma making depositions at low temperatures possible.

3.1.1 Liquid Phase Epitaxy (LPE)In silicon liquid-phase epitaxy a metal solvent saturated with silicon is used as silicon source. Solventswhich are typically applied are indium (In) and tin (Sn) or other low-melting metals. Intentionaldoping of the growing layers is achieved by adding suitable dopants like gallium (Ga) for p-type andindium-phosphite (InP) for n-type layers from In melt. For silicon growth the solvent is heated andbrought into contact with silicon bulk material thus producing a silicon saturated melt according to thephase-diagram. When saturation is reached the melt is cooled down resulting in a supersaturation.

3 Chemical vapor deposition (CVD) of silicon10

Silicon samples are introduced into the melt and excessive silicon crystallizes on the free siliconsurface. Starting from temperatures well above 900°C the melt is slowly cooled down at rates in therange of few Kelvin per minute and below. The growth process takes place near thermal equilibriumwith growth rates in the range of 1 µm/min.

For LPE tipping boat or centrifugal systems are traditionally used [29]. Long process cycles and smallwafer size capacity result in low throughput. The necessity for solvent metals of high purity (6N)represents a significant cost factor for this technology. Silicon LPE is mainly used in photovoltaicresearch applications.

3.1.2 Physical Vapor Deposition (PVD)

Molecular Beam Epitaxy (MBE)

Silicon deposition by MBE from a solid source is accomplished by electron beam evaporation ofsilicon in ultra-high vacuum (UHV). Ultra-pure silicon source materials have to be employed to keepthe contamination level of the deposited films on a low level. Layer doping is achieved bycoevaporation of dopant material e.g. aluminum (Al) for p-type and Ga or antimony (Sb) for n-typedoping [30]. Silicon deposition by MBE can be performed in a wide temperature range, from roomtemperature to temperatures well above 500°C. For the growth of device-quality silicon epilayers,sample temperatures exceeding 450-500°C have to be used. Typical growth rates are 0.6-6 nm/min[30].

The most crucial issue in MBE is the necessity for very clean sample surface, reactor and vacuumconditions to grow high quality epilayers. MBE allows a low-temperature deposition of very thin filmson a submicron-scale with sharp transition regions. Applications of MBE include e.g. siliconsubmicron devices, deposition of metal silicides or heteroepitaxy of thick strained SiGe layers on Sisubstrates.

Ion-Assisted Deposition (IAD)

Similar to MBE, solid silicon is evaporated by electron beam evaporation in IAD. About 1-5% of theevaporated silicon atoms are ionized and accelerated onto the substrate. Due to the kinetic energy ofthe ions, the substrates can in principle be maintained at lower temperatures for silicon depositioncompared to MBE. In [31] epitaxial deposition at 525-650°C with growth rates of 0.06-0.3 µm/min arereported. In silicon thin-film solar cell R&D, IAD is used for the deposition of silicon films on low-temperature substrates.

3.1.3 Chemical Vapor Deposition (CVD)

Thermal Chemical Vapor Deposition

Thermal CVD is based on the decomposition of silicon-containing source gases at the heated samplesurface and subsequent incorporation of silicon atoms into the growing film. Thermal CVD can becarried out at different operation regimes depending on process temperature and pressure.

Atmospheric pressure CVD (APCVD) operates at high deposition temperatures up to 1300°C wheredeposition rates up to 10 µm/min can be achieved. Trichlorosilane (SiHCl3, TCS) highly diluted inhydrogen is typically used as silicon source gas. In-situ layer doping is achieved by adding suitable

3.1 Silicon deposition techniques 11

dopant gases, e.g. diborane (B2H6) and phosphine (PH3) diluted in hydrogen for p-type and n-typedoping respectively. APCVD is in favor of epitaxial depositions because the high process temperatureenables an optimal arrangement of deposited atoms in the silicon crystal matrix and crystals withextremely low defect densities can be grown. Typically, silicon epitaxy by APCVD is carried out in atemperature range of 950-1250°C. Compared to other deposition techniques, where high vacuums andtherefore complex pumping systems are necessary, little technological effort is needed for CVD atatmospheric pressure and continuous systems are feasible.

Most APCVD system can also be operated at reduced pressure (RPCVD). The deposition chemistry isidentical to APCVD but the process pressure is reduced to approx. 103–104 Pa. Therefore epitaxialdepositions can be carried out at lower temperatures without deterioration of crystal quality.

Low-pressure CVD (LPCVD) is mainly applied for the deposition of polysilicon layers. Thedeposition of epitaxial silicon is also feasible but not widely used. SiH4 typically serves as siliconsource gas and B2H6 and PH3 as dopants. At deposition temperatures in the range of 580-630°C andlow pressures of 10-100 Pa, polysilicon layers can be grown with deposition rates of 5-20 nm/min[33]. LPCVD is widely used in microelectronic industry for the deposition of polycrystalline siliconand amorphous materials [34].

Ultrahigh-vacuum CVD (UHV-CVD) is operated at still lower pressures than LPCVD (10-1-10-3 Pa).A load-lock is necessary and turbo-molecular pumps are essential to reach the required vacuum. Ultra-clean process conditions are mandatory to enable epitaxial layer growth. Compared to LPCVD thediffusivity of molecules is increased and depositions are possible at low temperatures, down to 550°C[34]. Similar to MBE, UHV-CVD allows an accurately controlled deposition of high quality, thin Siand SiGe epitaxial layers with extremely sharp transitions.

Plasma-Enhanced Chemical Vapor Deposition (PECVD)

PECVD is based on the dissociation of a silicon source gas in a plasma and subsequent deposition on aheated substrate. Radio frequency (RF) power in the MHz range is commonly used as excitationsource. Sample temperatures below 400°C are feasible which enables the processing of temperaturesensitive samples at low thermal budget. The operating pressures range from 10-0.1 Pa and typicallysilane (SiH4) is used as silicon source gas. Silicon epilayers may be grown but at lower qualitycompared to thermal CVD because of the reduced deposition temperature.

PECVD allows the deposition of a large variety of materials with different properties. It is widely usedfor the deposition of dielectric layers, hydrogenated microcrystalline (µc-Si:H) and amorphous (a-Si:H) silicon films.

Hot-Wire CVD (HWCVD)

In hot-wire or thermocatalytic (Cat) CVD SiH4 is decomposed by a catalyst, usually a heated tungstenor tantalum wire in a low pressure ambient. During the deposition the substrate temperature is held at aconstant level in the range of 200-500°C. Amorphous and microcrystalline silicon layers can bedeposited at rates up to 300 nm/min and 60 nm/min respectively.

HWCVD has raised increasing interest in the past decade because this method allows the deposition ofsilicon films with improved electrical stability and at higher growth rates compared to PECVD.


Applications in thin-film solar cells and thin-film transistors (TFTs) are currently under investigation[32].

3.1.4 Overview on deposition techniques and applicationsThe demand for a controlled deposition of epitaxial and polycrystalline silicon layers emerged fromVLSI technology and applications. In microelectronic industry the focus for e.g. silicon epilayers is onperfect crystallinity, sharp doping transitions as well as thickness and doping uniformity. Sophisticateddeposition techniques have been developed and optimized to accomplish these requirements. Todaysilicon deposition by CVD is state-of-the-art for all epitaxy processes used in microelectronicproduction. With the ever decreasing size of microelectronic devices and novel device designs, today’sresearch activities focus on industrial feasible technologies for very thin epilayers deposited at lowtemperatures.

Silicon deposition technologies have also become an important tool in silicon thin-film solar cell R&Dfor the formation of thin active base layers. Depending on the solar cell structure and especially on thesubstrate-type (see section 2.2) different silicon deposition techniques are applied. Similar tomicroelectronic devices the deposition technique is chosen according to the maximum temperaturetolerable for device fabrication.

T [°C] Rate[µm/min]

Si-source Si-film Ref. Applications

Liquid Source (LPE)

LPE 950 0.1...1 In solvent Epi-Si [35]

RLPE6 930 2...4 In solvent Epi-Si [36]Epi-lift, epitaxial thin-film solar cells

Solid Source (PVD)

MBE >300 0.06...0.12 Solid Si Epi-Si [30] Submicron epitaxial silicon films

IAD 525...650 0.06...0.3 Solid Si Epi-Si [31] Silicon thin-film solar cells on glass, Ψ-process

Vapor Source (CVD)

LPCVD 550...750 0.2 SiH4 Poly-Si [37] Sensors, diodes, transistors, gate electrode in MOSdevices, emitter/base contacts in bipolar devices

900...1050 0.1...0.8 SiH2Cl2 Epi-Si [38], [39] Epitaxial thin-film solar cells

APCVD 1170 6...10 SiHCl3 Epi-Si This work

1000...1200 3...6 SiHCl3 Epi-Si [40]

950...1050 1...3 SiHCl3 Epi-Si [41]

Epitaxial thin-film solar cells, Thin-film solar cellson foreign substrates, QMS and PSI process,bipolar and MOS esp. CMOS applications

PECVD 150...450 0.006...0.018 SiH4, SiF4 µc-Si:H, a-Si:H [42]

VHF-PECVD

250 0.3 SiH4 µc-Si:H [43]

HWCVD 250...500 0.06...0.3 SiH4 µc-Si:H, a-Si:H [44]

a-Si:H solar cells, micromorph tandem solar cells,sensors, thin film transistors

Table 3.1: Overview on silicon deposition techniques and applications.

6 RLPE: Rapid LPE.

3.2 Deposition principle of silicon by thermal CVD 13

Table 3.1 gives an overview on the most commonly used silicon deposition techniques and mainapplications with emphasis on silicon solar cell R&D.

3.2 Deposition principle of silicon by thermal CVDThe deposition of microcrystalline and epitaxial silicon layers by APCVD for silicon thin-film solarcells is the major subject of this work. This section aims to give an insight on the principles of silicondeposition by thermal CVD with main focus on TCS as silicon source gas.

In order to predict deposition rates for a given reactor setup and therefore to optimize processparameters and reactor geometry, adequate growth rate models reflecting real conditions are needed.However, the description of the silicon growth process in CVD is a complex issue where gas transportphenomena have to be coupled to chemical reactions on the substrate surface and in the gas phase. Ageneral model describing the entire deposition process involves the solution of many coupled partialdifferential equations. Because of the large complexity of the problem many authors restrictthemselves to a simplified modeling of specific operating regimes e.g. by neglecting gas flowdynamics. The development of improved models and simulation tools is still a current topic ofresearch [45], [46], [47].

3.2.1 TransportThe transport phenomena in fluid dynamics are generally described by simultaneously solving thebasic equations for conservation of total mass, momentum, energy and chemical species in threedimensions with the process gas assumed to obey the ideal gas law and further assuming adequateboundary conditions [48], [49]. Neglecting all chemical reactions and temperature fields the transport-problem can be numerically solved for different reactor geometry. Taking into account radiationtransport and temperature fields the problem is getting more complex due to the temperaturedependence of most physical parameters (e.g. heat capacity, thermal diffusivity, gas density, viscosityetc.) determining the mass transport. The main effect on transport phenomena when chemicalreactions are included is the local change in gas composition and therefore the change in all otherparameters depending on this variable. Transport and reaction kinetics influence each other and aclosed solution of the entire deposition problem can only be obtained if both phenomena are accountedfor.

For a more qualitative description of gas flow dynamics and to allow for an easy determination of therelevance of different transport phenomena without computational methods, dimensionless numbers(e.g. Reynolds, Damkoler, Peclet, Grashof numbers) have been introduced [50]. These numbers can becalculated from reactor geometry, gas phase composition and properties and depending on their value,conclusions about the gas transport behavior in the CVD reactor can be drawn.

3.2.2 Thermal equilibrium conditionsSilicon CVD is traditionally based on the deposition from process gases composed of a siliconprecursor and hydrogen carrier gas. In thermodynamic equilibrium the partial pressures of all speciespresent in a gas mixture can be calculated using the Law of Mass Action. Considering e.g. a chemicalreaction of two species A and B reacting to species C and D:


dDcCbBaA +↔+ (3.1)

where the lower letters denote the stoichiometry constants. If the system is in equilibrium at a giventemperature and pressure, then the value of

ba

dc

BADCTK

][][][][)( = (3.2)

is constant. The values in square brackets correspond to the concentration of each specie and Kdenotes the equilibrium constant. Assuming an ideal gas the concentrations can be replaced by thecorresponding partial pressure of each gas component. Calculation of the standard free energychange ∆G0 allows to predict whether a reaction will occur or not:

KRTG ln0 −=∆ (3.3)

where R and T denote the gas-constant7 and temperature respectively. The free energy change can beobtained from the standard state Gibbs free energies of formation which are listed in the JANAF tables[51]. For ∆G0<0 the reaction under consideration occurs spontaneously, while in thermal equilibriumthe change in standard free energy is zero. For a system containing several gas species the equilibriumcomposition can therefore be determined as a function of temperature if all possible chemical reactionsand their equilibrium constants or Gibbs free energy changes are known. To calculate the partialpressures the free energy of the system has to be minimized [52].

The gas phase composition of a Si-H-Cl-system under atmospheric pressure was calculated atthermodynamic equilibrium using a software package [53] which refers to the JANAF tables. InFigure 3.1 the results are shown for two different Cl/H-ratios8 with temperatures varied between700°C and 1300°C.

In commercial APCVD reactors Cl/H-ratios below 0.1 are typically applied, represented by the graphon the left-hand-side in Figure 3.1. In Figure 3.1 (right) the process conditions are set according to thestandard epitaxy process used for the RTCVD100 reactor built at Fraunhofer ISE (see section 3.4.2).

Considering the gas phase composition at low temperatures, SiHCl3 and SiCl4 dominate the gascomposition for both process conditions. At high temperatures HCl and SiCl2 are the most abundantspecies. For low Cl/H-ratios and temperatures above 1100°C SiCl2 is clearly the dominating siliconcontaining compound whereas different silicon chlorides with similar mole fractions are present forhigh Cl/H-ratios at elevated temperatures.

CVD does not occur at thermal equilibrium conditions and therefore the presented calculations do notrepresent the actual conditions in the CVD reactor. Nonetheless, some general information on possibleeffects of temperature on the gas phase composition can be drawn from these calculations.

7 Universal gas constant R=8.315 Jmol-1K-1.8 The Cl/H-ratio denotes the ratio of chlorine to hydrogen atoms in the gas phase. This ratio is constantthroughout the deposition process since neither chlorine nor hydrogen are consumed or produced. Growth-related phenomena often do not depend on gas flow rates but on the gas phase composition and the specificationof the Cl/H-ratio to characterize the deposition conditions is more convenient.


800 900 1000 1100 120010-5

10-4

10-3

10-2

10-1

100

Cl/H = 0.045

HCl

SiCl3SiCl4

SiHCl3

SiCl2

SiH3Cl

SiH2Cl2

H2

Mol

e fra

ctio

n

Temperature [°C]800 900 1000 1100 1200

10-5

10-4

10-3

10-2

10-1

100

Cl/H = 0.43

SiH3Cl

SiH2Cl2

SiCl4SiHCl3

SiCl3

SiCl2

H2

HCl

Mol

e fra

ctio

nTemperature [°C]

Figure 3.1: Equilibrium gas phase composition for a Si-H-Cl-system as a function of temperaturefor a total pressure of 1 atm calculated for different Cl/H ratios.

3.2.3 Reaction kineticsFigure 3.2 shows a simplified schematic model for silicon deposition from the gas phase. First, theprecursor has to be transported from the main gas stream to the wafer surface (1). On the substratesurface, the precursor is adsorbed (2) and decomposed into a silicon adatom and reaction byproducts.While the silicon atom migrates on the substrate surface and is finally incorporated into the siliconcrystal on an energetically favorable site (3), the byproducts are desorbed from the substrate surface(4). In addition to the deposition process, reactions in the gas phase can occur leading to particlegeneration, or the adsorbed silicon precursor molecule may be desorbed from the surface withoutbeing decomposed. Using chlorine containing silicon precursor gases, silicon etching by HCl is animportant chemical side reaction. Hydrogen acts as a catalyst for the chemical decomposition process.

The growth rate is determined by the supply of reactants and the velocity of the chemical reactionsleading to the decomposition of the silicon precursor on the substrate surface. As already pointed out,both parameters depend on each other. Nonetheless some general statements on the temperaturedependence of the growth rate can be made.


Main gas stream

SiSi

Si

Si

Byproducts1

2

4

3

Sample

surfa

ce

Figure 3.2: Simplified schematic of silicon deposition from a gaseous silicon source.

Growth rate dependence on temperature

For thermally activated reactions, the reaction rate mostly increases with rising temperature and thedependence of the reaction rate constant from temperature can be described by an Arrhenius function(assuming constant reactant concentrations and pressure) [37]:

)exp(Tk

EAkB

A−= (3.4)

Where k, A, EA, kB and T denote the reaction rate constant, collisional frequency, activation energy,Botzmann’s constant and temperature.

An Arrhenius plot based on experimental values can give information on the activation energy and onchanges in reaction mechanisms determining the reaction rate. Figure 3.3 shows a typical Arrheniusplot for CVD at constant pressure.

1/T

surface reaction limited

mass transport limited

Slope= -EA/kB

ln (g

row

th ra

te)

Figure 3.3: Arrhenius plot for silicon CVD.


Two growth regimes are apparent: at low temperatures (surface reaction limited or kineticallycontrolled regime), the reaction rate is limited by chemical kinetics and small deviations intemperature result in large changes in growth rate. The slope of the Arrhenius curve gives theactivation energy of the dominating chemical reaction. Within this growth regime, the deposition ofuniform films requires a highly uniform temperature distribution in the reactor. At higher temperatures(mass transport limited or diffusion-controlled regime), the reaction rate shows only a weakdependence on temperature and small deviations in temperature have only little effect on the growthrate. The high temperature enables fast chemical reactions while the reactant supply is constrained bythe feed rate, the transport from main gas stream to reaction site or desorption rate of byproducts. Inthis case, a homogeneous gas distribution is necessary to grow films of high uniformity.

Modeling of silicon growth rate in a SiHCl3-H2-system

Apart from temperature, the gas phase composition (or silicon precursor partial pressure) and the totalpressure also influence the deposition rate. In [48] a theoretical growth model is presented andexperimentally verified for a silicon deposition process based on the decomposition of TCS in ahorizontal atmospheric pressure reactor at high temperatures. Because of the close relation to the CVDprocess used within this work, the approach by Habuka is discussed in this section to illustrate thedependence of growth rate on temperature and gas phase composition.

In [48] a 3-dimensional growth model is applied, including transport phenomena as well as chemicalsurface reactions. The transport equations are solved using the simulation program FLUENT. Thechemical reaction leading to silicon deposition is assumed as a two-step reaction. SiHCl3 moleculesimpinging on the substrate surface are chemisorbed to yield SiCl2 and HCl. While the SiCl2 isadsorbed on the substrate surface (denoted by the asterisk) the HCl is released into the gas phase:

↑+→ HClSiClSiHCl *23 (3.5)

Upon adsorption, the SiCl2 is decomposed by hydrogen to yield solid Si, which is incorporated into thecrystal, and gaseous HCl according to the following equation:

↑+→+ HClSiHSiCl solid 22*2 (3.6)

In a simplified form the overall chemical reaction can be described by:

HClSiHSiHCl 323 +→+ (3.7)

In addition, an etching process of solid silicon by HCl and desorption of SiCl2 from the surface isassumed to occur but not taken into account for growth rate modeling. Gas phase reactions are alsoignored. The reaction rate for process (3.5) is assumed to depend on the concentration of TCS at thereaction site and the amount of free surface sites available for an occupation by SiCl2:

])[1( 3SiHClkV adad Θ−= (3.8)

Vad, kad, Θ and [SiHCl3] denote the mole chemisorption rate, rate constant for chemisorption, fractionof occupied reaction sites and TCS-concentration respectively. Similarly, the reaction rate for process(3.6) depends on the hydrogen concentration and the amount of surface sites occupied by SiCl2:

][ 2HkV r Θ= (3.9)


where V is the mole growth rate and kr is the rate constant for the decomposition process. Bothreaction rate constants are assumed to depend on temperature through an Arrhenius function.

In a steady state, the change in free surface sites is equal to zero and the fraction of occupied surfacesites can be expressed as a function of TCS and hydrogen concentration and the reaction rate constantskad and kr. Combined with eqn. (3.9) an expression for the growth rate can be deduced:

]][[]][[][][ 2323

23

HSiHClkHSiHClHkSiHClk

kkV

rad

adr =+

= (3.10)

In this equation, k denotes the reaction rate constant of the overall reaction leading to silicondeposition. From experimental values, the overall rate constant k and subsequently the reaction rateconstants kad and kr are derived.

Figure 3.4 illustrates the effect of temperature and Cl/H-ratio on the growth rate, calculated accordingto eqn. (3.10).

0.05 0.10 0.15 0.200

2

4

6

8

1050°C

1000°C

1100°C

1150°C

Gro

wth

rate

[µm

/min

]

Cl/H-ratio

Figure 3.4: Growth rate depending on temperature and Cl/H-ratio calculated according toeqn. (3.10).

Depending on the Cl/H-ratio the growth rate features three regimes. At Cl/H-ratios below 0.5% thegrowth rate increases strongly with rising Cl/H-ratio. Small changes in gas-composition result in largechanges in growth rate. With further increase of the Cl/H-ratio a saturation is reached, where thegrowth rate changes only little with Cl/H-ratio and finally the growth rate even decreases withincreasing Cl/H-ratio. In this regime the growth rate is comparatively insensitive to the Cl/H-ratio.

Operation at high temperatures enables the chemical reactions of adsorption and decomposition tooccur very fast. The overall reaction rate for silicon deposition is high and for low Cl/H-ratios thegrowth rate is limited by the chemisorption process. Providing a larger concentration of TCSconsequently results in an increase in growth rate. However, if the Cl/H-ratio exceeds a certain value,the growth rate starts do decrease again. In this regime the reaction rate is limited by thedecomposition process: sufficient silicon precursor gas is provided to enable large adsorption and


growth rates but the chemical decomposition of the adsorbed species is hindered by the lack ofhydrogen.

The validity of the presented model was proved by Habuka in a wide temperature range of 800-1120°C and gas-compositions with molecular weights between 2.7x10-3 and 11x10-3 kg/mol, coveringthe operation regimes typically used for industrial APCVD processes.

In [54] a similar model is presented to describe the growth rate in a horizontal single-wafer reactorwith TCS as precursor gas. The predicted growth rates were also successfully verified by experiments.

3.2.4 Chemical yieldThe chemical yield denotes the conversion efficiency of silicon contained in the initial gas phase intosolid silicon. Comparing the initial Si/Cl-ratio to the final Si/Cl-ratio at deposition temperature underthermal equilibrium gives information about the amount of TCS which is theoretically consumed inreactions leading to silicon deposition. Using TCS as precursor gas the initial Si/Cl-ratio is 0.33. If thefinal Si/Cl-ratio exceeds this value, etching of silicon dominated the process instead of deposition. ForSi/Cl-ratios lower than 0.33 silicon deposition has occurred. The final Si/Cl-ratio depends on processtemperature and initial gas composition i.e. Cl/H-ratio.

The chemical yield can be defined by initial and final Si/Cl-ratio according to

i

fSi ClSi

ClSi)/()/(

1−=η (3.11)

Assuming thermal equilibrium, the silicon conversion efficiency can be calculated from the partialpressures of silicon and chlorine containing species as a function of temperature and Cl/H-ratio. In[40] the effect of temperature and Cl/H-ratio on the chemical yield has been evaluated by means ofthermal equilibrium calculations. The results are depicted in Figure 3.5.

0.65 0.70 0.75 0.80 0.85

30

40

50

60

70

80

90

0.08

0.03

0.06

Cl/H

0.04

0.01

0.001

0.1

0.005

η Si [%

]

103/T [°K]

1300 1200 1100 1000 900T [°C]

0.00 0.02 0.04 0.06 0.08 0.10

30

40

50

60

70

80

90 T= 900 °C T=1000 °C T=1100 °C T=1150 °C T=1200 °C T=1250 °C T=1300 °C

T=1300°C

T=900°C

η Si [%

]

Cl/H

Figure 3.5: Dependence of chemical yield on temperature and Cl/H-ratio in thermal equilibrium[40].

The Cl/H-ratio determines the maximum conversion efficiency, which can be reached. The lower theCl/H-ratio the larger is the chemical yield at a given temperature. With increasing temperature the


conversion efficiency rises due to the enhanced reactivity. The largest conversion efficiencies can beachieved at high process temperatures and low Cl/H-ratios.

3.3 Reactor design for APCVDWithin this work a thermal APCVD reactor constructed and built at Fraunhofer ISE has been used forsilicon deposition. Before describing the deposition systems at Fraunhofer ISE in more detail anoverview on the most common commercial APCVD system is given in this section. An extensivedescription of reactor configurations and CVD equipment is published e.g. in [55] and [56].

In the early sixties, the first stages of silicon deposition technology, vertical (a) and horizontal (b)reactors were widely used. In a horizontal reactor the samples are mounted on a horizontal susceptorand loaded into a quartz tube. The process gas enters on one side of the reactor tube and exits from theother side. Upon passing the heated sample surface, deposition occurs from the silicon containing gasphase. The susceptor is slightly tilted to reduce gas depletion effects. In a vertical setup the gas inlet islocated at the top with the gas flowing downwards.

Nowadays barrel reactors (c) are the workhorses for silicon epitaxy in microelectronic production. TheSiC-coated graphite susceptor used in a barrel reactor has a shape similar to a truncated frustum of a 5-or 6-sided pyramid. The samples are tilted to an angle of 2°-3° from the vertical to reduce particleimpinging on the surface and to compensate for depletion effects. A quartz bell surrounds the barreland banks of halogen lamps are used for heating. The process gas is injected in the top part of thereactor and upon flowing downwards, deposition occurs. A slow rotation of the barrel increasesthickness uniformity.

A flat, rotating susceptor is used in the pancake reactor (d). This reactor configuration is known tosuffer from inhomogeneities in the gas extraction system and their susceptibility to particlecontamination. Pancake reactors are mainly used for small diameter wafers.

Figure 3.6: APCVD deposition reactors [37].

3.4 APCVD at Fraunhofer ISE 21

3.4 APCVD at Fraunhofer ISEAt Fraunhofer ISE research activities on crystalline silicon thin-film solar cells have been a majorsubject since years. The demand for a silicon deposition system adapted to the needs of silicon thin-film solar cell processing and production led to the development and construction of new CVD-systems different from commercial tools. The RTCVD100 reactor was the first apparatus built in thiscontext at Fraunhofer ISE. After years of reliable operation a more sophisticated system was set up,the RTCVD160. The newest stage of development is represented by a continuous system (ConCVD)which was set up in autumn 2002.

3.4.1 Reactor designThe development of a silicon deposition reactor ready to meet the demands for a future integration insilicon thin-film solar cell production was the basic motivation for the research activities started atFraunhofer ISE in this area. The criteria the new deposition reactor had to fulfill can be summarized asfollows:

• high throughput (5-10 m2/h)

• high growth rates (≥5 µm/min)

• simple setup with little technological effort

• processing of rectangular or square wafers

• sufficient layer quality (diffusion length in epitaxial layers exceeding 2-3 times layer thickness)

• controllable doping profiles

• high chemical yield (>30%).

From all deposition methods presented in section 3.1 APCVD at high temperatures is the methodcapable to meet most of these demands. In microelectronic industry CVD is the key technology whichis commonly used for silicon epitaxial deposition. In this area, excellent crystallographic quality,thickness and doping uniformity in the 2% range and high purity are absolutely necessary [54]. Batch-type systems (barrel reactors) or single-wafer reactors are traditionally used and operation at high gasflow rates enables to achieve the required thickness and doping homogeneity, however at the expenseof low chemical yield and therefore at high cost per m2. Regarding the total cost for the entireprocessed microelectronic device, silicon deposition makes up only a small fraction even if cost-intensive deposition techniques are used. From this point of view, the development of high-throughput, low-cost silicon deposition reactors is of no interest. In contrast to that, the silicondeposition process constitutes a large fraction of the final cost for a silicon thin-film solar cell makingthe development of a cost-effective silicon deposition reactor an important subject of research.

Out of these preliminary settings the first CVD system was developed and built at Fraunhofer ISEwhich was expected to be capable to fulfill most of the imposed requirements.

At present three CVD systems are set up at Fraunhofer ISE representing the progress made in thedevelopment on these reactors within the past five years. The deposition principle is based on thermalCVD with trichlorosilane as precursor and hydrogen as carrier gas. In contrast to today’s commercialsystems, the design of the first ISE CVD-reactor is more comparable to the early horizontal reactorswhere a horizontal carrier loaded with wafers is introduced into a quartz tube. An outstanding feature


of the ISE reactors is the setup of the wafers which will be discussed in more detail in the followingsection. Thermal heating of the samples is achieved by lamp fields thus enabling rapid heating andcooling rates, quick temperature response and therefore low thermal budget. Since these elements havebeen transferred from Rapid Thermal Processing (RTP) technology the reactors were named RTCVDreactors. All deposition processes are computer controlled.

Since process development and optimization in the RTCVD100 reactor is one of the major subjects ofthis work, the technological aspects of this system are described in detail. The successor reactormodels (RTCVD160 and ConCVD) are also presented with main focus on the technical improvementsmade compared to the RTCVD100.

3.4.2 RTCVD100The RTCVD100 is the first laboratory CVD reactor which has been developed and built at FraunhoferISE. Until today a total of 1400 deposition runs have been carried out in this system which proved tobe reliable and reproducible in operation. In this section the technical details of the reactor arepresented, while deposition characteristics and process optimization are discussed in the followingchapter.

Figure 3.7 shows a picture (right) of the entire RTCVD100 system and a picture (left, top) andcorresponding schematic (left, bottom) of the reactor. The entire unit consists of the reactor withfurnace and quartz tube, the gas system and the control unit. All components except control unit aremounted on a single aluminum frame which is horizontally divided into two parts. The upper partforms a closed system with the furnace and the quartz tube inside. The lower half contains electricpower supply, thyristors and a separate casing for the TCS gas cylinder.

The water-cooled furnace is constructed of anodised aluminium with the interior walls clad with ahighly reflective, adhesive film (reflectance approx. 98%). Temperature sensors are integrated into thefurnace to prevent the system from over-heating. The horizontal quartz tube passes through circularopenings in the front and back walls. Tubes with a diameter of 100 mm are used, giving the reactor itsname. The top of the furnace houses a bank of 6 tungsten-halogen lamps each with 4.5 kW nominalelectrical power for radiative heating. The optical heating allows for fast heating and cooling rampsand therefore short process cycles. Several deposition runs can be carried out per day enabling aflexible variation of process conditions.

The gas system is made from electro-polished stainless steel. The valves are pneumatically operatedand controlled by electrical pilot valves. Available process gases are nitrogen to purge the reactor,hydrogen for carrier gas and for purging, trichlorosilane as silicon precursor, diborane at 2500 ppmdiluted in hydrogen for p-type boron doping and hydrochloric acid (HCl) for in-situ sample etchingand reactor cleaning. Trichlorosilane is a liquid at room temperature and therefore a bubbler system isused with a Source V vaporizer-unit to control the gas flow. The impurity level in hydrogen andnitrogen is specified below 1 ppm and the applied TCS is of semiconductor quality.

A palladium membrane cleaning-system for hydrogen is installed to minimize the oxygenconcentration in the hydrogen gas. The moisture content in hydrogen is monitored by an additionalsensor down to the ppbv (parts per billion volume) range and a particle-filter is implemented in the gasline right before entering the reactor.


The process gases are mixed before entering the reactor tube via a flange. Additional hydrogen ornitrogen can be introduced by a separate gas line, also via the flange. Exhaust gases leave the systemthrough one single gas line leading to a water-scrubber where they are washed out.

Figure 3.7: Left: Picture (top) and corresponding schematic (bottom) of the RTCVD100 reactor.Right: Entire RTCVD100 system with controlling units, TCS casing and reactorhousing. The gas system is located on the rear side and is therefore not visible in thepicture.

Process control is realized by a personal computer and a programmable logic controller. Individualdeposition programs can be set up by a special software, the programs are downloaded to thecontroller unit and executed. Process parameters like temperature and gas flows are monitored andrecorded during the whole process.

Wafer setup

The positioning of the wafers inside the reactor and the geometry of the gas inlet strongly influencesthe deposition characteristics. The wafer setup developed for the RTCVD100 is illustrated in Figure3.8. Two horizontal parallel wafer rows and the quartz carrier form a closed reaction volume intowhich the process gases are introduced during the deposition process. The side walls are formed by thefront and back plate of the carrier, the right and left edge rods of the carrier and the substratesthemselves. This avoids parasitic depositions on the walls of the outer quartz tube and minimizes theneed for a frequent cleaning of the tube. High chemical yields can be achieved since deposition takesplace only on wafer substrates and the walls of the carrier. In order to prevent the process gas from


leaving the reaction volume (e.g. through small gaps between the samples), a slight over-pressurebetween the outside and the inside of the carrier is created by narrowing the gas outlet to the outside.The maximum wafer size is limited to a width of 80 mm.

Gas inlet

Exhaust funnel

Top wafer row

Bottom wafer row

Quartz rods

Figure 3.8: Schematic drawing of wafer carrier used for the RTCVD100.

The arrangement of the wafers in relation to the lamp array is asymmetric: the top wafer row isdirectly heated by the halogen-lamps whereas the bottom wafer row is only heated by thermalradiation of the upper wafers and reflected light from the surrounding furnace (Figure 3.7, left,bottom). A temperature-drop of about 50K from top to bottom is the consequence making asimultaneous process optimization for both wafer rows impossible [40]. In this work the depositionprocesses were optimized for the top wafer row due to the higher temperature and therefore depositionrate on this site. In addition, the danger of particles falling down on the surface of the wafers isexcluded.

For gas inlet, a simple quartz tube with round inlet cross section is usually used. To improve the gasdistribution, experiments were carried out using a nozzle made out of quartz.

Temperature distribution

Gas and temperature distribution are the two governing parameters determining the local depositionrate inside the reactor. The temperature affects both, gas transport and chemical reaction kinetics.

The temperature distribution inside the reactor is predefined by the dimensions of the lamp arraywhich is 250 mm long and 120 mm wide. According to this rectangular geometry a temperaturedistribution profile is expected with a maximum in the middle and decreasing temperature to theboundaries. The injection of gas into the system results in a cooling of the samples where the gaspasses, with the cooling being stronger the larger the heat capacity or the total gas flow rate. In [40]temperature profiles were measured in longitudinal direction with two different hydrogen gas flowsapplied. The measurement was done by moving a thermocouple in 10 mm steps between the twowafer rows and recording the temperature.

As expected the maximum temperature was reached in the middle of the furnace. For a low hydrogengas flow rate of 0.5 sl/min a temperature-drop of approximately 100K was determined over the


250 mm length of the lamp-field compared to a decrease of almost 270K across the entire length of thesubstrate carrier (430 mm). An increase in total gas flow rate results in a cooling of the gas injectionregion and a shift of the maximum temperature in gas flow direction.

Figure 3.9 shows two temperature profiles measured in longitudinal direction along the centerline ofthe furnace for different temperature set-points. For this experiment, the set-point were measured andcontrolled by a pyrometer, located 50 mm in upstream direction relative to the center of the lamp-field.A medium hydrogen gas flow rate of 3.2 sl/min was applied.

Across the entire length of the lamp field, the temperature drops from the center to the edges by 120Kand 110K for the high and low temperature respectively. Within a length of 100 mm in the center ofthe lamp field the temperature variation is determined to 2% in both cases.

-150 -100 -50 0 50 100 150600

700

800

900

1000

1100

1200

1300

Temperature set point 1170°C 950°C

Gas flow

Tem

pera

ture

[°C

]

Distance from the center of the lamp field [mm]

Lamps

Wafers

Figure 3.9: Temperature profile measured by a thermocouple in gas flow direction for two differentset-point temperatures.

During the deposition the process temperature is recorded by a thermocouple located between the tworows of samples within the reaction volume. The soldered spot of the thermocouple (position, wherethe temperature is measured) is located in the back end zone of the substrate carrier in order to preventany impact on the gas flow and therefore the deposition rate.

In general, the measured temperature does not correspond to the absolute temperature of the wafers,but represents an average value depending on the exact position of measurement inside the reactor.The relation between the measured mean temperature and the absolute maximum temperature of thewafers in the middle of the reactor was determined by comparison with pyrometric measurementswhich were carried out in earlier experiments. For the setup currently used, the difference betweenabsolute maximum value and measured temperature comes up to approximately 100K. In thefollowing all temperature values refer to this absolute maximum temperature.


Process cycle

For epitaxial silicon deposition we follow a typical APCVD process [57]. Figure 3.10 illustrates thetemperature and gas flow characteristics for a complete process sequence. The individual process stepsare denoted by number 1-6 and are explained in the following.

In the standby mode the reactor is permanently purged with nitrogen. After the sample carrier isloaded the system further remains in the standby mode for 20 min before the deposition process starts.During this period, air which might have diffused into the system during the insertion of the carrier, isremoved by the nitrogen purge gas flow. In the first step of the process sequence (1) the purge gas isswitched from nitrogen to hydrogen to create an inert atmosphere inside the reactor. Then the systemis heated up with a ramp of 150K/min until the prebake temperature is reached (2). The in-situhydrogen prebake is typically implemented to remove the native oxide from the sample and thus togenerate a clean surface for epitaxial deposition [34]. For the RTCVD100 a 1 min prebake is appliedat a temperature identical to the deposition temperature of 1170°C (3). During the prebake, the processgases trichlorosilane, hydrogen and diborane are stabilized into the exhaust. The actual deposition stepstarts with the injection of the stabilized process gases into the reaction volume (4). The depositiontime is adjusted to the thickness of the silicon layer to be grown. After deposition the process gases areswitched off and the reaction volume is again purged with hydrogen to remove any remnants of theprocess gas. An annealing step at a slightly higher temperature is included (5). In the last step, thesystem is cooled down to 400°C (6) before the heating is completely turned off (END) and the systemreturns to the standby mode.

0

2

4

6

8

10

0 10 20 30 40 50

0

2

0

200

400

600

800

1000

1200

1400

Process gas H2 SiHCl3+B2H6

Gas

flow

[l/m

in]

N2

Time [min]

6

543

2

1

END

START

Dep

ositi

on

Stan

dby

Stan

dby

Tem

pera

ture

[°C

]

Figure 3.10: Temperature and gas flow characteristics of a typical epitaxy process cycle as appliedfor the RTCVD100 reactor.


The deposition of silicon on samples with SiO2 encapsulation is usually carried out at lowertemperatures, to prevent a damage of the oxide layer by hydrogen etching. In this case the hydrogenprebake is also omitted.

3.4.3 RTCVD160The RTCVD160 represents an up-scaled version of the RTCVD100 reactor featuring larger wafer sizecapability, higher throughput and increased chemical efficiency [58]. The optical heating system wasenlarged and modified to two vertically mounted arrays 400 mm in length and 250 mm in height. Eacharray houses 30 linear halogen lamps of 4.5 kW maximum electrical power. The vertical arrangementof the lamps and their control by thyristor units enables the realization of power and thereforetemperature profiles in longitudinal direction.

The principle of the wafer setup presented in section 3.4.2 was maintained but instead of a horizontalpositioning of the wafers a vertical configuration is now used. Figure 3.11 shows the quartz carrierdeveloped for the RTCVD160. Samples of up to 100 mm in width can be mounted in two verticalrows up to a total length of 500 mm. The process gas is first introduced into the gas conditioning zonefor homogenizing the gas flow, and then enters the deposition zone, where gas decomposition andsilicon deposition occurs at a length of approximately 300 mm. A simple modification of the quartzcarrier enables the processing of larger substrates of up to 125 mm in width.

Gas conditioning

Deposition zone

Adapter plates

Exhaust funnel

Gas inlet

Quartz rods

Exhaust zone

Figure 3.11: Quartz sample carrier developed for the RTCVD160.

Both sample rows can be utilized due to the completely symmetric arrangement of wafer rows andlamp arrays. Assuming a length of 300 mm for the deposition zone, 6 wafers of 100x100 mm2 in sizecan be processed per run.

The gas system is adapted to the larger deposition area and additional components have beenimplemented to improve process flexibility. A maximum diborane flow rate of 1000 sccm/min can beemployed and a phosphine (PH3) gas line is built in to enable the deposition of n-type layers. The lastmajor improvement to be mentioned is the extended version of the control software where an arbitrarynumber and sequence of process steps can now be defined by the user.


In Table 3.2 the main features of the RTCVD100 and RTCVD160 reactors are summarized forcomparison.

RTCVD 100 RTCVD 160Reactor tube Ø [mm] 100 160Wafer setup Horizontal VerticalMax. wafer width [mm] 80 125Max. deposition area [cm²] 430 1000

Heating system1 lamp-field

Upper wafer row directly heated2 lamp-fields

Both wafer rows directly heated20 TCS [g/min] 405 H2i [sl/min] 10

10 H2a [sl/min] 1050 B2H6 [sccm/min] 10002 HCl [sl/min] 2

Process gases andmaximum flow rates

- PH3 [sccm/min] 100Effective dep. area [cm²] 50 600

Table 3.2: Specifications of two atmospheric pressure CVD reactors developed and built atFraunhofer ISE.

While the RTCVD100 was used to investigate the potential of the reactor concept, and is clearlylimited in throughput and process flexibility, the RTCVD160 is a powerful tool for laboratory-typesilicon deposition. It represents an important step in the development from the purely lab-typeRTCVD100 to a large-area continuous silicon deposition reactor which can be implemented inindustrial production.

More than 100 runs have already been carried out in the RTCVD160 proving its reliable operation andverifying the concept of the reactor system. At present a first optimization cycle for silicon depositionon foreign substrates is completed and characterization of epitaxial processes is under investigation.

3.4.4 Continuous CVD (ConCVD)In industrial production, continuous atmospheric pressure CVD is routinely used for the deposition ofSiO2 layers at low temperatures [59]. Moving-belt systems are employed with nitrogen gas curtains atentrance and exit and sophisticated gas injection systems are implemented in the deposition zone foroptimal thickness homogeneity. Only little technological effort is required to operate these systemssince no pumping system has to be used. High deposition rates and high wafer throughput make thetechnology ready for production.

Concerning silicon deposition the successful operation of a continuous high temperature CVD for thedeposition of polycrystalline silicon layers is reported in [60]. From the technological point of viewthe feasibility of a continuous high temperature APCVD has already been proved. However, sincemicroelectronic industry has no need for such reactors, their further development has not beenpromoted to an industrial scale production.


In cooperation with the company Centrotherm (Blaubeuren, Germany) a continuous silicon CVDmachine was designed and built to demonstrate the technical and economical feasibility of thistechnology for industrial solar cell production. The development of the apparatus (ConCVD) is basedon the experiences gained with the fore-runner models RTCVD100 and RTCVD160 with their keyfeatures being maintained. In order to fulfill the requirements imposed on the system in terms of highthroughput and low cost the following major changes were necessary:

• continuous movement for higher throughput

• gas curtains for separation of reactor atmosphere from laboratory environment

• resistance heating for better temperature uniformity and increased electrical power utilization

• operation in the depletion regime to increase chemical yield.

The ConCVD is an open system where sample carriers are continuously fed into the reactor. Nitrogengas curtains located at both ends of the machine separate the atmosphere in the interior of the reactorfrom laboratory environment.

The horizontal reactor tube is heated by several resistance heating zones. The sample carriers withvertically mounted samples enter and leave the reactor via gas curtains. Before deposition starts, thesamples are heated up under hydrogen atmosphere. Figure 3.12 shows a schematic of the reactor tubeand reaction chamber. The reaction chamber, where the deposition takes place, consists of a framewith front and end plate being connected by rods. Together with the moving samples a closed volumeis generated into which the process gases are injected. After deposition the samples enter the coolingzone, where they are cooled down before they exit the reactor. The total length of the whole apparatusmeasures 5.4 m. Samples with a maximum width of 200 mm can be processed and by adjusting thetransport speed, layers of nearly arbitrary thickness can be grown.

Gas inlet

SubstrateReaction chamber

Tube

Gas outlet

Movement of the sample carrier

Figure 3.12: Schematic of the reactor tube and deposition chamber of the continuous CVD apparatus(ConCVD).

An increase in chemical yield and an improved homogeneity in layer thickness is expected from thisreactor design compared to its fore-runner models. The resistive heating provides a uniform


temperature distribution throughout the entire reactor. In longitudinal direction thickness homogeneityis achieved by the movement of the samples and for vertical uniformity a gas distribution system willbe implemented. The movement further allows the deposition process to be run under depletionconditions, thus drastically increasing the chemical yield.

Assuming a realistic average deposition rate of 5 µm/min, a reaction chamber length of 400 mm and asubstrate width of 200 mm, the throughput for a 30 µm silicon deposition is calculated to 1.4 m2/h.

LaboratoryReactor

N2 Jet pump

H2

Substrate

Figure 3.13: Scheme of nitrogen gas curtain principle as implemented in the continuous silicon CVDreactor.

For a safe operation of the system an absolutely reliable working of the gas curtains must beguaranteed. A malfunction of the gas curtains can result in an out diffusion of the highly toxic and - inthe presence of oxygen - explosive process gases into the laboratory environment. Figure 3.13illustrates the working principle of the gas curtains. Hydrogen coming from the interior of the reactoris prevented from out diffusion first by a pumping system and second by a back pressure of nitrogengas flowing in opposite direction. For optimal function, i.e. no hydrogen coming out of the system andno nitrogen going into the reactor, the nitrogen flow and the pumping speed have to be adjusted to theout coming gas flow. The pumping system consists of jet pumps which provide continuous pumpingand little technological effort since no electrical supply is needed.

After testing the transport, heating and pumping system, a first silicon deposition process has beensuccessfully carried out.

3.5 SummaryThe overview on common silicon deposition techniques given in the first section of this chaptershowed that silicon deposition by CVD at atmospheric pressure is the only technique which combinesthe advantage of high deposition rate (high throughput) and high crystal quality of epilayers. APCVDis therefore a suitable tool for silicon deposition in the high-temperature approach of CSiTF solar cells.The principle of silicon deposition by CVD was discussed by means of thermal equilibriumconsiderations and by describing a growth model presented in literature. Common APCVD reactorconfigurations and their characteristics were presented.

3.5 Summary 31

Main topic of this chapter was the introduction of atmospheric pressure CVD reactors designed andbuilt at Fraunhofer ISE. The RTCVD100 was the first silicon deposition reactor constructed atFraunhofer ISE and the workhorse in this work. Main technical features of this apparatus are: usage oftrichlorosilane as silicon precursor and diborane for p-type doping, optical heating by halogen lampsand horizontal wafer setup. The wafer setup consists of two horizontal parallel wafer rows forming(together with the quartz carrier) a closed volume inside the reactor tube. The process gas enters thisvolume on one side and exits from the other side via quartz tubes. Using this setup, silicon depositionoccurs only on the inside of the reaction volume i.e. on the wafers and not on the outer reactor tube.Parasitic deposits and a frequent cleaning of the tube are avoided and the chemical yield is increased.The principle of this setup is a key feature of all CVD reactors designed at Fraunhofer ISE. TheRTCVD100 is a lab-type reactor, constructed to evaluate the deposition and reactor principle.

The up-scaled successor model, the RTCVD160, is capable to handle larger wafers at higher capacity.The basic principles of the RTCVD100 were maintained. The continuous CVD set up in 2002 has thepotential for a throughput larger than 1 m2/h, making this system ready for industrial scale production.

33

4 Process Optimization for RTCVD100

Detailed knowledge of the CVD system characteristic is necessary if siliconlayers with well defined properties are to be deposited. This chapter dealswith the characterization of silicon layers grown in the RTCVD100 underdifferent process conditions. Process parameters like total gas flow rate, gascomposition and gas inlet geometry are varied and their effect on thedeposition characteristics is investigated. Finally optimized depositionprocesses are set up for epitaxy and silicon deposition on foreign substrates.

4.1 MetrologyEvery optimization process requires the availability of adequate characterization methods. For thecharacterization of silicon epilayers and silicon layers on foreign substrates properties like thicknesshomogeneity, dopant distribution and dopant level as well as crystal quality have to be quantified.

Different techniques for the analysis of grown silicon layers are explained with emphasis on thetechniques which have been mainly used within this work.

4.1.1 Thickness measurementMeasuring the sample weight before and after deposition gives a mean value for the layer thickness.However, no information about thickness homogeneity across the wafer can be drawn from thismeasurement. Infrared Fourier Spectrometry is commonly used to determine epilayer thicknessuniformity [61], [52]. Other methods providing thickness distribution maps are the defect method [57],[62], cross sectioning or surface profiling. Within the frame of this work all these methods have beenapplied with main focus on the defect method and cross sectioning.

FTIR

Thickness measurement by Fourier Transform Infrared Reflectrometry (FTIR) is based on the analysisof the infrared interference spectrum measured on the epi-sample. A Michelson interferometer isgenerally used for this measurement. The light beams reflected from sample surface and substrate-epilayer interface interfere, giving a spectrum with successive maxima and minima. The interferogramcontains central peaks which are associated to the reflection from the sample surface, and side peakswhich are attributed to the interfering reflection from the interface. The epilayer thickness can becalculated from the separation of the side peaks. A difference in doping level between substrate andepilayer is necessary to obtain the required change in refractive index at the interface. For FTIRmeasurements the specific resistivity of the substrate and epilayer must be less than 0.02 Ωcm andgreater than 0.1 Ωcm respectively. The epilayer thickness must be in a range between 2 and 30 µm[52]. An improvement to this method is obtained by using the fourier transform of the measuredinterferogram. In this case, the layer system and the corresponding reflectance spectrum are modeled


and fitted to the experimental reflectance spectrum. Advantages of this method are higherreproducibility and the ability to measure layer thickness down to 0.5 µm [61].

Defect method

The defect method takes advantage of the growth of epitaxial stacking faults on low quality substratematerial. Stacking faults typically nucleate on the site of impurity atoms present on the substratesurface and grow within the closest packed crystal layer which is the 111 layer in silicon.Considering a <100>-oriented silicon substrate, four equivalent 111 layers exist into which thestacking fault can spread out. They intersect the surface in lines or squares with edges along the <100>directions. Within the epilayer the stacking fault has the shape of an inverted pyramid with the apexlocated at the interface between substrate and epitaxial layer (Figure 4.1) [63]. Measurement of thebase length of the square stacking faults visible on the surface gives the thickness of the epilayer [64],[62]. Depending on substrate orientation, the stacking fault appears with different shapes so differentconversion factors are required.

substrateinterface

[110]

[110]

epilayer surface

base length a

[100]

layer thickness d

5.0ad =5.0=factorconversion

Figure 4.1: Epitaxial stacking fault on <100>-oriented substrate. Measurement of the base lengthgives the layer thickness.

-20 -10 0 10 2020

22

24

26

28

30

32

Defect method Cross section

Thic

knes

s [µ

m]

x axis [mm]

Figure 4.2: Comparison of thickness measurement by defect method and direct measurement on thecorresponding cross section.

4.1 Metrology 35

The error for measuring the absolute layer thickness depends on the error for measuring the baselength of the stacking fault. For a microscope magnification of 50 this systematic error was determinedto 2 µm resulting in a 1.4 µm error for depth measurement, assuming square stacking faults. Thinepilayers below 3 µm are difficult to characterize because the small stacking faults are barely visibleon the surface. The defect method is non destructive but time consuming since it is not automated.

Within this work the validity of this method was verified by comparison with cross sectionmeasurements (see next section) and FTIR. Figure 4.2 shows two thickness profiles measured by thedefect method and by cross sectioning. Within the error bars the data points are corresponding, thusdemonstrating that the defect method can be applied for epilayer thickness measurements. Thecomparison of FTIR and defect method lead to the same conclusion.

Cross sections

Cross sectioning, polishing and preferential etching of the samples enables a direct measurement ofthe epilayer thickness by microscopy. The visualization of epilayer and substrate are based on thedependence of the etch process on the doping level. The applicability of this method therefore requiresa difference in doping level of substrate and epilayer.

Silicon layers deposited on foreign substrates are microcrystalline making an identification of theinterface between substrate and grown layer easy (Figure 4.3). For an application of this method, thesamples were cut in stripes by laser scribing and analyzed by Nomarski microscopy. Polishing of thecutting edge was not necessary. All samples with microcrystalline silicon layer have beencharacterized using this method since neither FTIR nor defect method can be applied.

Figure 4.3: Cross section of a mc-Si substrate with SiO2 intermediate layer and silicon seeding layeron top. The interface between SiO2 and seeding layer is clearly visible.

The major disadvantage of the cross sectioning technique for film thickness evaluation are cost andtime consumption. In addition, the samples have to be destroyed for the analysis.

Surface profiling

At Fraunhofer ISE the applicability of surface profiling for the determination of silicon layer thicknessdistributions is currently tested. The measurement principle is based on the chromatic abberation ofoptical lenses. During the measurement the sample is exposed to a white light beam which is split upby chromatic abberation into spectral components with focus points lying in a vertical line.Wavelengths with focus on the surface of the sample are perfectly reflected. The reflected light isanalyzed by a spectrometer and the distance between sensor and sample surface is calculated.


The system used for this analysis is the MicroProf® by Fries Research & Technology. Areas of100x100 mm2 can be scanned and measurements can be carried out at rates up to 1000 Hz. Theresolution in lateral and vertical direction are specified to 10 nm and 3 nm respectively. 2D and 3Dmeasurements are possible and values for roughness or waviness are calculated automatically. Themajor advantage of this method is clearly the short measuring time required. For a 100x100 mm2

sample only about 4 min are needed for scanning the wafer with a lateral resolution of 1 mm.

The application of this method for a quantification of silicon layer thickness is not obvious. Specialcare must be taken of wafer bow, inhomogeneous thickness of the substrate or parasitic deposits on theback side which may falsify the measurement data. Measurement of the sample before and afterdeposition or the use of uniform substrates with parallel surfaces simplifies the determination of thesilicon layer thickness by surface profile measurements. The applicability of surface profiling forthickness measurements of silicon films on different substrtes is currently under investigation.

4.1.2 Doping controlFor doping control 4-point probe measurements, CV-profiling and Spreading Resistance Profiling(SRP) are commonly used. In the frame of this work, silicon epilayers were characterized by SRP. Theapplication of sheet resistance mapping by 4-point probe measurements in combination with thicknessmapping has been evaluated as a tool to determine doping densities and doping homogeneity for largearea samples. The principle of 4-point probe measurement and SRP are explained in this section.

Since both techniques are based on measuring the resistance between two probes in contact with asemiconductor the expression for the total resistance R between the probes will be given here for betterunderstanding:

sspcp RRRRR +++= 222 (4.1)

where Rp is the probe resistance, Rc is the contact resistance at the metal/semiconductor interface, Rsp

is the spreading resistance and Rs is the resistance of the semiconductor [65].

4-point probe

The 4-point probe method allows the measurement of sheet resistance in thin layers. Four electrodesare positioned in line on the surface of the sample and a current is passed through the two outerprobes. The voltage drop between the inner pair is typically measured with a potentiometer whichdraws no current, so that parasitic resistance like contact, probe and spreading resistance can beneglected in this setup. For thin layers on non-conductive substrate and with thickness d smaller thanprobe spacing s (d ≤ s/2), the sheet resistance can be expressed as

IV

S )2ln(πρ = (4.2)

assuming infinite lateral extension of the sample. V and I denote the voltage drop across the innerelectrodes and the current applied to the outer electrodes, respectively. Correction factors have to beapplied to this formula if samples with finite geometry are to be measured [65].

The 4-point probe measurement is typically used for p/n+ or n/p+ systems. For an application on p+/por n+/n systems the resistance of the substrate must be accounted for [61]. An evaluation of the dopinguniformity across a wafer is only possible, if the layer thickness distribution is known. The

4.1 Metrology 37

measurement principle does not give any information on the doping profile, it gives only the averagesheet resistance.

The potential of sheet resistance mapping for a characterization of specific resistivity in epilayers ofinhomogeneous thickness was evaluated. High resistivity (>10 Ωcm) 3” FZ-Si wafers were used assubstrates and epilayers were deposited using the maximum possible dopant gas flow. Local 4-pointprobe measurements were done using the FAKIR system developed at Fraunhofer ISE, Laboratory andService Center Gelsenkirchen. This high speed system allows for characterization of sample sizes upto 150x150 mm2 with the measurement range being specified to 100 µΩ/sq to 120 MΩ/sq [66]. Sheetresistance measurements were done on a 50x50 mm2 area on the 3” wafer according to the dimensionsof the epilayer. The distance between the points of measurement was set to 5 mm which correspondsto an 11x11 matrix for the characterization of the entire area. Figure 4.4 (left) shows the sheetresistance map of such a sample.

Interpretation of the measurement is not straightforward because of the p+/p structure of the sampleand the associated influence of the conducting substrate to the sheet resistance measurement.However, in a first approximation the substrate was assumed to be isolating thus enabling a separatemeasurement of the epilayer sheet resistance. An evaluation of the doping distribution from sheetresistance data is now possible, if the layer thickness at each point of measurement is known. Thedefect method was applied to determine the local layer thickness d(x,y) and in combination with thevalues of sheet resistance Rsheet(x,y) the specific resistivity was calculated according to

),(),(),( yxRyxdyx sheetS =ρ (4.3)

In Figure 4.4 (right) the resulting distribution map for the calculated specific resistivity is shown. Aninspection of the wafer surface revealed that at the edges of the measurement area the 4 probes werenot always positioned within the epitaxial region but in the neighboring substrate region. Consequentlythe measured values do not display the sheet resistance of the epilayer but the sheet resistance of thesubstrate alone or a combination of both. The high sheet resistance and the corresponding low specificresistivity at the edges of the graphs in Figure 4.4 are attributed to this effect.

-20 -10 0 10 20

-20

-10

0

10

20

>30

Rsheet [Ω/sq]151719212325272930

x [mm]

y [m

m]

-20 -10 0 10 20

-20

-10

0

10

20 <0.04

>0.06

0.04

0.05

0.06

Spec. Res. [Ωcm]

x [mm]

y [m

m]

Figure 4.4: Left: Sheet resistance map of a highly doped epilayer on a high resistivity FZ-Sisubstrate. Right: Corresponding map of calculated specific resistivity.

Taking into consideration that the measured sheet resistance does not correspond to the sheetresistance of the epitaxial layer alone, the calculated resistivity values do not represent the specific


resistivity of the epilayer. Nonetheless, the homogeneity obtained in resistivity distribution shouldreflect the real conditions, assuming a constant influence of the substrate on the measured sheetresistance.

Spreading resistance measurements were carried out along the y=0 direction to determine the specificresistivity in the epilayers. Figure 4.5 (left) shows two resistivity profiles measured on 2 positions,20 mm apart from each other.

0 5 10 15 20 25 30 35

10-1

100

101

Subs

trate

Epitaxy

x [mm] 0 20

(y=0 mm)

Spec

ific

resi

stiv

ity [Ω

cm]

Depth [µm]-10 0 10

141618202224262830

4-point probe SRP

Rsh

eet [

Ω/s

q]

x axis [mm]

Figure 4.5: Left: Specific resistivity profiles for epilayer on high resistivity substrate measured bySRP at different sample positions. Right: Comparison of sheet resistance valuesmeasured by 4-point probe and calculated from spreading resistance profiles.

Both curves are roughly corresponding with slight differences in epilayer thickness. Resistivities in therange of 0.07 Ωcm are measured in the constant epilayer region compared to a mean value ofapproximately 0.05 Ωcm, calculated from 4-point probe and thickness measurements (Figure 4.4). Asalready mentioned, this calculation was based on the assumption that the measured sheet resistance isidentical to the sheet resistance in the epilayer, which is certainly not correct for the p+/p structureunder consideration and a deviation between SRP and the calculated values was therefore expected.

Now, instead of comparing the values for the specific resistivity, the sheet resistance was calculatedfrom each SRP curve (substrate included) and compared to the data points obtained from the 4-pointprobe measurement. The results depicted in Figure 4.5 (right) show that the calculated sheetresistances exceed the measured data by approximately 30%. Possible reasons for this deviation arethe unknown impact of substrate, epilayer and highly doped surface layer on sheet resistancemeasurement.

To determine whether the calculated map of specific resistivity in Figure 4.4 (right) corresponds to thereal distribution in the epilayer, more data points from SRP measurements are necessary.

For a realistic determination of epilayer resistivity from 4-point sheet resistance measurements andepilayer thickness measurements, an ideal sample structure with non-conducting substrate andhomogeneous doping density in the epilayer is essential to enable an unambiguous interpretation of themeasured sheet resistance values. However, assuming a constant influence of the substrate on the 4-point probe measurement and using epitaxial layers with constant doping densities throughout theentire layer, the calculated distribution of specific resistivity should reflect the real doping distributionin the epilayer. In this case, it might be possible to calibrate the sheet resistance measurement data e.g.

4.1 Metrology 39

by spreading resistance measurements to yield a mapping of the prevailing carrier density. For averification of this interpretation further experiments have to be carried out.

A combination of absolute epilayer thickness measurement by surface profiling and sheet resistancemapping with the FAKIR system could provide a fast and efficient characterization tool for dopingdensity and homogeneity of large area epilayers.

Spreading Resistance Profiling (SRP)

Using Spreading Resistance Profiling (SRP), the depth profile of the specific resistivity in a singlecrystalline silicon layer can be quantified. The method is based on the measurement of the spreadingresistance between two probes which are stepped along the beveled sample surface. Comparison of thespreading resistance data with calibration curves gives the specific resistivity at the location ofmeasurement [65].

For depth profiling a small chip is taken from the sample, waxed onto a bevel mount and ground usinga diamond slurry. Next, the probes are aligned parallel to the bevel edge and are stepped along thebeveled surface, perpendicular to the bevel edge (Figure 4.6).

xα

z

Beveled surface

Bevel mount

Probe tipsBevel edge

Figure 4.6: Left: Ground sample on bevel mount, the line of measurement is indicated. Right: Theprobe tips are aligned parallel to the bevel edge and move in a perpendicular line to it.

The depth resolution ∆z is given by the step width ∆x and the bevel angle α according to

αsinxz ∆=∆ (4.4)

The total resistance between the two probes is again given by (4.3) with the spreading resistancedominating. For a flat, circular ohmic contact to a semi-finite sample the spreading resistance Rsp canbe expressed as

aRsp 2

ρ= (4.5)

with specific resistivity ρ and contact radius a. In reality, conductivity-type, resistivity, surface finishand orientation influence the spreading resistance.

The two tungsten-osmium probe-tips are roughened such that the actual electrical contact is made by acluster of microcontacts which are able to penetrate the native silicon dioxide layer present on everysilicon surface [67]. The contact area and radius is given by the amount, the shape and the distributionof the microcontacts; they characterize the electrical contact. Roughening of the microcontacts resultin a higher penetration and an increase in the number of microcontacts whereas smoothing leads to the


opposite result. The spreading resistance is very sensitive on the condition of the probe-tips makingregular qualification and conditioning an absolute necessity for quality control. The spacing betweenthe probes lies generally between 65 to 100 µm and the voltage between the probes is kept at a lowvalue of 5 mV to reduce any influence of contact resistance.

The probes are mounted on gravity-loaded probe arms so that the probes impinge the surface with aconstant force. The spreading resistance also depends on the probe loading: using low probe loads, thepenetration of the spreading resistance is reduced and the measurement is more concentrated on thenear-surface layer. For the measurement of ultra-shallow junctions, low probe-loads of 5 g aregenerally used.

Spreading Resistance is a comparison technique. Measured spreading resistance data are compared tocalibration curves relating resistivity to spreading resistance. Calibration standards for n- and p-typesilicon with <100> and <111> orientation are available from the National Institute of Standards andTechnology (NIST). Calibration curves have to be generated for each specific measurement setup(probe-arms, conditioning probes, surface finish, step-width) using the calibration standards.Reconditioning of the probe-tips or changing the probe-load requires a re-calibration.

At Fraunhofer ISE a NanoSRP2000 system by Solid State Measurements (Pittsburgh, USA) was setup for measuring doping profiles on epilayers. Typical step widths are 1, 2.5, 5 or 10 µm. Differentbevel mounts with angles from 4’ to 11°32’ can be used giving depth resolutions down to 1 nm. Bevelangle and step width are chosen according to the required resolution and measurement depth. Themeasurement range is specified to a range from approximately 1x1011 cm-3 to the dopant solubilitylevel. Time saving measurements are realized by automated bevel edge alignment, probe calibrationand conditioning. Up to 6 samples can be mounted on the sample holder for successive measurements.The analysis software Analysis-NANOSRP enables automated processing of the measured data to yieldspecific resistivity and carrier density. A typical analysis procedure includes determination of p- andn-type regions, smoothing of the raw profile and calculation of the corresponding profiles forresistivity and carrier densities based on the calibration curves. Field effects from underlying layersinfluence the spreading resistance data and are therefore taken account of by using adequate correctionfactors. Finally, the corrected resistivity is converted to carrier densities using Thurber’s empiricalcurves for boron and phosphorous-doped silicon [68]. The measurement error is associated to the errormade for the calibration which is typically in the 5% range.

For the characterization of epilayers by SRP a probe-load of 10 g has been used. Unless otherwisestated a step width of 5 µm and a bevel angle of 2°52’ was applied resulting in a depth resolution ofapproximately 500 nm. Grinding was done by two steps: first, the samples were ground on a graniteplate using an Al2O3/glycerin slurry. A fast removal of surface layers is achieved, however at theexpense of surface smoothness. Second, the samples were polished on a rotating quartz plate using thetypical diamond/oil slurry. The grinding procedure has to be done with great care in order to avoidscratches on the beveled sample surface which might influence the SRP measurement. Grinding ofsamples with hard ceramic substrates or with silicon carbide intermediate layer is critical, since smallbits of the material tend to break out and produce further scratches (Figure 4.7).

The bevel angle was measured with a mechanical Tencor alpha-step profiler. For a bevel angle of2°52’ the standard deviation for angle measurements on monocrystalline beveled samples wasdetermined to 1%. Bevel angle measurement is reliable for monocrystalline epilayers with defect-free,smooth surface but is difficult for multicrystalline or recrystallized samples with rough, facetted

4.1 Metrology 41

surface. For these materials, the specified bevel angle has usually been used for measurement andalignment has been done using the interface between substrate and silicon layer or using theintermediate layer as reference line. Further, a <100> crystal orientation has always been assumed forrecrystallized samples. This approximation can be tolerated because the preferential crystal orientationof the recrystallized silicon layers is the <100> orientation [69].

Sample surface Beveled samplesurface

Bevel edge

Monocrystalline sample α = 2°52‘ 10x magn. Recrystallized sample α = 2°52‘ 10x magn.

Scratches

Bevel edge

Figure 4.7: Left: Beveled Cz-Si sample. The bevel edge is clearly visible as a straight line. Right:Beveled multicrystalline silicon layer. The bevel edge is facetted because of themulticrystalline structure of the layer and scratches are disrupting the beveled surface.

The advantages of the SRP technique are excellent depth resolution and wide range of measurement.However, sample preparation is time consuming and destructive. Skillful operation, frequent probeconditioning and calibration are necessary to ensure constant quality of the measurements.

4.1.3 Impurity concentration measurements by SIMSSecondary Ion Mass Spectroscopy (SIMS) was applied to characterize oxygen, carbon and boronconcentrations in epilayers. During SIMS, material is sputtered from the sample surface andsubsequently analyzed by mass spectrometry. Only about 1% of the sputtered atoms are ionized(secondary ions) and can be detected by the mass spectrometer. For a specific element the yield ofsecondary ions depends on the energy of the primary ions but also on the type of ions used forsputtering. Electronegative ions are used if electropositive elements are to be detected and vice-versa[65]. The chemical surrounding i.e. the composition or type of the sputtered material representsanother factor influencing the yield of secondary ions. For quantitative measurements, calibratedelement standards of known composition have to be used.

The strength of SIMS lies in its capability to detect any kind of element with detection limits as low as1x1014 cm-3 for some elements. The lateral resolution depends on the dimension of the ion beam and istypically in the range of 100 µm. For depth profiling the sputter crater is measured and correlated tothe sputter time by linear interpolation.

SIMS measurements were done by RTG Microanalyse (Berlin, Germany) using a Cameca ims4fsystem. For boron and carbon/oxygen profiles an O2

+ beam with 8 keV energy and a Cs+ beam with14.5 keV energy has been applied respectively.


4.1.4 DefectsThe most frequent defect type in epilayers are stacking faults, spikes and dislocations [63]. Stackingfaults and spikes can be identified by microscopic analysis of the surface of the epilayer. Dislocationscan be revealed by chemical etching, where small etch pits develop on the site of dislocation. The etchpit density is generally used as a measure to quantify the crystallographic quality of silicon material.

Dislocation densities in epilayers were determined by Secco9 etching of polished sample surfaces andautomated counting of the etch pit density. This method does not make account of stacking faults andspikes, only point defects and line defects intersecting the surface are used for measurement.

4.1.5 Lifetime measurement by MW-PCDMicrowave Photo-Current-Decay (MW-PCD) is a powerful tool for the characterization of minoritycarrier lifetimes in silicon bulk material. It makes use of the correlation of effective lifetime on theasymptotic decay characteristic of excess minority carriers generated by a pulsed excitation. A changein the number of excess minority carriers is associated with a change in reflectivity. The temporalchange in reflectivity of a microwave signal is used as a measure for the decay of minority carriers inthe sample [65].

The measured lifetimes are effective lifetimes which means that surface recombination effects areincluded. Surface recombination velocities can be reduced by passivating the surfaces with silicondioxide or silicon nitride layers. At Fraunhofer ISE surface passivation is done by the deposition ofSiNx:H layers by PECVD resulting in surface recombination velocities below 10 cm/s [70].

The application of MW-PCD on epilayer systems is not straightforward because thickness, dopingdensity and bulk lifetime in the epilayer and substrate as well as interface recombination velocityinfluence the measured minority carrier lifetime. Using a low resistivity substrate, such that thelifetime in the epilayer is considerably larger than the lifetime in the substrate, information on theepilayer bulk lifetime and the interface recombination velocity can be extracted from MW-PCDmeasurements [71]. In return, the measurement becomes more difficult due to the high reflectivity ofthe highly doped substrate. The generating laser pulse and the microwave antenna are located onopposite sides of the sample. Therefore generation is high if the epilayer faces the laser but at the sametime the measurement signal is small because the substrate faces the microwave antenna. Turning thesample results in a weak generation but good detection characteristics. In this work, best results wereobtained for the substrate surface facing the laser pulse.

4.2 Epitaxial depositionWithin the approaches of crystalline silicon thin-film solar cells pursued at Fraunhofer ISE the activebase layer of the cell is typically deposited onto recrystallized silicon layers or other silicon substratesby epitaxy. The requirements imposed on layer quality in terms of defect density and impurity contentare stringent if high minority lifetimes are to be achieved. Optimization of the epitaxy process in theRTCVD100 was carried out with focus on thickness and doping uniformity as well as crystal quality.

9 Secco etch: Solution from K2Cr2O7 and HF.

4.2 Epitaxial deposition 43

According to the prevailing temperature distribution within the reactor, characterization andoptimization procedure were reduced to sample positions in the middle of the top wafer row where thetemperature distribution was found to be the most homogeneous (see section 3.4.2).

State-of-the-art CVD processes are run at high temperatures of 950-1250°C where high quality layerscan be grown at high deposition rates. For the RTCVD100 a deposition temperature of 1170°C wasfound to be adequate to produce epilayers of low defect density. Going to higher temperatures resultsin higher growth rates at the expense of an early process gas depletion. On the other hand lowering thetemperature gives silicon layers with a larger defect density. With respect to these restrictions andbased on first experimental results [40] the deposition temperature was fixed to 1170°C for theoptimization.

4.2.1 Pre-epitaxial sample cleaningSample preparation prior to epitaxy plays a crucial role concerning crystal quality of the epitaxiallayer. Residual oxygen or other contaminants on the surface form nucleation centers for defectgeneration leading to highly defective epilayers. Standard cleaning procedures include an ex-situcleaning before loading the samples into the reactor and an in situ cleaning during the CVD process.The ex-situ cleaning aims to remove organic and metallic contaminants from the sample surface. Forin-situ cleaning a hydrogen prebake at elevated temperature (≥1000°C) is typically applied duringwhich the native oxide (1.0-1.5 nm) which forms on every silicon surface is decomposed andevaporated [72]. An additional HCl in-situ etch is sometimes implemented directly before silicondeposition starts [73].

Within this work, sample pre-cleaning was usually done by an ex-situ RCA10 cleaning with the lastHF-dip omitted to prevent any impurities or water molecules from adhesion on the hydrophobichydrogen-terminated sample surface [74]. Polished wafers coming from the producers box weredirectly introduced into the reactor without additional ex-situ cleaning. Before deposition a hydrogenbake at growth temperature was applied for all sample types.

4.2.2 Thickness uniformityA uniform distribution of the process gas across the entire deposition area is essential if excellentthickness homogeneity is to be accomplished. Wafer geometry and gas inlet play a key role on thatscore. The entire setup of the RTCVD100 reactor can be compared to traditional horizontal reactorsand some of the problems encountered there have also been found to arise in the RTCVD100.

In [40] some basic characteristics of the RTCVD100 system concerning epitaxial depositions havealready been evaluated. The effects of process temperature, gas composition and total gas flow on thelongitudinal deposition profile of both wafer rows were investigated. As a result of these experimentsa standard process was defined. The evaluation of the longitudinal growth rate profiles has beenperformed on the base of mean values calculated from the difference in mass before and afterdeposition leaving the real thickness distribution across the sample area in the dark.

10 RCA cleaning: Standard chemical cleaning procedure to remove metallic and organic impurities from siliconwafers. Step 1: solution of NH4OH:H2O2:H2O, Step 2: solution of HCl:H2O2:H2O.


Taking the parameter set defined in [40] as a starting point the effect of gas inlet geometry wasinvestigated and further variations of total gas flow rates and composition were carried out. Saw-damage etched Cz-Si wafers with <100> crystal orientation were used for all experiments and thedefect method was applied for thickness measurement. A mesh of 9x7 measurement points wasapplied on a 50x100 mm2 area, giving a resolution of 15 mm in longitudinal direction and 5 mm inlateral direction. Figure 4.8 shows the thickness distributions for two deposition runs differing only ingas inlet geometry. A simple gas tube with round cross section (Figure 4.8, top) and a nozzle (Figure4.8, bottom) have been applied as gas inlet for the deposition processes. All values are relative to themaximum thickness measured for each run.

-80 -60 -40 -20-20

-10

0

10

20

TCS = 12 g/min

H2i = 3 sl/min

gas inlet: tube


Lat

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m]

20 40 60 80

020406080100

relativethickness [%]

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10

20


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pos

ition

rel

. to

cent

er [m

m]

20 40 60 80

TCS = 12 g/min

H2i = 3 sl/min

gas inlet: nozzle

020406080100


Figure 4.8: Thickness distribution for two runs with identical process parameters. Top: Applicationof a tube as gas inlet. Bottom: Application of a nozzle as gas inlet.

Both distribution maps in Figure 4.8 feature a decrease in lateral direction towards the edges of thedeposition area. Assuming laminar flow the gas velocity distribution within the reaction volumefollows a parabolic profile with zero velocity at the boundaries and maximum velocity in the center ofthe main gas stream. The concentration of chemical species is proportional to the velocity andtherefore decreases towards the walls leaving the corners impoverished of process gas. A drop ingrowth rate from center to the corners of the carrier follows [45].

Application of the tube as gas inlet leads to a thickness distribution which is symmetric relative to themiddle of the furnace reflecting the temperature distribution within the reactor. A so called “coldfinger” effect is observed in gas flow direction (Figure 4.8, top). This characteristic is commonlyexplained as follows: heat is transferred from the reactor walls to the incoming cold process gasleading to a cooling of the sample surface and hence a drop in growth rate [34]. This drop in growthrate can be seen in Figure 4.8 (top) along the centerline of the deposition area. The presence of thecold finger depends on the properties of the process gas: a large thermal capacity or a high gas flowrate (which means large velocity) generally results in a more pronounced cold finger effect [75]. Amaximum deposition rate of 6.3 µm/min was measured under the prevailing conditions.


In horizontal reactors gas diffusers like screens and shower heads were developed to accomplish auniform gas distribution [76]. In our setup a simple nozzle is used to widen the incoming gas flow.The process gas is conducted towards the boundaries of the reaction volume making the parabolicvelocity and mass concentration profile in the reaction volume more shallow. A more uniformdistribution of all gas species across the entire reaction cross section and a more homogeneous heatingup of the gas mixture is the consequence. The thickness distribution in Figure 4.8 (bottom) illustratesthese effects. The cold finger has disappeared and the onset of the uniform region of the depositionzone has moved upstream towards the gas inlet as a result of the broader gas distribution. Compared tothe process without nozzle a higher maximum growth rate of 8.4 µm/min was reached whichcorresponds to an increase by a factor 1.3. However, a drop in growth rate is observed in downstreamdirection. This effect is attributed to a depletion in precursor gas resulting from an improveddistribution and heating of the incoming process gas and consequently an enhanced consumption oftrichlorosilane at the inlet region. In traditional horizontal reactors and also barrel reactors a slight tiltof the sample tray counteracts the depletion. In the RTCVD100 reactor larger flow rates are employedto diminish depletion effects.

To evaluate the limits in terms of thickness uniformity when using the nozzle for gas injection, furtherexperiments were carried out with varying total gas flow rates and gas composition. Best results wereachieved for maximum gas flow rates of precursor and carrier gas resulting in a thickness distributionas illustrated in Figure 4.9. The large flow rate of 20 g/min of trichlorosilane is needed to minimize thedepletion effect which is still observed in Figure 4.8. On the other hand, a large amount of hydrogen isnecessary to ensure an effective chemical conversion.

-80 -60 -40 -20-20

-10

0

10

20


Lat

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rel

. to

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m]

20 40 60 80

TCS = 20 g/min

H2i = 10 sl/min

gas inlet: nozzle


020406080100

Figure 4.9: Thickness distribution map measured for a deposition process using a nozzle andmaximum gas flow rates. A maximum growth rate of 10 µm/min was determined.

In conclusion, the optimized process gives a mean deviation in layer thickness of 13% across thedeposition area of 40x100 mm2. Further improvement in thickness uniformity can be expected using amore sophisticated gas injection system e.g. a shower head.

Two different growth processes giving similar thickness uniformity but featuring a large difference ingrowth rate were selected for a further characterization of epilayer quality. The deposition parametersof both processes A and B are listed in Table 4.1. The corresponding thickness distribution mappingshave already been presented in Figure 4.8 (top) and Figure 4.9 for process A and B respectively.


A B

T [°C] 1170 1170

TCS [g/min] 12 20

H2i [l/min] 3 10

Total gas flow rate [l/min] 5 13.3

Cl/H 0.75 0.43

Gas inlet Tube Nozzle

Average growth rate [µm/min]in uniform area

5.5 9

Table 4.1: Comparison of process parameters for two different epitaxy processes.

4.2.3 Doping of epilayersTwo aspects of doping concentration in epitaxial layers were investigated: first, the functionaldependence of doping density on dopant gas flow and second, the uniformity of the doping densityacross the deposition area. A detailed discussion of the characteristics of the epilayer doping profiles ispresented in a separate chapter 5.

The measurement range of the diborane mass flow controller limits the maximum dopant gas flow rateto 50 sccm. For flow rates below 1 sccm the accuracy of the controlling unit reduces thereproducibility of doping concentrations. Figure 4.10 shows the dependence of minority carrier densityfrom the diborane gas flow rate for process A and B.

1 101015

1016

1017

1018

1019

process A process BC

arrie

r den

sity

[cm

-3]

B2H6-flow [sccm/min]

Figure 4.10: Measured carrier density as a function of diborane gas flow rate for epitaxy process Aand B on a double-logarithmic scale.

Increasing the diborane gas flow for fixed process conditions results in an increase in carrier density.On the other hand, the carrier concentration decreases when leaving the diborane gas flow fixed andusing process A (low growth rate) instead of process B (high growth rate). For both cases the linear


relationship between carrier density and dopant gas flow rate is obvious. The observed functionalityallows for a deposition of epilayers with defined carrier concentrations. The mechanism of boronincorporation and the dependency of process parameters on carrier density are discussed in detail inchapter 5.

The deposition of silicon without addition of diborane results in p-type layers with specific resistivityin the range of 133 Ωcm, independent of substrate resistivity. The low doping density measured forthese intrinsic layers verifies the purity of the used process gases and the cleanliness of the entirereactor and gas system. The growth of intrinsic layers and the corresponding doping profiles arestudied in chapter 5.

The doping uniformity along the deposition area was quantified for the maximum and minimumreproducible gas flow rates. Local SRP measurements of carrier densities were carried out along thecenterline of the reactor and in a parallel line along the side walls, which represents the longitudinaledge of the deposition area. In Figure 4.11 the distribution of specific resistivity is graphed for bothdeposition processes A and B.

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0.1

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2 sccm B2H650 sccm B2H6

Process A, centerline (y=0mm), edge (y=20mm)

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cm]


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Process B, centerline (y=0mm), edge (y=20mm)

2 sccm B2H650 sccm B2H6

Spec

. res

istiv

ity [Ω

cm]


Figure 4.11: Distribution of dopant concentration across the deposition area for process A (top) andB (bottom). Measurements were carried out along the centerline and in a parallel linenear the edge.


Comparing the two processes (Figure 4.11 top vs. bottom) again shows the difference in dopingdensity for equal dopant gas flows but different process conditions: the measured specific resistivity isconsiderably larger for process B compared to process A. For both deposition processes, the resistivityvalues along the edges are slightly higher compared to the centerline and a slight rise is observed indownstream direction. The standard deviation in doping density across the entire deposition area isdetermined to 11% for both diborane gas flow rates and both epitaxy processes.

In conclusion, the distribution of doping density across the deposition area shows a uniformity similarto the growth rate distribution. Dopant gas depletion along the direction of gas flow only plays a minorrole.

For silicon thin-film solar cells, comparatively large variations in doping densities can be toleratedwithout considerably reducing the performance. The uniformity in carrier concentration accomplishedfor both epitaxy processes is sufficient for solar cell application.

4.2.4 Crystal qualityThe crystal quality of epilayers depends on substrate material, pre-epitaxial cleaning and processconditions [77]. Epitaxial defects can be categorized according to their origin in substrate-relateddefects and defects related to process conditions. Grain boundaries or other crystal imperfectionsintersecting the substrate surface are continued in the epitaxial layer and are therefore accounted to thefirst category. Stacking faults and spikes are the most common epitaxial defect type. They aregenerally attributed to the presence of impurities (organic or metallic) on the substrate surface [78].Contamination of the sample surface can be caused by an incomplete cleaning prior to epitaxy andunclean process conditions (wafer handling, laboratory cleanliness, purity of the process gases etc).Epitaxial layers are known to have larger defect densities compared to standard wafers but the oxygenconcentration is typically lower compared to Cz-Si [79].

Epitaxial stacking faults have already been discussed in section 4.1.1. Characterization of epitaxialsolar cells on <100> Cz-substrates by EBIC (Electron Beam Induced Current) shows low short circuitcurrents at the corners of the stacking faults, indicating that the dislocations present at these sites act aspotential barrier for minority carriers [80]. In [64] it is proposed that the electrical recombinationactivity is not caused by the stacking fault itself but is related to its gettering effect on point defectsand impurities. Spikes appear as polycrystalline protrusions of several µm in height on the epilayersurface and sometimes they are combined with stacking faults. Of all defect types they are reported tohave the most detrimental effect on the electrical quality of epitaxial wafers [63]. Figure 4.12 showsSEM11-images of both defect types.

The surfaces of epitaxial layers grown in the RTCVD100 on Cz-Si substrates were inspected byNomarski microscopy. The density of stacking faults and spikes was found to depend on the substratepre-cleaning procedure and morphology: epilayers on polished Cz-Si substrates taken directly from theproducers box revealed only few stacking faults and no spikes indicating excellent layer growth.Application of an HF-dip prior to epitaxy enhanced the growth of both defect types. This effect isassumed to be related to the hydrophobic sample surface after HF-treatment and the associatedenhanced attraction of particles from the surrounding. Growth of epilayers on CP-133 saw-damage

11 SEM: Secondary Electron Microscopy.


etched Cz-Si substrates of minor quality typically resulted in high densities of stacking faults andspikes within the epilayer.

Figure 4.12: Left: Epitaxial stacking fault on <100>-oriented silicon layer. Right: Spike protrudingfrom epitaxial surface (microscope images).

The quality of the epitaxial layers grown by process A and B was quantified in terms of dislocationdensities. High quality single-side polished <100> Cz-Si wafers with an off-orientation of 1° wereused as substrate material. They were taken directly from the producers box and introduced into thereactor without additional ex-situ cleaning. For both epitaxy processes a mean value of 1x104 cm-2 wasspecified as defect density. Assuming a typical value of less than 100 cm-2 for silicon wafers [81] thiscorresponds to an increase by 2 orders of magnitudes. In commercial epitaxy reactors used formicroelectronics defect densities below 1x103 cm-2 are typically reached. However, the measureddefect density of 1x104 cm-2 is still in an acceptable range for an application of the epilayers in siliconsolar cell preparation. High oxygen and carbon concentrations or a high density of self-interstitialswithin the epilayers might be the reason for the comparatively high defect density.

4.2.5 Lifetime measurementsThe effective minority carrier lifetime in epilayers was determined by MW-PCD. Samples wereprepared by epitaxial deposition of a 2 µm thick BSF layer and a 30 µm thick silicon base layer on Cz-Si wafers (≤0.02 Ωcm). The doping concentration of the BSF was set to a high level comparable tosubstrate doping density, while the base layer doping was varied from 4x1016 cm-3 to 1x1017 cm-3. Forcomparison, epitaxial layers grown in a commercial system were also characterized. All samples wereRCA cleaned with SiNx:H layers deposited by PECVD on front and rear side for surface passivation.

Figure 4.13 illustrates the dependence of the measured effective carrier lifetime from specificresistivity of the epilayers. The measured values for effective minority carrier lifetime range from2.5 µs to 7.2 µs depending on the doping concentration of the epilayer. Increasing the specificresistivity results in an increase of the effective minority carrier lifetime due to a reduced Augerrecombination. The measured effective carrier lifetime depends on the lifetime of the bulk epilayerand the surface recombination velocities. The front surface is well passivated by SiNx:H whereas therear surface recombination is determined by the interface between substrate and epilayer. Thecontribution coming from minority carriers generated in the substrate material is considered to benegligible due to the high doping level. Assuming perfect surfaces with zero recombination velocities


the effective lifetime gives a lower limit for the actual bulk lifetime. At a doping level of 1x1017 cm-3

the measured carrier lifetime of 2.48 µs corresponds to a minority carrier diffusion length of 66 µm,which is about twice the epilayer thickness, satisfying the imposed requirement on epilayer quality.

0.1 0.2 0.3 0.4 0.5 0.61

2

3

4

5

6

7

8 RTCVD 100: process A RTCVD 100: process B commercial reactor

τ eff [

µs]

Specific resistivity [Ωcm]

Figure 4.13: Effective minority carrier lifetimes measured by MW-PCD for epitaxial layers withdifferent specific resistivity.

4.2.6 Chemical analysisOxygen and carbon are two of the most common impurities which are incorporated during siliconCVD film growth. The amount of incorporated atoms depends on process conditions and especially ongas purity. High concentration peaks of either impurity at the interface between substrate and epilayergenerally result from incomplete preclean of the sample surface [82]. The concentration of bothelements in the epilayer generally increases with decreasing deposition temperature [79].

For a characterization of the oxygen and carbon content in epilayer samples were prepared on RCAcleaned FZ-Si and Cz-Si substrates. The epilayers were either mechanically ground or wet-chemicallyetched to a final thickness of approximately 7 µm in order to reduce SIMS measurement time and toincrease depth resolution.

Using FZ-Si substrates, oxygen and carbon concentration below the detection limit of 1x1016 cm -3

were measured for epilayer and substrate verifying the high purity of the RTCVD100 system.

Figure 4.14 shows carbon and oxygen concentration profiles for an epilayer grown on Cz-Si substrate.The depth of the interface was determined by SRP and verified by SIMS boron profiling. The oxygenconcentration in the substrate is at the level of solid-state solubility and in a typical range for Cz-Si12.Within the epitaxial layer the concentration reduces to 1x1018 cm-3 at the surface. The carbonconcentration behaves in just the opposite way: it increases slightly from substrate to epilayer surface.The carbon content in the substrate comes up to approximately 3x1017 cm-3 compared to 6x1017 cm-3 atthe epilayer surface. At the interface between substrate and epitaxial layer no peaks in oxygen orcarbon concentration are observed indicating that surface contamination does not present a problem.

12 In Cz-Si and FZ-Si typical oxygen concentrations are in the range of 1x1017 to 2x1018 cm-3 and 1x1015 to1x1016 cm-3 respectively [May90], [Kar99].


6 4 2 0 -2 -4 -6

1017

1018

1019

1017

1018

1019

Con

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n [c

m-3]

Distance from interface [µm]

oxygen carbon

epitaxy substrate

Figure 4.14: Oxygen and carbon concentration profile measured by SIMS for an epilayer on Cz-Sisubstrate.

The decrease of oxygen concentration with increasing distance from the interface is considered to bedue to a solid-state out-diffusion of oxygen from the silicon substrate into the epilayer [83]. Asimulation of the epitaxial growth process and oxygen diffusion was carried out to verify thisstatement. The applied simulation tool is based on a discretized growth process with Fick’s diffusionequations being solved after each growth step. Input parameters for the simulation are silicondeposition parameters and material properties. The CVD process is characterized by growthtemperature, duration and thickness of the final epilayer. Additional high temperature steps followingthe growth process can be included. The concentration of the element under investigation – in this caseoxygen – has to be assumed for substrate and epilayer region.

The diffusion process strongly depends on the diffusion coefficient which is given by

)exp()( 0 TkEDTD

B

A−= (4.6)

where T is the diffusion temperature, kB is Boltzmann’s constant and D0 and EA denote diffusionconstant and activation energy respectively [84]. For the diffusion of oxygen in silicon both valueswere taken from [85] for the simulation:

120 13.0,53.2 −== scmDeVEA (4.7)

According to experimental values, the growth of a 25 µm epilayer at a deposition rate of 10 µm/minwas simulated. Growth temperature and post-deposition anneal temperature were varied to evaluatetheir influence on the oxygen diffusion profile. An oxygen concentration of 1x1013 cm-3 and4x1018 cm-3 were assumed for epilayer and substrate respectively. Because of the strong functionaldependence of the diffusion coefficient on temperature, the growth temperature and the annealtemperature significantly effect the diffusion of oxygen. Figure 4.15 shows simulated oxygen diffusionprofiles resulting from a variation of growth temperature.


6 4 2 0 -2 -4 -6

1016

1017

1018

Growth temperature [°C] 1270 1170 1070

anneal at 1200°C

Con

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n [c

m-3]


Figure 4.15: Simulated oxygen concentration profiles across the interface between substrate andepilayer. The growth temperature has been varied.

In general, increasing the deposition or anneal temperature results in an enhanced diffusion of oxygen.The gradient of the corresponding concentration profile is consequently smaller and the profile moreflat.

The simulation verifies that the oxygen concentration in the epilayer can indeed be explained by adiffusion of oxygen from the substrate into the epilayer. However, in case of carbon the SIMS profilein Figure 4.14 shows an increase in concentration from substrate to epilayer. Taking into considerationthat the carbon concentration in epilayers grown on FZ-Si substrates are below 1x1016 cm-3 a diffusionof carbon from epilayer to the substrate has to be excluded. At present the reason for the increase incarbon concentration in the epitaxial layer is not clear.

4.2.7 Surface morphology of multicrystalline layersNomarski microscopy was used for a characterization of surface morphology. On <100>-oriented Cz-Si substrates the morphology of the epilayer was found to depend on the substrate surface. Forepilayers on polished substrates the surface was equally smooth. An orange peel like morphology wasobserved for epilayers on saw-damage etched substrates, reflecting the substrate morphology.

Epilayers grown on multicrystalline substrates show different surface morphologies from almost flat toinverted tripyramid-like textures according to the underlying grain orientation. Trenches at the site ofmost grain boundaries is a typical feature. A dependence of growth rate on crystal orientation has beenobserved. In Figure 4.16 all of these features are illustrated. Surface micrographs and correspondingtopographic profiles for an epilayer on mc-Si substrate are presented for two different positions. Note:the measured height does not correspond to the epilayer thickness.

The image on the left hand side in Figure 4.16 (top) shows two grains of similar or equal crystalorientation enclosing a small grain of different crystal orientation. The grain in the middle ischaracterized by a significantly larger thickness and a rougher surface structure compared to the outergrains. The typical base length of the isosceles triangles visible on the surface is in the range of 90 µmwith an enclosed angle of ~64°. The structure resembles the shape of an inverted tripyramid with theapex located several microns below the actual surface of the epilayer. The grain boundaries betweenthe adjacent crystal orientations are rather smooth without trenches.


On the right hand side in Figure 4.16 (top), two grains with very smooth surface morphology areadjoining. On the site of the grain boundary a trench has developed with a width of ~120 µm and adepth of ~9 µm. The difference in thickness between the two grains was determined to 5 µm.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.98

101214161820222426

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ght [

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x-axis [mm]0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.98

101214161820222426

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x-axis [mm]

Figure 4.16: Nomarski microscope images (top) and corresponding profiles (bottom) of epilayersgrown on a multicrystalline substrate.

For LPE layers a difference in growth velocity for neighboring grains of different crystallographicorientation is reported to be a consequence of growth conditions. In the surface reaction limited regimethis difference is large, leading to large steps between neighboring grains [86]. For mass transportlimited growth the difference is smaller leading to a smoother transition between two grains ofdifferent orientation. Epitaxy in the RTCVD100 is limited by surface reaction kinetics and thus thegrowth rate is also a function of grain orientation which is clearly visible in Figure 4.16.

The growth induced texture of multicrystalline epilayers is a typical feature for high temperatureAPCVD and is reported to be a consequence of the development of <111> facets [87]. The shape ofthe texture depends on the crystallographic orientation of the underlying grain.

The trenches observed on sites of grain boundaries can be explained from an energetical point of view:the growth of most grain boundaries requires high energies and as a consequence the growth rate isreduced on these sites. The development of crystal facets between neighboring grains usually requiresless energy and is therefore more favorable compared to the growth of the grain boundary [88]. Thedevelopment of trenches can be interpreted as a compromise between these two mechanisms. Once thefacets have established the silicon species impinging on the sample surface are more likely to beincorporated on these slightly protruding sites, thus further retarding the growth of the grain boundary


[89]. The width and depth of the trenches depends on the type of grain boundary between adjacentgrains with low-energy grain boundaries usually being associated to small and shallow trenches.

4.3 Silicon deposition on foreign substratesIn chapter 2 a silicon thin-film solar cell approach based on recrystallization of silicon layers onforeign substrates was presented. The realization of this concept requires the heterogeneous growth ofa thin highly doped silicon layer on non-Si substrates. For this purpose CVD processes had to bedeveloped and optimized.

The substrate material to be used for this solar cell structure are low-cost ceramics encapsulated by adiffusion barrier layer. At Fraunhofer ISE, silicon dioxide (SiO2) and SiO2/SiNx/SiO2 (ONO –oxide/nitride/oxide) layer stacks are generally used as effective diffusion barrier. The CVD process forthe deposition of silicon layers on substrates with SiO2 encapsulation was optimized for mc-Sisubstrates covered by a 2 µm PECVD SiO2 layer.

Compared to epitaxy, silicon growth on a SiO2 covered surface has to be performed at lowertemperatures in order to prevent a decomposition of the silicon dioxide by hydrogen and therefore adamage of the dielectric layer. The process temperature was fixed to 950°C for the optimizationprocedure.

Silicon deposition at low temperatures is determined by reaction kinetics and consequently growthrates are comparatively low and depletion can already be avoided by comparatively low precursor gasflows. In return, the maximum dopant partial pressure and therefore the maximum dopantconcentration which can be achieved in the deposited layer is increased. This effect is beneficial forthe later function of the layer as BSF within the solar cell.

In principle, silicon deposition on foreign substrates can also be carried out at high temperaturesprovided that the substrate material remains mechanically and chemically stable. In this case, highdopant gas flow rates are necessary to achieve the required doping level.

4.3.1 Thickness uniformityThe growth rate distribution across the deposition area was quantified by thickness measurements oncross sections according to the method described in section 4.1.1. Equivalent to the optimizationprocedure for epitaxial layers, the effect of gas inlet geometry, total gas flow and process gascomposition was evaluated by systematic variation of these parameters.

The application of the nozzle had a similar effect on thickness homogeneity as already seen for theepitaxy process: the lateral distribution was improved and the deposition zone shifted towards the gasinlet. Therefore the nozzle was used for further optimization.

Figure 4.17 illustrates a deposition series with fixed partial pressures of the process gas componentsbut different total gas flow, the latter increasing from top to bottom. For constant Cl/H-ratio the effectof total gas flow rate or equivalently trichlorosilane gas flow rate on the thickness distribution in gasflow direction is clearly visible. In the top graph of Figure 4.17 the process gas contained only 1 g/minof trichlorosilane, resulting in a depletion in gas flow direction and a distinct drop in growth rate fromcenter to the edges. The graph in the middle shows the best thickness uniformity in this series. Theprecursor gas flow is large enough to prevent depletion and the total gas flow rate is sufficient to

4.3 Silicon deposition on foreign substrates 55

achieve a comparatively good lateral uniformity. In the bottom graph of Figure 4.17 a large total gasflow rate was applied and the associated large heat capacity led to a cooling of the substrate regionnear the gas inlet and a downstream shift of the center of the deposition zone.

-80 -60 -40 -20-20

-10

0

10

20


Lat

eral

pos

ition

rel

. to

cent

er [m

m]

20 40 60 80

TCS = 1.0 g/min

H2i = 1.5 l/min

total = 1.7 l/min


020406080100

-80 -60 -40 -20-20

-10

0

10

20relativethickness [%]


Lat

eral

pos

ition

rel

. to

cent

er [m

m]

20 40 60 80

TCS = 2.0 g/min

H2i = 3.0 l/min

total = 3.3 l/min

020406080100

20 40 60 80

-80 -60 -40 -20-20

-10

0

10

20

TCS = 3.0 g/min

H2i = 4.5 l/min

total = 5.0 l/min


020406080100


Lat

eral

pos

ition

rel

. to

cent

er [m

m]

Figure 4.17: Maps of thickness distribution for silicon layers deposited at 950°C. The Cl/H ratio isfixed to 0.16 for all runs and the total gas flow rate increases from top to bottom. Themaximum growth rates were all in a similar range of 1 µm/min.

T [°C] 950

TCS [g/min] 2

H2i [l/min] 3

Cl/H 0.16

Gas inlet Nozzle

Average growth rate [µm/min]in uniform area

1.1

Table 4.2: Deposition parameters for optimized silicon growth process at low temperatures.


The best thickness uniformity was determined for the set of parameters listed in Table 4.2. Under theseconditions the mean standard deviation in layer thickness across an area of 40x90 mm² is 15%, similarto the epitaxial depositions. A mean growth rate of 1 µm/min was achieved.

In the RTCVD100, closed layers with a minimum thickness of approximately 5 µm can be grown.Below this critical value the surface is covered with single crystallites.

4.3.2 Doping of seeding layersSilicon growth on amorphous substrates generally results in a fine-grained crystal structure with grainsizes in the 1 µm range. In this case neither 4-point-probe measurements nor SRP can be applied for acharacterization of doping concentration.

To enable a determination of the doping level in polycrystalline silicon films, these layers wererecrystallized by ZMR. The resulting multicrystalline coarse grain structure enables the application ofSRP on a single large grain. Figure 4.18 shows the carrier concentration profile measured for such asample.

0 10 20 30 40 5010101011101210131014101510161017101810191020

SubstrateBSFBase

SiO2 layer

Car

rier d

ensi

ty [c

m-3]

Depth[µm]

Figure 4.18: Carrier density profile of a recrystallized and epitaxially thickened silicon layerdeposited on mc-Si substrate with SiO2 barrier layer (SRP).

The base layer of 35 µm thickness is followed by the highly doped recrystallized seeding layer (BSF).The silicon dioxide intermediate layer can clearly be identified as a 2 µm thick region of highresistivity. At a depth of 43 µm the onset of the highly doped substrate region is visible.

With respect to their function as BSF, the seeding layers were always deposited with the dopant gasflow adjusted to its maximum possible value. Under the process conditions optimized for thicknesshomogeneity a minimum specific resistivity of approximately 0.02 Ωcm was obtained.

4.4 Layer growth in RTCVD160In this section, first results achieved for the deposition of polycrystalline silicon layers in theRTCVD160 reactor are presented. The insight already gained on the characteristics of the deposition

4.4 Layer growth in RTCVD160 57

process especially with respect to the geometry of the reactor could be transferred from theRTCVD100 to the up-scaled reactor model.

First experiments were carried out using a quartz tube with round cross section for gas injection. Thegas inlet is not located in the center of the sample carrier front plate but at a height of 30 mm makingthe setup asymmetric. The deposition temperature was set to 950°C.

Figure 4.19 illustrates the presence of a cold finger extending from the gas inlet into the depositionarea. The top area of the first two samples seems to be affected by a roll back cell which might beassociated to the large total gas flow rate of 7.4 l/min. In general, the same correlation between processparameters and thickness distribution as discussed for the RTCVD100 were observed: using too littleprocess gas leads to a depletion and adjusting the total gas flow to small values gives a morepronounced drop in growth rate from centerline to the edge. On the other hand, a cold finger can onlybe avoided if gas flow rates are not too high. The choice of process parameters is in fact a compromisebetween these effects.

-140 -120 -100 -80 -60

20

40

60

80

H

eigt

h [m

m]

-40 -20 0 20 40

Distance from the center of the lamp field [mm]60 80 100 120 140

TCS = 14.0 g/min

H2i = 5.1 l/min

total = 7.4 l/min

020406080100


Figure 4.19: Map of relative thickness distribution on 3 wafers of 100x100 mm2 in size positioned inthe middle of the RTCVD160 reactor. A maximum growth rate of 1.2 µm/min wasmeasured.

At present, the best deposition process in terms of thickness uniformity results in a mean standarddeviation of 34% in growth rate across a deposition area of 90x90 mm2. Considering a smaller area of70x90mm² in the middle of the sample the standard deviation reduces to 14%.

From the experience gained on characterizing deposition processes in the RTCVD100, it seems to beclear that a sufficient thickness uniformity across the deposition zone can only be achieved, if a moreefficient gas distribution system is used. For this aim, perforated silicon masks were designed whichcan be inserted into the sample carrier acting as shower heads. The total area covered by holes wasadapted to the cross section of the inlet tube to avoid any overpressure. Alternatively a nozzle can alsobe used for gas distribution. The benefits to be gained from these modified setups are currently subjectof further optimization procedures.

The suitability of the deposited silicon layers for zone melting recystallization has been successfullytested. Figure 4.20 shows the image of a recrystallized silicon layer on a 100x100 mm2 substrate. Thewidth of the recrystallized area depends on the width of the melting zone as indicated in the figure.


Figure 4.20: Recrystallized silicon seeding layer on a 100x100 mm2 sample. The deposition of thesilicon layer has been done in the RTCVD160 reactor.

4.5 SummaryCharacterization methods suitable for a complete analysis of silicon epitaxial layers and polysiliconlayers were evaluated. A combination of thickness profiling and 4-point probe mapping is presented asan effective tool for a fast and efficient characterization of thickness and dopant homogeneity on largearea samples.

The epitaxy deposition process in the RTCVD100 was optimized in terms of thickness uniformitywhich could be quantified to 13% across a deposition area of 40x100 mm² for optimized processconditions. The dependence of doping concentration on dopant gas flow was determined over twoorders of magnitude and a doping homogeneity of 11% across the deposition area could be defined,independent from dopant gas flow and deposition process. The possible doping range for epilayersextends from 5x1015 cm-3 to 1.5x1018 cm-3 with the maximum doping density being limited by theoperation range of the diborane mass flow controller. Defect densities below 1x104 cm-2 and effectiveminority carrier lifetimes up to 7.5 µs for a 30 µm thick epilayer of 0.5 Ωcm resistivity indicate a highcrystal quality of the epilayers indifferent of growth rate. Carbon and oxygen concentration below1x1016 cm-3 were measured by SIMS in epilayers on high-resistivity FZ-Si substrates.

The entire characterization procedure was carried out for two epitaxy processes, differing in growthrate by a factor 1.6. Using the fast growth mode, an average deposition rate of up to 9 µm/min can beachieved. Thickness and doping uniformity as well as defect density, impurity concentration andcarrier lifetime are comparable for both process types.

As a result of the extensive characterization and optimization procedure, high purity epilayers withwell defined properties and mean growth rates up to 9 µm/min can now be deposited in theRTCVD100.

For the deposition of silicon layers on foreign substrates at low temperatures the thicknesshomogeneity could be optimized to 15% across a deposition area of 40x100 mm². A minimumresistivity of 0.02 Ωcm was reached using maximum dopant gas flow.

4.5 Summary 59

First experiments were run in the RTCVD160 reactor and the CVD process for seeding layerdeposition was characterized in terms of thickness homogeneity. The layers proved to be well suitablefor zone melting recrystallization.

For both reactor types the geometry of the gas inlet was identified to have a detrimental effect ongrowth rate homogeneity. An improved gas distribution and consequently thickness uniformity couldbe achieved by the application of a nozzle and masks similar to a showerhead.

61

5 Doping of epitaxial silicon layers

The application of epitaxially grown doped silicon layers for semiconductordevices originates in the integrated circuit technologies. Unlike conventionaldoping techniques like diffusion or ion implantation CVD allows thefabrication of silicon layers with well controlled doping concentrationprofiles and doping levels on any kind of silicon substrate withoutintroducing any damage to the silicon crystal. With CVD the growth oflightly doped layers over heavily doped substrates is possible.

A short introduction on the theory of dopant incorporation is given in thefirst section and the functional dependence between doping level andprocess parameters is pointed out. Subsequently boron diffusion from thegas phase, autodoping and memory effect are described based onexperimental results. Main emphasis is put on the discussion of differentshapes of doping profiles which were obtained in dependence on processconditions in the RTCVD100. Finally, the effect of different doping profileson the performance of epitaxial solar cells is evaluated by means of devicesimulation. The chapter closes with a discussion of the gas system of theRTCVD100 and a proposal for an improved design.

5.1 Dopant incorporationThe request for growing epitaxial silicon layers with well defined doping concentrations and profilesmakes an understanding of the dopant incorporation process necessary. Similar to silicon depositionthe process of dopant incorporation can be described by the following steps: transport of dopant gas tothe substrate surface, adsorption of the dopant molecules, chemical decomposition and incorporation,and finally desorption of byproducts [41], [90]. A detailed comprehension of the chemical reactionstaking place on the substrate surface is still a topic of research.

The amount of dopant incorporated during silicon deposition is known to depend on processparameters like temperature, growth rate and partial pressure of the process gases. In literature thisdependence is often modeled by the following equation [91], [52], [79]:

0

0

),(Si

dopanteffdopant p

pvTKC = , 10 ≤≤ effK (5.1)

where Cdopant denotes the dopant concentration in the deposited silicon film, p0Si and p0

dopant are thepartial pressures of silicon and dopant containing process gases and Keff is the effective segregationcoefficient, which depends only on temperature and growth rate for low dopant concentrations [92].Keff can be regarded as a measure for the effectiveness of dopant incorporation, assuming that theincorporation efficiency for silicon is always equal to 1. In the limiting case Keff =1 all the dopantatoms reaching the substrate surface are built into the growing film. For Keff <1 only a fraction of

5 Doping of epitaxial silicon layers62

atoms is incorporated, the rest being rejected from the surface. According to this model the carrierconcentration in the growing film is linear with the partial pressure of the dopant gas.

Depending on the type of dopant the incorporation efficiency shows different characteristics. In caseof B2H6 the dopant concentration is known to increase with rising temperature whereas for PH3 orAsH3 the dopant incorporation decreases [91], [93]. Figure 5.1 shows the phosphorus dopingconcentration in epitaxial silicon as a function of temperature, growth rate and dopant partial pressurefor a PH3-SiH4 system [94], pointing out the complexity of the incorporation mechanism.

Figure 5.1: Doping concentration in epitaxial layers as a function of temperature for different PH3

partial pressures and silicon growth rates [94].

In [41] a model describing the mechanisms of boron incorporation is developed for a B2H6-SiHCl3-H2

system at atmospheric pressure. The model is based on a competitive incorporation of silicon andboron during the growth process and further assumes a negligible desorption rate of boron atoms fromthe silicon substrate surface due to the low concentration of diborane gas. The dopant concentration inthe epitaxial silicon layer is defined as

SiB

BSiB NN

NCC+

= , ][2 62 HBkN aB = (5.2)

where CB and CSi denote the density of boron and silicon atoms in the grown silicon film, respectively.NSi is the molecular deposition rate of the silicon crystal and correspondingly NB describes the borondeposition rate. [B2H6] denotes the molecular diborane concentration. ka is the overall rate constant ofthe boron incorporation process and is assumed to depend on the ratio of the silicon substrate surfaceoccupied by chemisorbed SiCl2 molecules:

ova kkk Θ+Θ−= )1( (5.3)

5.1 Dopant incorporation 63

kv and ko denote the rate constants for the chemical reaction of diborane molecules on vacant andoccupied surface sites respectively. Θ represents the fraction surface states occupied by SiCl2. Incontrast to diborane molecules, the TCS-molecules are assumed to react only on vacant surface sitesleading to a competition for these states between both species. Thus the boron deposition rate does notonly depend on the boron concentration but also on the SiHCl3 and H2 concentration.

In [48] a functional dependence between the silicon growth rate NSi, temperature and Cl/H ratio isgiven. Taking this into consideration, the effect of temperature and growth rate on dopantincorporation are clearly specified through eqn. (5.2), in contrast to the model described by eqn. (5.1).

Based on experimental results Habuka reports a decrease in carrier concentration with increasingsilicon deposition rate, for fixed diborane concentration [41]. Furthermore, similar to eqn. (5.1) alinear increase of carrier concentration was observed for an increasing concentration of diborane.Comparing experimental results with numerical calculations, the proposed model could be verified forlow Cl/H-ratios and within a temperature range of 950-1050°C. For the numerical simulation ofdoping densities in epitaxial layers the transport phenomena in a horizontal cold-wall reactor weretaken into account.

To determine the dependence between process parameters and epilayer carrier concentration for theRTCVD100 reactor, experiments with varying diborane gas flow were carried out. The depositionswere done using two different epitaxy processes (A and B) which have already been presented inchapter 4. The main difference between the two processes is the total gas flow and composition andtherefore the growth rate. Process A and B yield growth rates of 5-6 µm/min and 9-10 µm/minrespectively, corresponding to a difference by factor of 1.6. The diborane gas flow was varied within arange of 1 sccm to the maximum possible gas flow of 50 sccm. Diborane diluted to 2500 ppm inhydrogen was used for all experiments. The minority carrier concentration in the epilayers wasanalyzed by spreading resistance measurements, always assuming that the measured carrierconcentration equals the concentration of incorporated boron atoms. Figure 5.2 shows carrier densitiesmeasured in epilayers as a function of boron concentration in the process gas for both epitaxyprocesses.

All data points can be fitted by one single curve independent from the applied deposition process. Agood fit is obtained for

)][log(17.0])log([41.154.16~)log( 26262 HBHBCB ×−×+ (5.4)

In a first order approximation the fit curve shows a superlinear dependence of the carrier density onthe boron concentration at the inlet:

41.162

16 ][1047.3~ HBCB × (5.5)

This interrelation shows that under the prevailing conditions the minority carrier concentration in theepilayer does not depend on the silicon growth rate.

For an interpretation of these results with respect to the observations made in [41] the processconditions under which the experiments were carried out have to be compared and the assumptionsmade for the modeling have to be considered. The discussed model of boron incorporation presentedby Habuka is based on a conventional CVD process, run in the reaction-limited regime. The TCS ishighly diluted in hydrogen and large process gas flows are used. In [41] silicon depositions werecarried out using process gas mixtures with TCS concentrations of 0.9-3.5% of H2 gas corresponding


to Cl/H-ratios in the range of 0.01-0.05 and mean molecular weights between 3.2x10-3-6.7x10-3

kg mol-1. The deposition temperature ranged from 950-1050°C with deposition rates between 1-3 µm/min. For boron doping the diborane concentration at the inlet was varied between 1x10-4-1 ppm.Consequently a negligible interaction between TCS and diborane molecules was assumed and for bothspecies the binary diffusion coefficient in hydrogen was used to describe the diffusion forced by theconcentration gradient.

0.1 1 101015

1016

1017

1018

1019

Car

rier d

ensi

ty [c

m-3]

B2H6 concentration at the inlet [ppm]

Process A Process B Fit: y =1016.54*x1.41

Figure 5.2: Measured carrier densities for epilayers of process A and B graphed against the diboraneconcentration in the process gas. All data points can be fitted by one curve withsuperlinear characteristics.

Within this work, process gas compositions with Cl/H-ratio of 0.75 and 0.43 for process A and Brespectively have been used with mean molecular weights of 5.5x10-2 kg mol-1 and 3.5x10-2 kg mol-1.In this case, TCS and hydrogen make up a similar mole fraction of the entire process gas. For processA and B the TCS concentration can be determined to 40% and 25% of the total gas respectively. Theproperties of the process gas mixture are no longer dominated by the properties of hydrogen but issignificantly influenced by the TCS species. The depositions were carried out at a temperature of1170°C with growth rates ranging from 5-6 µm/min for process A and 9-10 µm/min for process B.Diborane concentrations between 0.1-25 ppm have been applied.

Compared to [41], silicon depositions in the RTCVD100 were carried out in a regime, where thegrowth rate is no longer limited by adsorption but by reaction kinetics. Cl/H-ratio, mean molecularweight of the gas composition and diborane concentration are by one order of magnitude larger for thedepositions in the RTCVD100 compared to the commercial reactor used in [41]. In addition, asubstantially higher process temperature has been applied. Altogether, gas flow dynamics and reactionkinetics can be expected to be different for both systems and deviations from the model for dopantincorporation presented in [41] can be expected.

For the development of a theoretical model to describe the mechanism of dopant incorporation leadingto the observed carrier concentrations, additional experiments e.g. with varying growth rate andtemperature are necessary.

5.2 Doping profiles of epitaxial layers 65

5.2 Doping profiles of epitaxial layersThe characteristics of a typical doping profile in epitaxial layers is determined by a transition zonebetween substrate and epilayer where the doping level of the substrate gradually approaches thedoping level of the epitaxial layer. In microsystem technology sharp transitions and thin epilayers arerequired for an optimal performance of the devices [73], [95]. In crystalline silicon thin-film solar celltechnology the demands on the width of the transition region are less critical.

In general, a step-like change in dopant gas flow does not result in an equally abrupt change in carrierdensity in the growing film, because a finite amount of time is needed to establish a new steady-stateof dopant concentration in the gas phase [96]. The region between the initial and final constant dopingconcentration reflects the gradual change in partial pressure of the dopant containing gas during thedeposition process. This transient is commonly referred to as transition region.

An ideal transition zone is only characterized by the time which is needed to establish a stable gasphase after changing the dopant partial pressure. Realistic transients are additionally affected by solid-state diffusion and autodoping [37], [52].

Solid-state diffusion occurs if e.g. the deposited epilayer features a doping density different from theunderlying substrate. Assuming the deposition of a lightly doped layer on a heavily doped substrate,the substrate can in a first approximation be taken as an inexhaustible source for dopant atoms and thedoping concentration by solid-state diffusion can therefore be described by a complementary errorfunction depending on location x and diffusion time t:

)2

(),( 0 DtxerfcCtxC = (5.6)

where C0 and D denote initial substrate concentration and diffusion coefficient of the dopant species.

The traditional model for autodoping is based on the evaporation of dopant atoms from the surface ofthe wafers inside the reactor during the heating ramp and the high-temperature prebake and theirintroduction into the gas stream. Part of these atoms can be re-incorporated into the growing film,giving rise to an unintentional doping of the epilayer [97].

Other additional dopant sources are the back of the wafers and the surrounding reactor. For the growthof lightly doped layers on heavily doped substrates, the constant background doping coming from thedeposition system is the limiting factor for the maximum resistivity to be reached (assuming pureprocess gases).

Figure 5.3 shows schematics of intended (left) and actual (right) doping profiles for an intrinsicepilayer grown on a heavily doped substrate. The components of unintentional doping are highlighted.

Common methods to decrease the effect of boron autodoping include e.g.

• Low bake temperature and time

• Reduced process pressure to decrease gas residence time

• Rapid thermal processing i.e. fast heating and cooling ramps

• Low deposition temperature

• Backsealing of the samples.


Intended doping profile Actual doping profile

Figure 5.3: Intended (left) and actual (right) doping profile in an intrinsic epitaxial film deposited ona heavily doped substrate. Sources of unintended doping: (1) Solid-state out diffusion,(2) Autodoping, (3) Background doping [96].

5.3 Experimental carrier concentration profilesThe following paragraphs deal with the characteristics of doping profiles in epitaxial silicon layersgrown under different epitaxy process conditions. The depositions were carried out in the RTCVD100reactor using epitaxy process B (fast growth mode). All substrates were p-type boron doped with a<100> crystal orientation. Unless otherwise stated, the substrates were not polished and a damage etchhas been applied before epitaxy.

5.3.1 Boron diffusion and evaporationThe first basic experiments on doping profiles focused on the intentional diffusion of boron from B2H6

into the silicon wafers at high temperatures. FZ-Si and Cz-Si substrates with a specific resistivityexceeding 10 Ωcm and below 0.02 Ωcm respectively have been used as test wafers.

The applied diffusion process followed the standard deposition process in terms of purge time, heatingand cooling ramps and gas stabilization. Diffusion temperature, time, diborane and hydrogen gas flowrate were set to 1170°C, 5 min, 50 sccm and 8 slm respectively. The diffusion processes were followedby a 1.5 min reactor-purge at 1170°C and a 1 min annealing step at 1200°C under hydrogen. Figure5.4 shows the carrier concentration profiles measured by SRP after the diffusion process.

Both carrier density profiles show a distinct increase in doping concentration towards the surface ofthe sample. The increasing slope is restricted to a surface-near region of about 1.5 µm with a peakconcentration in the range of 6x1019 cm-3 for the high resistivity substrate and slightly below for thelow resistivity sample.

The profiles verify that a diffusion of boron from the gas phase has occurred during the high-temperature step. While the carrier concentration profile of the high resistivity sample shows a Gausslike characteristic, the profile is rather flat for the low resistivity sample. SIMS measurements are

5.3 Experimental carrier concentration profiles 67

necessary to verify whether this difference is caused by electrical inactivity of boron in case of theheavily doped substrate or is related to the diffusion mechanism of boron in silicon [98], [77].

0.0 0.5 1.0 1.5 2.0 2.5 3.01014

1015

1016

1017

1018

1019

1020

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Substrate [Ωcm] > 10 < 0.02

Figure 5.4: Carrier concentration profiles measured after high-temperature boron diffusion from thegas phase containing B2H6 and H2.

The diffusion of boron from the vapor-phase is only little discussed in literature. In [99] this methodhas been used for the preparation of shallow MOS base structures. Similar to the experiment describedin this section the diffusion was carried out in an APCVD reactor using B2H6 as a dopant source attemperatures between 800-900°C. Under these conditions the carrier concentration was found toincrease with increasing dopant gas flow rate and diffusion time. For carrier concentrations exceedinga value of about 1x1019 cm-3 the boron concentration exceeded the carrier concentration, i.e. part of theboron atoms was not activated. In [100] the diffusion of boron from B2H6 in a UHV-CVD apparatuswith subsequent RTA (rapid thermal anneal) is presented as a novel technology for the preparation ofultra-shallow junctions for MOSFET devices. However, the boron diffusion mechanisms are notinvestigated in either publication.

To gain more insight on the diffusion of boron from the vapor-phase additional experiments have to becarried out in the RTCVD100. The dependence of carrier concentration and boron diffusion profileson the sample position in the reactor, diffusion time and temperature and diborane concentration in thegas phase have to be determined.

In a second experiment, the inverse process – diffusion of boron atoms from the bulk of the sample tothe surface and evaporation into the gas phase – was studied. The diffusion process has been testedusing again a high resistivity FZ-Si and a low resistivity Cz-Si sample in separate runs. Prior to eachexperiment, the reactor and the dummy wafers were capped by a doped silicon layer in order togenerate standard deposition process conditions. After heating up to 1170°C, the substrates wereannealed for 5 min under pure hydrogen. Figure 5.5 shows the carrier concentration profiles of bothsample types after anneal.


Considering the low resistivity sample, the doping concentration decreases towards the surface. Basedon the SRP data, the integrated boron dose loss was calculated to 1.4x1014 cm-2. This result verifiesthat during the high-temperature process step, boron atoms can in fact evaporate from the samplesurface.

For the high resistivity sample, the carrier density increases from 8x1014 cm-3 in the substrate to a peakconcentration of 1x1016 cm-3 at the surface. In this case, a diffusion of boron into the substrate hasoccurred. Since no diborane has been injected, the diffused boron atoms must originate from thesurrounding. During the heating- and cooling-ramp and the high-temperature bake, boron canevaporate from the surrounding dummy wafers and quartz carrier, which have been intentionallycapped by a doped silicon layer. A subsequent adsorption of boron species on the surface of the lowlydoped test wafer and diffusion of boron into the bulk results in the observed doping profile. Theintegrated dose across the diffused region of the high resistivity sample is by almost 4 magnitudeslower compared to the case of intentional diffusion of boron from B2H6.

0.0 0.5 1.0 1.5 2.0 2.5 3.01014

1015

1016

1017

1018

1019

1020

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Substrate [Ωcm] > 10 < 0.02

Figure 5.5: Carrier concentration profiles measured after high-temperature anneal under hydrogen.

The experimental results show that depending on the specific resistivity of the substrates and the boronconcentration in the surrounding atmosphere, a diffusion of boron can occur either from the gas phaseinto the bulk of the sample or vice versa if the sample is subjected to a high-temperature anneal. For aquantification of the influence of process conditions like bake temperature and time, hydrogen gasflow, doping concentration of the test sample and of the surrounding on the diffusion process of boron,additional experiments have to be carried out.

5.3.2 Background doping and memory effectTo evaluate the contribution to epilayer carrier density coming from a constant background doping,intrinsic silicon layers have been grown on silicon substrates of different resistivity. To exclude anycontamination from parasitic deposits on the quartz carrier or quartz tube these parts were wetchemically cleaned and baked in hydrogen before the depositions were carried out. Quartz carrier anddummy wafers which were used for the experiment were capped with an intrinsic silicon CVD layer.


The test wafers were used in the order of increasing doping level to exclude any memory effects fromproceeding samples. Figure 5.6 shows the measured carrier concentration profiles for intrinsicepilayers grown on different silicon substrates.

All curves in Figure 5.6 (left) show the same characteristic: the carrier concentration profiles consist ofa steep drop until a concentration of approximately 3x1014 cm-3 is reached, followed by a more gradualdecrease and a dip before the final constant doping level is approached. For each substrate type theminimum carrier density in the dip is located at 6-7x1012 cm-3 and the final epilayer dopingconcentration reaches a constant value of 1x1014 cm-3. The whole transition region from substrate untilthe constant part of the profile begins, expands over 7-8 µm for all depositions (Figure 5.6, right). Theon-substrate steep decrease is not present for the substrate of 100 Ωcm resistivity.

25 30 35 40 45 501012

1013

1014

1015

1016

1017

1018

1019

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

ρsub [Ωcm] < 0.02 1 > 10 100

32 34 36 38 40 42 44 461012

1013

1014

1015

1016

1017

transition region

ρsub [Ωcm] 1

constant doping

substrate

Depth [µm]

Figure 5.6: Carrier concentration profiles of intrinsic epilayers deposited on silicon substrates ofdifferent resistivity.

The independence of the measured profiles on the resistivity of the substrates indicates a negligibledopant contribution from the backside or edges of the samples. All epitaxial layers are p-type with acarrier concentration of 1x1014 cm-3, representing the background doping level. Interpolating theempirical function given in eqn. (5.5), a diborane concentration of 16 ppb is necessary to produce thisdoping concentration. A contamination through impurities present in the trichlorosilane can beexcluded since the trichlorosilane which has been used, is of electronic grade purity with a specifiedboron content below 0.1 ppba. Other sources for boron contamination may be the quartz carrier, thesurrounding quartz tube or the gas system.

Compared to the schematic doping profile illustrated in Figure 5.3, the experimental curves show adistinct dip in carrier concentration within the transition region. The interpretation of this characteristicis not straightforward and will be discussed in the next section.

To extract the influence of system memory effects on the carrier concentration of epilayers, twodepositions with a different conditioning process of the surrounding carrier and dummy wafers werecarried out. In the first case, an intrinsic pre-deposition was applied while in the second experiment thereaction chamber was conditioned by depositing a doped silicon layer. The resulting carrierconcentration profiles are shown in Figure 5.7.

zoom


The sample with intrinsic pre-deposition shows the same characteristics as in Figure 5.6 (right). Theconditioning of the reaction chamber by a doped silicon layer (doped predep.) resulted in a carrierdensity profile with on-substrate peak. The peak doping density was determined to 6x1015 cm-3. Theformation of the peak is assumed to result from a diffusion of adsorbed boron atoms from the surfaceinto the bulk of the sample during the heating-ramp and the prebake (see section 5.3.1) i.e. before thedeposition process begins. The adsorbed boron atoms are provided from boron evaporation of thedoped surrounding. The final shape of the peak is determined by solid state diffusion of boron fromthe peak into the lower doped neighboring regions during the deposition process and the followinghigh-temperature purge and annealing step.

10 12 14 16 18 20 22 241012

1013

1014

1015

1016

1017

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Reactor conditioning intrinsic predep. doped predep.

Figure 5.7: Influence of memory effect on the carrier concentration profiles of intrinsic epilayers.

To evaluate the impact of gas phase autodoping caused by the residence time of the dopant gas in thereactor system, a high-low doping deposition process was carried out where the growth of a lowresistivity epilayer was directly followed by the deposition of an intrinsic layer. The resulting carrierconcentration profile of the entire epilayer and the corresponding setting of the diborane gas flow rateare illustrated in Figure 5.8.

The abrupt change in diborane gas flow results in an immediate drop in carrier density, followed by asteady decrease. Within the deposition time of 2 min, the final steady state featuring a constant dopingconcentration of 1x1014 cm-3 was not reached.

The residence time of dopant gas in the reaction volume and in the gas lines determine the transition ofthe high-low junction. These parameters are intrinsic characteristics of each deposition system,depending on reactor geometry, gas inlet and gas system. The residence time of the process gas in theRTCVD100 reaction chamber is assumed to be comparatively short, due to the high total gas flowrates and the associated high gas velocities in the range of several 10 cm/s. The gradual decrease incarrier density is supposed to be mainly related to the design of the gas system (see section 5.3.4).After closing the diborane valve, the diborane gas line is still filled with dopant gas which slowlydiffuses into the main gas line feeding the reactor.


5 10 15 20 251015

1016

1017

1018

02468

10

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

B 2H6 [

sccm

]

Figure 5.8: Diborane gas flow rate set for a high-low doping deposition process (top) andcorresponding carrier density profile (bottom).

For the preparation of epitaxial silicon thin-film solar cells, epilayers with carrier concentrations in therange of 4x1016-1x1017 cm-3 are deposited onto highly doped substrates. Compared to theseconcentrations, the observed background and gas phase autodoping and memory effect are negligible.

5.3.3 Doping profile of intrinsic epilayersThe main features of a typical carrier concentration profile for intrinsic epilayers have already beenpresented in the previous section. The most prominent and unexpected characteristic is the dip incarrier concentration within the transition region between substrate and epilayer. This section aims todiscuss and explain possible mechanisms which can lead to the development of such a depression.

In general, there are two possibilities to explain the lack in carrier concentration: first, it is due to aphysical lack of boron atoms and second, the electrical activity of boron atoms in this region iseliminated or compensated. Both hypotheses are discussed in the following.

SIMS measurements were carried out to determine the actual boron content in the epilayer. In Figure5.9 SRP and corresponding SIMS profile are compared. The boron concentration in the substrateaccounts to 2.6x1016 cm-3 and exceeds the corresponding SRP value. In contrast to the SRPmeasurement, no dip in dopant concentration is visible near the interface, whereas the mean value forboron in the epilayer is in good agreement with the measured carrier concentration.

The deviation between boron and carrier concentration in the substrate might be caused by anelectrical inactivity of part of the boron atoms or might be associated to the SIMS measurementprinciple. A careful interpretation of the SIMS profile measured in the transition region is necessary:the detection limit for SIMS is in the same range as the doping density in the epilayer and in addition,the depth resolution typically deteriorates with increasing depth of measurement. For these reasons ithas to be taken into consideration that SIMS is probably not capable to detect the dip observed in SRPand no unambiguous information on the boron concentration in the dip region can be drawn.


7 6 5 4 3 2 1 0 -1

1013

1014

1015

1016


Dop

ant c

once

ntra

tion

[cm

-3] SRP

SIMS

Figure 5.9: Comparison of boron concentration measured by SIMS and corresponding carrierconcentration (SRP).

Physical lack of boron atoms

In the absence of intentionally injected dopant gas, background and gas phase autodoping determinethe dopant concentration in the epitaxial layers. To understand the formation of the dip, possiblemechanisms have to be found which are capable to explain, why at the beginning of the epitaxialgrowth process, no or only little boron is incorporated into the growing layer.

According to eqn. (5.5) the reduction in doping concentration from 1x1014 to 7x1012 cm-3 correspondsto a decrease in diborane concentration by a factor 6.6. If the incorporation of boron depends only onthe boron-concentration in the gas phase, the formation of the dip can either be achieved by a short-term reduction of boron-containing species or by an increase in trichlorosilane gas flow, assuming thehydrogen gas flow to be fixed. From a technical point of view, the latter scenario is less likely and forthe following considerations only the first possibility is regarded.

In the following the issues of gas transport and chemical consumption of boron species are addressedto give possible explanations for a sudden drop in boron concentration.

Transport

After heating and prebake, the reaction volume is in a state where the boron concentration in theatmosphere is determined by the evaporation of boron from carrier and wafers (assuming a negligiblecontribution from gas system or other parts of the reactor). The introduction of the process gasrepresents a perturbation of the present atmosphere and some time is needed until a steady state is re-established. The diffusion of boron atoms to the sample surface may be disturbed or even inhibitedduring this period. Based on these assumptions, the formation of the sink could be explained asfollows: immediately before the process gas enters the reactor, the system is in a quasi equilibriumwith boron atoms being adsorbed and desorbed on the sample surface. With the injection of theprocess gas, part of the boron species present in the gas atmosphere may be driven out of the systemby forced convection. On the other hand, boron which is adsorbed on the sample surface can beincorporated into the growing film. The on-substrate decreasing part of the dip reflects theconsumption of the limited amount of boron by incorporation. The abrupt disturbance of the gas phaseand the short “evacuation” of the atmosphere from boron species prevents a continuous supply of the


sample surface with boron. Assuming a growth rate of 9 µm/min, about 27 sec are needed to grow anepilayer thickness of 4 µm, i.e. after about 27 sec a constant boron concentration begins to establish inthe gas stream. However, with respect to the large gas velocities in the reaction chamber in the rangeof several 10 cm/s even at room temperature (total gas flow rate of 10 sl/min), the establishment of anew steady gas phase is supposed to occur on a much smaller time scale in the order of few seconds.

According to the presented assumption, a dip will develop every time the trichlorosilane is injectedinto the system. To verify this statement, an experiment has been carried out, where two intrinsiclayers were deposited within one run, the deposition steps only being separated by a 2 min hydrogenbake. An analysis of the doping profile showed that between substrate and first epilayer the typicaldeep dip had developed whereas between first and second epilayer only a minor depression in carrierconcentration is visible. This result is also in contradiction to the above presented transport theory.

Chemical consumption of boron

A mechanism known to consume boron or diborane is the chemical reaction of water vapor withreactive boron halides. The presence of water vapor and HCl in the reactor atmosphere has beenreported to influence the boron concentration in epitaxial layers [101]. It was found that for a fixedpartial pressure of diborane the boron concentration in the grown layer decreases with increasing watervapor concentration. A similar result has been obtained for the presence of HCl in the atmosphere. Atthermal equilibrium and high temperatures, BH2 is the dominant boron species in a gas phasecontaining only hydrogen and boron. Chemical reactions of this halide with Cl, HCl or H2O lead to aconsumption of this species [102], [101].

For a B-H and a B-H-O system in thermal equilibrium the gas phase composition was calculated usinga simulation program [53]. According to experimental conditions, a temperature of 1170°C and a totalpressure of 1 atm was assumed. Figure 5.10 shows the mole fractions of the dominant chemicalspecies calculated for different concentrations of diborane and water vapor.

0.1 1 1010-7

10-6

10-5

H2O = 0 ppm

BH3

BH2

H

Mol

e fra

ctio

n

B2H6 concentration [ppm]0.1 1 10 100

10-7

10-6

10-5

B2H6 = 1 ppm

BHO2

BHO

BH2

BH3

H

Mol

e fra

ctio

n

H2O concentration [ppm]

Figure 5.10: Gas phase composition of a B-H-O-system in thermal equilibrium for a total pressure of1 atm and a temperature of 1170°C.


If the humidity in the gas phase is set to zero, BH2 and BH3 are the most abundant compounds (Figure5.10, left) and the amount of both species increases with increasing initial diborane concentration. InFigure 5.10 (right) the initial diborane concentration is fixed to 1 ppm and the H2O concentration isvaried. For low concentrations of water vapor, BH2 and BH3 are still the dominating species. Withincreasing humidity, the mole fraction of oxygen containing boron halides rises rapidly on the expenseof BH2 and BH3. For H2O concentrations exceeding the diborane concentration, boron hydride oxide(BHO) dominates the gas phase composition. If the amount of water vapor is further increased, themole fractions of BH2 and BH3 become negligible and instead BHO and BHO2 (boric acid) are themost stable compounds. The same characteristics can be observed if the initial diborane concentrationis increased.

The simulation shows that in the presence of water vapor, diborane may in fact be used up bychemical reactions including hydrogen and oxygen. If the concentration of water vapor is greater thanthe diborane concentration, the reduction in boron halides becomes significant. Assuming that theresulting boric acids do not contribute to the incorporation of boron, the carrier concentration in agrowing epilayer may be reduced.

To explain the measured carrier density profiles according to this theory, it must be assumed thatduring the first stages of deposition, water vapor is introduced into the system e.g. through thetrichlorosilane, or that oxygen containing species cover the surface of the samples and impede theadsorption of boron-containing molecules. To reduce the background doping density of 1014 cm-3 byone order of magnitude, the diborane concentration must also be reduced by approximately the samefactor. With respect to the hypothesis presented in this section, this can be achieved if the partialpressure of water vapor in the reactor is greater than the partial pressure of diborane. Assuming abackground diborane concentration of 16 ppm, the concentration of water vapor must exceed thisvalue.

From a technical point of view the presence of water vapor in the trichlorosilane or the correspondinggas lines is difficult to detect and could not be investigated within this work.

During the heating-ramp and the high-temperature prebake, all oxygen should be removed from thereactor and the sample surface should be free from native oxide. Assuming an incomplete prebake, theresidual oxygen on the sample surface might hinder the adsorption of boron species and/or might reactwith the boron halides according to the presented reaction path way. In any case, the boronconcentration near the interface substrate/epilayer would be reduced.

First tests on the influence of prebake time and temperature were carried out with the results indicatingthat these parameters in fact influence the doping profile. Further experiments on prebake conditionsare needed to quantify their impact.

Compensation or electrical inactivity

Substitutional boron represents an acceptor state in the silicon crystal with the minority carrierconcentration depending on the boron content. In the presence of donors the hole concentration maybe reduced or even compensated thus lowering the p-type conductivity. Apart from group V impurityatoms, defects or thermal donors can act as donor states in the silicon crystal. Crystal defects disturbthe normal lattice order and can therefore introduce electrically active states of either kind in theforbidden band gap. A prominent source for donor states are different oxygen complexes known as


thermal donors or new donors [103]. An accumulation of either kind in an otherwise boron dopedregion may lead to a locally reduced minority carrier concentration.

The oxygen and carbon concentration in the epilayer and especially across the interface were analyzedby SIMS measurements. An accumulation of either impurity at the interface might lead to a highlydefected area, capable of trapping carriers or in case of oxygen enhance the formation of donors and inconsequence compensate the acceptor concentration at this site. Figure 5.11 shows SIMS profiles forboth elements. Although carbon and oxygen are present in high concentrations no irregularities arevisible at the interface.

The dip in carrier concentration has been observed in epilayers on substrates with high oxygen andcarbon concentrations but also on FZ-silicon substrates where the concentration of both elements isbelow 1x1016 cm-3. A dependence of the carrier concentration profile on the substrate concentration ofthese impurities can therefore be excluded.

6 4 2 0 -2 -4 -6

1017

1018

1019

Impu

rity

conc

entra

tion

[cm

-3]


oxygen carbon

epitaxy substrate

Figure 5.11: Oxygen and carbon concentration profile measured for epilayer and substrate (SIMS).

The epitaxial deposition of high resistivity layers on low resistivity substrates can result in anenhanced formation of crystal defects caused by the lattice mismatch between the differently dopedregions. The crystal structure at the epilayer/substrate interface was investigated by defect etching ofcross sections and in addition EBIC measurements were carried out on corresponding sample crosssections. Neither defect density nor recombination activity were found to be increased at the interface.

In conclusion, the observed dip in carrier concentration cannot be clearly attributed to any of theproposed mechanisms. Under the prevailing deposition conditions the width of the dip-regioncorresponds to a deposition time of approximately 50 sec assuming a constant deposition rate of9 µm/min. An investigation of the dependence of the local decrease in carrier concentration on processparameters (prebake conditions, growth rate, temperature) could give further insight on themechanisms responsible for the formation of the dip.


5.3.4 Standard epitaxyThe standard process for epitaxial deposition of doped silicon layers in the RTCVD100 consists ofheating the samples under hydrogen to the process temperature of 1170°C, prebaking for 1 min andsubsequent layer growth. In chapter 4 two epitaxy process A and B were described and characterized.The outstanding difference between process A and B is the growth rate, which is 5-6 µm/min forprocess A and 9-10 µm/min for process B. Now the carrier concentration profiles measured forepilayers grown via both processes are discussed in more detail.

Epitaxial layers of 30-40 µm thickness were deposited on highly-doped, polished Cz-Si substrates withvarying diborane flow rate. Figure 5.12 shows the carrier concentration profiles measured by SRP forboth epitaxy processes.

0 5 10 15 20 25 30 35 401011

1012

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1016

1017

1018

1019

Process AB2H6 [sccm]

1.5 2.0 10.0 50.0

Car

rier D

ensi

ty [c

m-3]

Depth [µm]0 5 10 15 20 25 30 35 40

1011

1012

1013

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1016

1017

1018

1019

Process BB2H6 [sccm]

2.0 5.0 10.0 50.0

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Figure 5.12: Carrier concentration profiles of epilayers deposited by epitaxy process A (left) and B(right) for different diborane gas flow rates.

All profiles show the same characteristics, independent from deposition process and dopant gas flow.The transition region can be separated into three regions: first, the carrier concentration decreases untila minimum is reached, then a steep increase follows and the final constant epilayer doping level isgradually approached. An exception to this characteristic is observed for a maximum diborane gasflow rate of 50 sccm. In this case, the substrate-near decrease in carrier concentration is missing andinstead a slight increase in visible. With decreasing dopant flow rate the substrate-near dip gets widerand deeper. About 1 µm before reaching the sample surface the carrier concentration rises again tovalues in the range of 1x1018 cm-3.

Transition region

The measured carrier concentration profiles in the transition region resemble the transients obtainedfor intrinsic epilayers (see section 5.3.3). However, while for all intrinsic layers the minimum waslocated at a constant carrier density of 7x1012 cm-3, the width of the dip and its depth now depend onthe diborane gas flow rate and silicon growth velocity or more general on the diborane inletconcentration. The dip with the lowest carrier concentration featured a density below 1012 cm-3, oneorder of magnitude smaller compared to the intrinsic case.


In order to control the actual boron concentration in the grown silicon film, SIMS measurements werecarried out. In Figure 5.13 a SIMS profile is compared to the corresponding SRP characteristics. Thecurves were adjusted to match the on-substrate slope.

0 2 4 6 8 10 12 14 161013

1014

1015

1016

1017

1018

Depth [µm]

D

opan

t con

cent

ratio

n [c

m-3]

SRP SIMS

Figure 5.13: Comparison of boron and carrier concentration profiles measured by SIMS and SRPrespectively for an epilayer grown on a highly doped substrate.

The boron concentrations measured for substrate and epilayer agree with the corresponding carrierconcentration measured by SRP. The SIMS profile reveals a sink in boron concentration confirmingthe SRP measurement. However, in case of SIMS the dopant density in the dip is by about 1.5magnitudes larger and expands over a smaller region compared to SRP. This deviation from SRP maybe attributed to an artefact of the SIMS measurement, where depth and concentration resolutiondecrease with increasing depth of measurement. The deeper the sputter crater, the larger is theinfluence of additional signals coming from the borders of the crater. This effect is pronounced incases where the boron concentration decreases with increasing depth. In Figure 5.13 the boronconcentration measured in the dip may be influenced by the top layer where the boron content is muchlarger.

In contrast to the intrinsic layers, the decrease in carrier density observed in SRP measurements cannow be definitely related to a lack in boron concentration.

The transition from the dip to the region of constant doping density can be separated in a steepincrease followed by a more gradual rise in carrier concentration. Compared to this, the dip appearedto be more or less symmetric for the intrinsic case. Considering the carrier density profile under theaspect of dopant concentration in the gas phase, the steep rise reflects a sudden change in diboraneconcentration while the gradual slope marks a slow establishment of the final state of quasi-equilibrium.

Figure 5.14 shows an extract of the gas system, in particular the course of diborane, trichlorosilane andhydrogen gas lines. Starting from the valve, the diborane gas line crosses the hydrogen line after alength of 85 mm. This gas mixture combines with the trichlorosilane gas line after another 190 mmlength. The length of the TCS gas line from valve to nodal point comes up to only 25 mm. Since thehydrogen gas flow is typically by a factor 100 larger compared to the diborane gas flow, the velocity


of the diborane/hydrogen mixture is determined by the hydrogen gas flow. Assuming a simultaneousoperation of diborane and TCS valve the time for the diborane to reach the nodal point can becalculated from the volume of the diborane gas line, which is approximately 1.1 cm3, and the diboranegas flow rate.

190mm

85m

m

25m

m

B2H6

H2

SiHCl3valve

reactor

B2H6 mixes with SiHCl3(nodal point)

Figure 5.14: Extract of the RTCVD100 gas system featuring the connection of the process gas lines.

In Table 5.1 the calculated delay times for different diborane gas flow rates are listed. The delay refersto the difference in time between the arrival of TCS and diborane at the nodal point. The larger thediborane gas flow the shorter is the delay. By the time the diborane reaches the reactor, the silicondeposition process has already started. With respect to the two epitaxy processes, the thickness of theepilayer which can grow until the diborane reaches the reactor is also calculated (dA, dB).

B2H6 tdelay dA dB

[sccm/min] [sec] [µm] [µm]

1 64 5.9 9.6

2 32 2.9 4.8

5 13 1.2 1.9

10 6 0.6 0.96

50 1 0.13 0.19

Table 5.1: Diborane delay times and corresponding layer thickness for different diborane flowrates. Growth rates of 5.5 µm and 9 µm have been assumed for process A and Brespectively.

The epilayer between the substrate surface and the minimum of the dip corresponds to the intrinsicfilm which can grow during the delay time. The width of this region decreases linearly with increasingdiborane concentration or increasing silicon growth rate (Figure 5.12). The calculated delay times andthe corresponding layer thickness show the same characteristic and a correlation between both featuresis obvious.

To verify the effect of the gas system on the carrier density profile in epilayers, experiments werecarried out where the operation point of the diborane valve was adjusted to enable a simultaneous


arrival of trichlorosilane and diborane at the nodal point. This synchronization was achieved by an intime manual operation of the diborane gas valve.

Figure 5.15 shows a comparison between carrier concentration profiles measured for standardepilayers (process B) with a delayed introduction of diborane gas and for epilayers where the delaywas compensated by an in time operation of the diborane gas valve.

5 10 15 20 25 301011

1012

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1016

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B2H6=2 sccm B2H6 delayed B2H6 delay eliminated

Car

rier D

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ty [c

m-3]

Depth [µm]5 10 15 20 25 30

1011

1012

1013

1014

1015

1016

1017

1018

1019

B2H6=5 sccm B2H6 delayed B2H6 delay eliminatedC

arrie

r Den

sity

[cm

-3]

Depth [µm]

Figure 5.15: Carrier concentration profiles for epilayers grown with (delayed) and without (delayeliminated) a delayed injection of diborane relative to trichlorosilane (SRP). Twodifferent diborane concentrations are considered.

As a result of the earlier operation of the diborane gas valve, the steep slope from sink to constantepilayer doping level has disappeared, verifying the impact of the gas system on the doping profiles.The gradual rise of the carrier concentration remains almost unchanged indicating that an additionaleffect must be present.

The experiments described in this section prove that the dip in carrier concentration can be partlytraced back to a delayed injection of diborane relative to trichlorosilane in case of intentionally dopedepilayers. For the construction of future CVD reactors, a change of the gas system is necessary toprevent delay times between different process gases.

Similar to the intrinsic case, the transition region still features a depression in carrier concentration anda very gradual approach of the constant epilayer doping level, even if the delay time of diborane iscompensated. A slow establishment of constant gas phase composition and deposition process, anincomplete prebake procedure or water vapor present in the atmosphere may be responsible for thisphenomenon.

Surface-near peak

In Figure 5.16 the surface-near carrier density profiles for process A are depicted for three differentdiborane gas flow rates. The characteristics show that the width and the height of the surface-nearpeak depends on the diborane gas flow rate: the larger the gas flow, the higher the maximum carrierdensity and the wider the peak. The same features are observed for process B.

The presence of a peak in doping concentration at the epilayer surface is assumed to be a result of thedelayed operation of the diborane valve, combined with a long residence time of the diborane in the


reaction volume or in the gas system. The moment the TCS valve is closed, diborane is still injectedinto the reactor at full flow rate while the TCS gas flow quickly diminishes. The prevailing hightemperature and the following anneal at 1200°C facilitates a diffusion of residual boron into the grownepilayer.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.61015

1016

1017

1018

1019

1020

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Process AB2H6 [sccm]

2 5 10

Figure 5.16: Surface-near carrier concentration profiles for different diborane gas flow rates.

5.3.5 Deposition with pre-epitaxial diffusionThe standard epitaxy process (type B) was modified in terms of an additional vapor-phase diffusion ofboron prior to the beginning of the growth process. For this aim, the diborane gas valve was manuallyopened 60 sec in advance of the TCS valve. While the diborane gas flow was fixed to 10 sccm for thegrowth of the epilayer, it was varied between 10-50 sccm for the pre-epitaxial diffusion step. Thecorresponding carrier concentration profiles are depicted in Figure 5.17.

20 21 22 23 24 25

1017

1018

1019

substrateepitaxy

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Pre-diffusionB2H6 [sccm]

10 25 50

Figure 5.17: Carrier concentration profiles for epilayers with pre-epitaxial diffusion of boron (SRP).The pre-diffusion was carried out for 60 sec with variable diborane gas flow rate.


The implementation of a boron diffusion step resulted in the formation of a peak between the regionsof constant doping level. The width and the height of the peak increases with increasing diborane gasflow. The transition from the peak to the substrate side of the profile features a slow decrease in carrierconcentration while the transient from peak to epilayer is much steeper.

The observed characteristic can be explained as follows: prior to the onset of the deposition, thereaction volume is flooded with diborane and according to section 5.3.1 a diffusion of boron atomsfrom the gas phase into the bulk of the sample can occur. The gradual rise from substrate to peakreflects this process. The width and the height of the peak depend on the diborane gas flow rateapplied during the diffusion step: the greater the dopant gas flow the larger is the amount of boronspecies adsorbed on the sample surface and the more boron can diffuse into the bulk.

The opening of the TCS valve and the simultaneous change in diborane gas flow determine thebeginning of the deposition step and the abrupt decrease in carrier concentration reflects the associatedchange in gas composition. Solid-state out diffusion and the establishment of a steady state in the gasphase determine the transient from diffusion peak to constant epilayer doping. The transient is about1.5 µm wide, indicating a fast generation of a steady state in the changed gas phase and a negligibleautodoping effect.

The situation discussed here is similar to the experiment carried out to determine the memory effect(section 5.3.2). The difference between the two experiments lies in the different boron sources and thedifferent dopant concentrations in the gas atmosphere at the onset of the deposition process. For theautodoping-experiment the boron content in the vapor-phase resulted only from an evaporation of thesurrounding system. Now, the atmosphere was intentionally over-saturated by the introduction ofdiborane. In both cases, a diffusion of boron into the bulk of the sample takes place.

5.3.6 High-low depositionIn contrast to the standard deposition process a so-called high-low process consists of two subsequentgrowth steps differing in dopant gas flow rate. This deposition process is especially attractive if a p/p+-junction with low interface recombination velocity is to be accomplished. The direct deposition of a p-doped layer on a low resistivity substrate is known to enhance the formation of crystal defects due tothe lattice mismatch between the two regions. With the application of a high-low process, theelectrical interface can be separated from the crystallographic interface of epilayer and substrate andthe recombination velocity at the junction may therefore be reduced.

For epitaxial thin-film solar cells on highly doped substrates, low surface recombination velocities areessential and therefore high-low CVD processes are often used for the deposition of the base layer.Within the solar cell structure the heavily doped region acts as back surface field (BSF). Thisnomination will also be used in the following paragraph to denote the highly doped epilayer grownduring the first deposition step.

Experiments were carried out with the duration of the BSF deposition being varied between 5-20 secand the diborane gas flow held constant at the maximum value of 50 sccm. According to the cellstructure of epitaxial silicon thin-film solar cells, only highly-doped substrates have been used. Theresulting carrier concentration profiles are presented in Figure 5.18.

The characteristics in Figure 5.18 show, that an increase of the BSF deposition time from 5 to 20 secresults in the development of a separate on-substrate shoulder with its width and height increasing


with deposition time. The gradient of the on-substrate slope decreases with increasing BSF-time. Forthe 5 sec BSF the deposition time was too short for a full development of the shoulder. Instead, thetransient between substrate and epilayer is smooth.

18 19 20 21 22 23 24

1017

1018

1019

epitaxy substrate

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

BSF-time [sec] 5 10 20

Figure 5.18: Carrier concentration profiles measured for epilayers deposited by a high-low process(SRP). The diborane gas flow for BSF was fixed to 50 sccm.

The presence of a dip between substrate and peak indicates that a lowly doped epilayer must havebeen grown prior to the actual BSF-deposition. This cannot be explained by the retarded introductionof diborane, since the calculated delay time for a gas flow of 50 sccm comes up to 1 sec and assuminga growth rate of 9 µm/min this corresponds to an epilayer thickness of only 0.15 µm. Compared to thisvalue, the distance between minimum carrier concentration and substrate/epilayer interface isdetermined to approximately 1 µm (~7 sec growth time) from experimental profiles. In previoussections, possible mechanisms for the generation of a thin, high resistivity epilayer at the interfacebetween substrate and epilayer have already been discussed. These mechanisms also apply in this case.

The maximum doping density of the BSF layer is determined by the limited diborane gas flow ratewhich can be applied. With the application of epitaxy process B the doping density is thereforerestricted to values below 6x1017 cm-3. In future systems, an increase of the tunable dopant gas flowrange is necessary to enable the deposition of silicon layers with doping concentrations exceeding1019 cm-3. This feature would allow the controlled generation of high-low junctions at high depositionrates, with even larger doping gradients and improved BSF effect. In the RTCVD160 this demand isalready realized and maximum diborane gas flow rates of 1000 sccm can be used.

5.4 Effect of doping profile on solar cell performanceTo evaluate the effect of different doping profiles on solar cell performance, device simulation wascarried out using PC1D [126]. Two cases were compared: (1) Steep, step-like transition of dopingdensity between substrate and epilayer (ideal case) and (2) Dip between substrate and epilayer.

The minority carrier lifetime in the dip was assumed to be identical to the constant base region. Theshape of the dip was modeled by a fixed total width of 4 µm, while the minimum doping density in the

5.4 Effect of doping profile on solar cell performance 83

dip was varied. In Figure 5.19 (top, left) the doping density profiles used for the simulations are given.Dip 1 represents a situation, where the depth of the sink is only about one order of magnitude belowthe constant base doping level. A significant decrease in doping density is assumed for dip 2. Forcomparison the ideal case of a sharp transition was added.

The doping density in base layer and substrate were set to 5x1016 cm-3 and 4x1018 cm-3 respectively.The substrate was assumed to be 600 µm thick with a minority carrier diffusion length of 3 µm. Theinterface recombination velocity between substrate and epilayer was fixed to zero. These settings wereadjusted to match experimental values. For a detailed description of the simulated solar cell model seesection 6.2.8. Simulations were carried out with varying base lifetime and thickness.

Considering a sharp transition in doping concentration, a strong electric field builds up at the interfacebetween substrate and base which repels the minority carriers coming from the base (BSF-effect). Theinverse effect occurs if a dip is located between substrate and base: due to the low doping level in thedip, minority carriers in the base are accelerated towards the dip region where they get “trapped”.

24 25 26 27 28 29 30 311013

1014

1015

1016

1017

1018

1019

Sharp transition Dip 1 Dip 2

Dop

ing

dens

ity [c

m-3]

Depth [µm]10 20 30 40 50 60

-1.0

-0.5

0.0

0.5

1.0Efficiency [%]

Sharp transition

Base thickness [µm]

log(

τ base

) [µs

]

8.0009.00010.0011.0012.0013.0014.00

8.0 - 9.0 9.0 - 10.010.0 - 11.011.0 - 12.012.0 - 13.013.0 - 14.0

10 20 30 40 50 60-1.0

-0.5

0.0

0.5

1.0Dip 1


log(

τ base

) [µs

]

10 20 30 40 50 60-1.0

-0.5

0.0

0.5

1.0 Efficiency [%]

Dip 2


log(

τ base

) [µs

]

8.09.010.011.012.013.014.0

8.0 - 9.0 9.0 - 10.010.0 - 11.011.0 - 12.012.0 - 13.013.0 - 14.0

Figure 5.19: Top, left: Doping concentration profiles for simulated solar cells with sharp transitionand dip between substrate and epilayer. 3D-diagrams: Corresponding electricalefficiency as a function of base thickness and minority carrier lifetime for differentdoping concentration profiles.

Figure 5.19 (top, right) shows the efficiency diagram obtained for a step-like transient in dopingdensity. For minority carrier lifetimes below 1 µs (corresponding to a minority carrier diffusion length


of 46 µm) the performance of the solar cell is almost independent on the base thickness. In this case,the efficiency is limited by the quality of the base layer. For larger carrier lifetimes, the efficiencyincreases with base thickness: carriers generated at the back of the cell can reach the pn-junction andcontribute to the photocurrent.

Comparing the efficiency diagram for the sharp transition and the shallow dip 1, the existence of thedip results only in minor changes in efficiency for minority carrier lifetimes below 1 µs independentfrom base thickness. For greater lifetimes the minimum thickness to reach a certain efficiency shiftstowards larger values i.e. thicker layers are necessary to obtain similar efficiencies.

Increasing the depth of the dip (dip 2) leads to a further shift of efficiency boundaries towards thickerbase thickness and also toward greater lifetimes. The dependence of efficiency on base thickness forlow carrier lifetimes indicates an increased effect of the electrical attraction imposed by the sink ongenerated minority carriers.

5.5 Improved gas system designWithin the course of the experiments carried out on the issue of doping profiles in epitaxial layers, twoshortcomings of the gas system as implemented in the RTCVD100 have been revealed:

• A simultaneous operation of diborane and TCS valve results in a temporal delayed injection ofdiborane and TCS into the reaction chamber.

• After closing the diborane valve, the corresponding gas line is still filled with dopant gas whichslowly diffuses into the main gas stream.

To avoid the associated effects on carrier density profiles (e.g. dip and surface peak) the gas systemhas to be changed. The schematic in Figure 5.20 shows an outline of a future gas system.

B2H6

valve

reactor

other SiHCl3

H2, N2 purge

exhaust

H2i

a a a c

b b db

M

P

N2i

three-way valve

Figure 5.20: Schematic of improved gas system design.

The length of the gas lines denoted by small letter a, b, c and d have to be as short as possible toreduce the dead storage capacity.

Compared to the existing gas system, the improved design allows a common gas stabilization of thediborane (or any other dopant) and TCS mixture into the exhaust line. At the beginning of thedeposition process the three-way valve M is operated and the homogeneous gas mixture is introduced

5.6 Summary 85

into the reactor. Similarly a closing of the three-way valve, entirely cuts off the reactor from theprocess gas supply. A delayed or supplementary injection of any process gas can therefore be avoided.

A multilayer growth of epilayers of different doping types and sharp transitions can only be realized ifa hydrogen purge of the process gas lines is included in between separate deposition steps.Considering e.g. the subsequent growth of a p- and n-type layer, where the gas line denoted by “other”in Figure 5.20 is fed by the dopant gas PH3: a subsequent closing and opening of the diborane andphosphine valve respectively results in a delayed injection of an unstabilized phosphine gas flow intothe reactor. In addition, a supplementary diffusion of residual diborane occurs from the dead storagebetween diborane valve and main gas line into the process gas stream. Both effects counteract thegrowth of epilayers with sharp transients.

A solution to this problem is the separate deposition of layers of different doping-types. After eachdeposition step, all process gas valves are closed, the three-way valve M is opened to the exhaust andthe process gas line is purged by hydrogen. As soon as the gas lines are cleared from any residuals, thecorresponding process gas valves are opened and the new process gas mixture is stabilized into theexhaust before it is injected into the reaction chamber. During the gas-line purge and the gasstabilization the reactor is purged with hydrogen. This hydrogen purge step can only be avoided if amore complex gas system is used, where each dopant gas can be mixed with TCS in a separate gasline.

5.6 SummaryUnder the prevailing conditions for epitaxial deposition in the RTCVD100, the incorporated carrierconcentration of intentionally doped epilayers was observed to depend only on the diboraneconcentration in the initial gas mixture.

Intrinsic epilayers feature a p-type conductivity with a resistivity in the range of 100 Ωcm confirminga high level of purity of the entire system. Background doping and memory effect were found to beuncritical for the deposition of epilayers for thin-film solar cells.

During high-temperature hydrogen anneal, a diffusion of boron from the gas phase into the bulk ofsilicon samples or vice-versa occurs, depending on the resistivity of the sample. The intentionalinjection of B2H6 during hydrogen anneal results in an enhanced diffusion of boron into the bulk of thesamples.

The design of the gas system in the RTCVD100 causes a delayed injection of diborane into thereactor, relative to trichlorosilane. As a consequence, the resulting carrier density profiles ofintentionally doped layers feature a dip in doping concentration near the substrate/epilayer interface,with depth and width of the dip depending on silicon growth velocity and the diborane gas flow rate.The compensation of the diborane delay by an in time manual operation of the diborane gas valveresults in carrier density profiles which still feature a shallow depression near the interface. A similarcharacteristic is observed for intrinsic layers. At present, the origin for the formation of a highresistivity silicon layer during the initial stages of layer growth is unclear. A variation of prebakeconditions should be carried out, to exclude the possibility of an incomplete prebake process and theassociated presence of residual oxide on the sample surface.

Solar cell simulations have been carried out to evaluate the effect of a dip in doping concentrationbetween substrate and epilayer, according to the experimental findings. The results show that a


decrease in carrier concentration between substrate and base is to be avoided if high efficiencies are tobe attained. Consequently, either a high-low deposition process should be used or a deposition withpre-diffusion should be applied.

Finally, an improved gas system design is outlined where all process gases can be homogeneouslymixed before they are introduced into the reaction chamber. The delayed injection of any process gasis avoided and dead storage capacities are reduced.

87

6 Epitaxial thin-film solar cells

The term “epitaxial solar cell” refers to a solar cell structure where theactive silicon base layer is deposited onto a silicon substrate by epitaxy. Thecharacteristic feature of epitaxial silicon thin-film solar cells is the electricalinactivity of the substrate and the reduced thickness of the base layer whichis typically below 50 µm. Using inexpensive substrates and silicon depositiontechniques, this material represents a potential low-cost wafer equivalentwhich can be directly introduced into standard industrial solar cellproduction lines.

In this chapter the application of screen printing technologies on epitaxialmaterial is investigated in detail using epilayers grown on low-resistivity Cz-Si wafers as ideal model system. Subsequently the industrial type solar cellprocess is transferred to epilayers on mc-Si and single-crystal reclaimsubstrate wafers. The chapter closes with a preview on future applications ofRTCVD in the area of emitter and BSF formation.

6.1 Solar cell conceptCompared to other silicon thin-film solar cell concepts the epitaxial solar cell plays an outstanding rolebecause of its simplicity and the possibility to introduce it directly into industrial production. Figure6.1 illustrates the typical design and solar cell process sequence of an epitaxial thin-film solar cell.

n+

p+ silicon substrate

ARC

emitter contact grid

epitaxial base (p)

base contact

Screen printing of contacts

Rapid thermal firing

Edge isolation

Silicon substrate

Saw damage removal /cleaning

Epitaxy of base layer

PECVD SiNx deposition

PSG removal

Homogeneous emitterdiffusion

Figure 6.1: Left: Schematic of epitaxial thin-film solar cell structure. Right: Solar cell processsequence for epitaxial solar cells.

In general, the solar cell material consists of a low-cost silicon substrate and a thin base layer(<50 µm) epitaxially grown on top. The substrate wafers typically feature high doping levels or / and

6 Epitaxial thin-film solar cells88

high defect densities, making them electrically inactive. The possibility to use silicon as substrate is ofgreat advantage compared to other silicon thin-film approaches: matching of thermal expansioncoefficient and high-temperature stability do not present a problem and the expertise from alreadyexisting silicon technologies can be applied.

Compared to conventional silicon wafers, the active device region is drastically reduced and lowerquality material can be employed (see chapter 2). Using a highly doped silicon substrate, the solar cellperformance benefits from the BSF effect of the high-low junction at the interface between active baselayer and silicon substrate. On the other hand, the disadvantages of the reduced base layer thicknessand the thick highly doped substrate are obvious: the generation of electron-hole pairs contributing tophotocurrent is restricted to the thin active base layer since electron-hole pairs generated in thesubstrate recombine very fast and are therefore lost. The implementation of optical confinementfeatures is essential to increase the short-circuit current.

The solar cell process sequence in Figure 6.1 (right) points out that compared to conventional solarcell processing only one additional step is needed for the preparation of epitaxial solar cells: theepitaxy of the base layer. For a large scale production of epitaxial solar cells, the existing productionlines can be directly addressed, making this concept a very attractive cost-saving alternative toconventional silicon wafer solar cells.

For a successful industrial manufacturing of the epitaxial silicon thin-film solar cell concept thefollowing criteria have to be accomplished: the processing of epitaxial material by conventionalindustrial techniques has to be proved to be straightforward and the aspect of cost-saving has to befulfilled. The successful application of screen printing technologies on epitaxial material has alreadybeen demonstrated for epitaxial layers deposited in a commercial system on various kinds of substrates[104]. The issue of cost-saving is affected by the cost for the silicon substrate, the epitaxial depositionas well as the solar cell efficiency. These three aspects and their effect on solar cell structure orprocessing will be discussed in the following sections.

6.1.1 Silicon substrate materialsCompared to conventional silicon wafer solar cells the concept of silicon thin-film solar cells cantolerate base layers of minor quality. The restrictions imposed on crystal perfection and contaminationlevel in the base are less severe. This conclusion similarly holds for the substrate material making theapplication of low quality silicon as a starting material for silicon substrates possible.

The cost for commercial silicon wafers is basically determined by the starting material, which is thesilicon powder, and the manufacturing cost, especially the slicing step. The production of Cz-Si or FZ-Si rods requires the use of high purity silicon. During wafering a substantial part of the high-qualitymaterial is lost by kerf loss. Both aspects, high purity silicon powder and kerf loss contribute to thehigh cost for this type of silicon material. Consequently, the cost of either one or both steps has to bereduced for a competitive alternative material.

The cost for silicon powder depends on the degree of contamination: the higher the impurity level inthe powder, the lower the price. Metallurgical grade (MG) or upgraded metallurgical grade (UMG)silicon therefore represents a cost-saving option to electronic grade material at the expense of highcontamination levels. UMG-Si is gained from MG-Si by a low-cost cleaning step. Common impuritiesin UMG-Si are C, O, Ti, Al, Ca and large amounts of Fe and B thus making the material unsuitable for

6.1 Solar cell concept 89

conventional solar cell production. Because of the large impurity concentration and / or defect densityin MG and UMG silicon wafers, these substrates are in general electrically inactive.

The expensive slicing of the wafers can be replaced either by new slicing techniques resulting inthinner wafers and less kerf loss or by ribbon technologies where thin silicon sheets are directlyproduced thus saving the slicing step. Edge Defined Film-Fed Growth (EFG) [105], String Ribbon[106], Dendritic Web [108], Ribbon Growth on Substrates (RGS) [109] and Silicon Sheets fromPowder (SSP) [110] are the most prominent ribbon technologies to be mentioned.

A large variety of different silicon materials has already been tested as substrate for epitaxial thin-filmsolar cells. In [111] epilayers were grown on highly doped RGS ribbons leading to a maximumefficiency of 10.4% for a 30 µm base layer. The solar cell process included tube furnace diffusion ofthe emitter, evaporated contacts, hydrogen passivation and the deposition of a double layerantireflection coating. For epitaxial solar cells on SSP a maximum efficiency of 8% has been achieved[112]. SSP is characterized by a low average grain size of 60 µm which basically limits the solar cellperformance.

In recent years, many R&D projects focused on the application of silicon substrates from cast MG orUMG multicrystalline ingots. Compared to ribbon technologies, this concept benefits from theexpertise from industrial production. At the University of Konstanz epilayers were grown by LPE onUMG mc-Si substrates. Using screen printing technologies a maximum efficiency of 10% wasobtained for a 30 µm thick epilayer [113]. CVD-epilayers grown on grooved MG mc-Si substrateswere reported to reach efficiencies of up to 12% for a 100x100 mm² solar cell with screen printedcontacts [104].

6.1.2 EfficiencyThe potential of crystalline silicon thin-film solar cell in terms of high efficiencies has already beendiscussed in chapter 2. The efficiency of epitaxial solar cells depends on various parameters. Materialproperties, thickness, doping level and minority carrier lifetime of the base, as well as interfacerecombination velocity and contributions coming from the substrate determine the solar cellparameters. Thickness and doping of the deposited base layer have to be tailored to the substratematerial to maximize the solar cell efficiency. In section 6.2.8 the influence of these parameters on theoverall solar cell performance is investigated by device simulation.

Effective light trapping is a basic requirement for crystalline silicon thin-film solar cells to reach highshort-circuit currents. For epitaxial thin-film cells the application of a reflective porous siliconintermediate layer represents a promising option to enhance the optical confinement [114]. Anincrease in photocurrent can also be obtained by texturing the front surface of the cell thus reducingthe front-surface reflection and increasing the optical path length in the base. Surface texturing can beapplied after the deposition of the epilayer e.g. by an isotropic etching of random pyramids or beforeepitaxy e.g. by mechanical V-grooving. The rough surface obtained by texturing imposes highchallenges on solar cell processing technology. Because of the increased surface area excellent surfacepassivation is necessary and the emitter formation and front metallization must meet the demandsimposed by the structured surface.


6.1.3 Epitaxial deposition systemsIn microelectronic industry batch type or single-wafer CVD epi-reactors with low wafer size capacityare commonly used. These reactors typically operate with large gas flow rates but low chemical yieldand therefore gas consumption makes up for a substantial part of the final high cost for silicondeposition. Assuming a solar cell production capacity of 50 MWp per year and an electric solar cellefficiency of 15%, a throughput of 28 m²/h is necessary (no losses in yield). The batch-type CVDreactors used for microelectronic applications are not capable to meet the required demands on cost-effectiveness and throughput imposed by solar cell production. Alternative solutions for silicondeposition have to be found and therefore, the development of high throughput epitaxy systems is acurrent issue in R&D of silicon thin-film solar cells.

At the University of Konstanz an up-scaled batch-type LPE system with a potential wafer capacity of0.54 m² per run is currently developed [115]. The LPE process makes use of a melt back step beforesilicon deposition thus supplying the melt with silicon material and in principle, no additional siliconhas to be added. Assuming a process time of 8 h per run for a 30 µm thick layer, a maximumthroughput of 0.07 m²/h can be reached. Industrial feasibility is expected to be achievable by a furtherenlargement and multiplication of the deposition system.

In [39] an up-scaled batch-type LPCVD system is proposed for industrial-scale silicon deposition atlow cost. The presented deposition reactor has a capacity of 20 wafers of 100x100 mm² and depositionrates between 0.1 and 0.5 µm/min are reported. Epitaxial layers grown in this reactor proved to be ofexcellent quality.

An early development of an open-tube continuous silicon deposition reactor is described in [60],where 200 µm thick polycrystalline silicon films were grown and subsequently used as solar cellmaterial. The deposition process was based on high-temperature CVD from trichlorosilane in a hot-wall reactor and the successful operation of this system demonstrated the technical feasibility of acontinuous silicon deposition reactor.

At Fraunhofer ISE a continuous APCVD system has recently been developed where samples of up to200 mm in width can be processed (see section 3.4.4). Assuming a realistic epitaxial deposition rate of5 µm/min a throughput of 1.4 m²/h can be reached for a 30 µm thick epilayer with the option of furtherup-scaling. This high throughput CVD apparatus represents a good basis for the development of aproto-type CVD reactor for industrial scale production.

6.1.4 Efficiency table for epitaxial thin-film solar cellsIn Table 6.1 the most important results achieved in the area of epitaxial thin-film solar cells aresummarized. The solar cell approach has been tested on different silicon substrate materials usingmainly CVD and LPE growth techniques. High-efficiency processes as well as industrial screenprinting technologies have been applied for solar cell preparation. Solar cells prepared on epilayers onhigh-resistivity p-type substrates or with supplementary thinned substrates were not taken intoconsideration.

In general, depositions denoted by APCVD were carried out in a commercial CVD system used formicroelectronic production. In contrast, LPE and RTCVD100 (the reactor discussed herein) representlab-type systems. One major goal of this work was to verify that epilayers grown in the lab-typeRTCVD100 on different silicon substrates can be processed by industrial type technologies and yield

6.2 Solar cells on Cz-Si substrates 91

similar efficiencies than solar cells prepared on epilayers grown in a commercial system. Togetherwith the possibility for an up-scaling of the reactor-principle (as already done by the RTCVD160 andthe continuous APCVD - see chapter 3), the RTCVD100 might be regarded as an embryo for futuresilicon deposition systems in crystalline silicon thin-film solar cell production.

Substrate Deposition Epilayer[µm]

Area[cm²]

Solar cell process Efficiency[%]

Ref.

Single-crystal silicon substrates

p+ sc-Si RTCVD100 37 4 High-efficiency 17.6 [40]

p+ sc-Si LPE 32 4 Microgrooved, high-efficiency

16.4 [116]

Multicrystalline silicon substrates

p+ mc-Si APCVD 20 4 Evaporated ContactsHydrogen passivation

13.3 [117]

p+ mc-Si,grooved

APCVD 20 24 Screen printed contacts 13.2 [87]

p+ mc-Si LPE, melt-back cycles 25 4 Evaporated contacts 15.2 [89]

UMG-Si substrates

p+ UMG-Si APCVD 20 4 Evaporated contactsHydrogen passivation

12.8 [104]

p+ UMG-Si APCVD 20 100 Screen printed contacts 10.8 [104]

p+ UMG-Si,grooved

APCVD 20 100 Screen printed contacts 12.0 [104]

UMG-Si LPE, Substrate melt-back 30 3 Screen printed emitter andcontacts

10.0 [113]

Ribbon silicon substrates

p+ SSP RTCVD100 15 4 Evaporated Contacts 8.0 [112]

p+ RGS APCVD 30 4 Evaporated ContactsHydrogen passivation

10.4 [111]

Table 6.1: Thin-film epitaxial solar cells on different highly doped silicon substrates.

6.2 Solar cells on Cz-Si substratesIn this work, epitaxial silicon thin-film solar cells were prepared on Cz-Si substrates to test theapplication of industrial screen printing technologies on epitaxial material and to verify the quality ofepilayers grown in the RTCVD100. Epitaxy was carried out in the RTCVD100, where two processtypes featuring different growth rates were used. For solar cell processing, conventional cleanroomand industrial techniques for emitter and contact formation were applied in various combinations.Therefore, possible interactions between the epitaxial material and different solar cell process stepscould be separated.


6.2.1 Solar cell processingHighly doped <100>-oriented Cz-Si wafers with a nominal specific resistivity ≤ 0.02 Ωcm were usedas substrate material. Prior to epitaxy the samples were wet-chemically treated by a CP-133 damage-etch and a subsequent RCA cleaning with the last HF-dip omitted. The epitaxial depositions werecarried out in the RTCVD100 using two different CVD-deposition processes, A and B. In thefollowing, process A determines a process with medium growth rates of 5-6 µm/min, whereas processB is defined by large growth rates of 9-10 µm/min. The almost doubled growth rate for process Bcompared to process A represents an attractive option for industrial production, where high throughputis requested. Both processes were already discussed in detail in chapter 4. Epitaxial layers of 30 µmthickness and with a doping density of 5x1016 cm-3 were deposited. The thickness of the layers wasdetermined by weighing the samples before and after deposition, and calculating the averagethickness. Before solar cell preparation the highly doped surface layer, which is a consequence of thedeposition process in the RTCVD100, was removed thus reducing the effective base layer thickness toapproximately 26 µm. In Figure 6.2 the standard process sequence used for the preparation of epitaxialmaterial is summed up.

CP-133 damage etch RCA cleaning Epitaxy Removal of ~5 µmfrom the surface

Solar cellprocess

Figure 6.2: Standard process sequence for the preparation of epitaxial solar cells.

Apart from the epi-samples two different types of reference material were included in the solar cellbatches. First, Cz-Si or FZ-Si wafers were used to enable a control of the solar cell process. Second,epilayers on highly doped, polished Cz-Si substrates deposited in a commercial system were added asan ideal epi-reference. In contrast to the samples grown in the RTCVD100, these epilayers were40 µm thick with a doping level of 4x1016 cm-3, as measured by SRP. The specific resistivity of thesubstrate was determined to 0.015 Ωcm. Before solar cell processing, both reference types weresubjected to the same cleaning procedure as the epi-samples.

Five different solar cell processing routes were tested. In Table 6.2 an overview is given on therealized solar cell structures. Process 1 represents the standard cleanroom process typically used atFraunhofer ISE for silicon solar cells. The emitter is homogeneously diffused from a POCl3 source in aconventional tube furnace with a final sheet resistance of 80 Ω/sq. Photolithography was employed forthe definition of the front contact grid and metallization was done by evaporation of TiPdAg andadditional electro-plating. For base contact formation, aluminum was evaporated on the backside ofthe cell. Finally a double layer antireflection coating (DLARC) of TiO2/MgF2 was deposited onto thefront surface of the solar cell.

In contrast to this cleanroom process only screen printing techniques were employed in process 5. Thestandard screen printing process at Fraunhofer ISE consists of the following steps [118]: screenprinting of phosphorus dopant and in-line diffusion of the emitter in a conveyor belt furnace with afinal sheet resistance of 40 Ω/sq, deposition of an antireflection passivating PECVD-SiNx layer, rearand front contact formation by screen printing using aluminum and silver paste respectively and RapidThermal Firing (RTF) of the contacts through the SiNx-layer.


Emitter Metallization

POCl3-source Screen printed dopant Lithography Screen printingProcess no. Tube furnace In-line diffusion Evaporation RTF through SiNx

1 80 Ω/sq X

2 40 Ω/sq X

3 40 Ω/sq a: with SiNx

b: without SiNx

4 40 Ω/sq X

5 40 Ω/sq a: with SiNx

b: without SiNx

Table 6.2: Different combinations of cleanroom and industrial screen printing technologies realizedon epitaxial material in five solar cell batches.

The remaining solar cell process routes 2, 3 and 4 represent different combinations of emitterformation technique and metallization from cleanroom and screen printing technologies. Comparingprocess 2 and 3 information can be obtained about the impact of contact formation by screen printingand evaporation respectively on samples with POCl3 diffused emitters. A similar comparison can alsobe done for process 4 and 5 where both metallization techniques are applied to a standard screenprinted and in-line diffused emitter. On the other hand, the effect of emitter formation technique on thesolar cell characteristics of samples with evaporated contacts can be studied using the results fromprocess 2 and 4. Combining process 3 and 5 a similar investigation can be carried out with respect to ascreen printed metallization. In addition, the influence of firing through SiNx can be evaluatedcomparing solar cells processed via route 3 and 5 with and without silicon nitride deposition. Process3 and 5 represent industrially relevant processing routes and are therefore of major interest whileprocess 1 was included to allow for a monitoring of the epilayer quality.

Summing up, the extensive experimental setup allows the detection of any effect on solar cellperformance induced by screen printing technologies.

6.2.2 RTCVD-process A vs. BIn this section the influence of epilayer deposition process on solar cell performance is investigated.Comparing the solar cell parameters for both epilayer types A and B within one process route can giveinformation about possible differences in epilayer quality. Instead of analyzing all process routes onlyprocess 1 is considered exemplarily. In Table 6.3 the calculated mean values for the illuminated I/Vcharacteristics of 4 solar cells per process type are summarized.

The results show that process A yields an overall better solar cell performance. For both epitaxyprocess types, the relative standard deviations differ only on a small scale indicating a comparablereproducibility.

While the mean values for the open-circuit voltage are similar for both CVD processes, solar cells onepilayers of type B feature a slightly lower short-circuit current density and fill factor. However, inboth cases the differences are still within the range of standard deviation. The reduced fill factor for


process B may be explained by additional defects which might be introduced during the deposition asa result of the fast growth mode.

In Figure 6.3 the internal quantum efficiency of two solar cells prepared by CVD-process A and B arecompared. Apart from a small difference in the long wavelength range the characteristics are identical.The solar cell with type B epilayer shows a slightly reduced red response indicating a thinner baseregion.

VOC JSC FF EfficiencyProcess[mV] [mA/cm²] [%] [%]

RTCVD100 (A) 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2

RTCVD100 (B) 626 ± 5 28.2 ± 0.2 75.9 ± 2.4 13.4 ± 0.5

Table 6.3: Comparison of epitaxy process A and B in terms of illuminated I/V parameters for solarcell process 1.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

Epitaxy process A B

IQE

λ [nm]

Figure 6.3: Comparison of internal quantum efficiency for solar cells with type A and B epilayer.

In conclusion, it can be stated that solar cells prepared on epilayers of type A show a slightly bettersolar cell performance compared to epilayers of type B. The large growth velocity of 10 µm/min isthought to introduce additional defects leading to an increase in saturation current density and theformation of shunts, thus reducing the fill factor. For solar cell process 2 to 5 a similar behavior isobserved, verifying that the differences are indeed related to material properties.

Using process B the throughput of the silicon deposition system can be almost doubled with a loss insolar cell efficiency below 1% absolute, compared to process A. This characteristic makes the fastgrowth mode an interesting choice for large scale production.

Unless otherwise stated the following investigations were carried out for solar cells with type Aepilayers.


6.2.3 Epilayer qualityThe electrical quality of epilayers deposited by process A is evaluated comparing solar cell parametersand spectral response to the results gained for FZ-Si and commercial epitaxial reference cells. Again,only solar cells prepared by the standard cleanroom process 1 are considered.

In Table 6.4 the calculated mean values for the illuminated characteristics are given. Comparing thesolar cell parameters with respect to the epitaxy process, similar values for open-circuit voltage and fillfactor are observed. The main difference lies in the short-circuit current density, which is 1.9 mA/cm²larger in case of commercial epilayers, possibly due to the greater thickness of the base layer.

The solar cells on FZ-Si wafers resulted in slightly larger VOC and substantially greater JSC comparedto the epi-cells, the latter reflecting the increased thickness of the active device region. The meanvalues for the fill factor are in the same range.

dbase VOC JSC FF EfficiencyProcess[µm] [mV] [mA/cm²] [%] [%]

FZ-Si Ref. 633 ± 2 35.3 ± 1.0 78.4 ± 0.2 17.5 ± 0.6

Commercial epitaxy 35 625 ± 1 30.5 ± 0.2 78.0 ± 0.6 14.9 ± 0.2

RTCVD100 (A) 26 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2

Table 6.4: Calculated mean values and standard deviations for illuminated I/V parameters of FZ-Sireferences and epi-cells. The epilayers were deposited in a commercial reactor and in theRTCVD100 using process A.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

FZ-Si reference Epitaxial reference Epitaxial cell (ISE)

IQE

λ [nm]

Figure 6.4: Comparison of internal quantum efficiency for solar cells prepared on FZ-Si and onepilayers deposited in a commercial reactor and in the RTCVD100.

The internal quantum efficiency characteristics measured for the three solar cell types are compared inFigure 6.4. In the short-wavelength range the curve for the epitaxial reference differs from the othersdue to a slight difference in emitter properties, related to the solar cell process. Otherwise, all three


curves show an almost identical characteristic up to a wavelength of 700 nm. In the long-wavelengthrange the decrease in spectral response is mainly correlated to the thickness and minority carrierdiffusion length of the active base region. In case of the FZ-Si reference cell, the hump observed neara wavelength of 1100 nm results from internal rear surface reflection. Because of the large substratethickness and the high doping level this hump lacks in case of the epitaxial cells.

Summing up, the results show that epilayers grown in the RTCVD100 are of sufficient quality to yieldhigh solar cell efficiencies. The implementation of an adequate optical confinement could furtherincrease the photocurrent.

6.2.4 Comparison of solar cell technologiesIn the proceeding sections the high quality of the epilayers grown in the RTCVD100 has beendemonstrated. Now the focus is put on a correlation between solar cell preparation technique andepitaxial solar cell performance. The influence of emitter formation and metallization technique on theepitaxial material and the associated solar cell parameters are discussed.

Before comparing the process technologies in terms of solar cell characteristics, the process steps forboth emitter and contact formation techniques are described in more detail to enable an understandingof possible effects.

Emitter formation

- TF emitter (Tube Furnace): emitter diffusion from a POCl3 source takes place in a closed tubefurnace under an atmosphere containing nitrogen, POCl3 and oxygen. A chemical reaction ofoxygen and the phosphorus containing compounds on the heated sample surface leads to theformation of phosphorus silicate glass (PSG), serving as source for the phosphorus diffusion. Thediffusion of highly doped emitters was carried out at temperatures around 875°C for 20 min.

- CBF emitter (Conveyor Belt Furnace): the phosphorus containing paste “Soltech P101” washomogeneously screen printed on the front side of the wafer. After drying, in-line diffusion wascarried out in an infrared heated RTC conveyor belt furnace at 925°C under oxygen atmosphere.The total process time for this step was 15 min.

Both emitter formation techniques finish with a PSG-etch using hydrofluoric acid (HF).

Contact formation

- EC (Evaporated Contacts): the standard cleanroom process at Fraunhofer ISE employs contactformation by photolithography and subsequent evaporation of the contact metal. For the emitterfront contacts a combination of Ti/Pd/Ag and in addition electroplating is used whereas aluminumis evaporated on the rear surface. The photolithographic emitter contact grid used for these solarcells is optimized for an 80 Ω/sq emitter. The fingers and bus bar are tapered with a contact widthof 10 and 20 µm in case of the fingers and 60 and 120 µm for the bus bar. After electroplating thefinger width was determined to approximately 100 µm with a final height of 20 µm. The entireprocess ends with a sinter step at 400°C for 35 min.

- SPC (Screen Printed Contacts) : the standard screen printing process starts with the deposition ofan antireflection PECVD-SiNx at 346°C for 10 min resulting in a layer thickness in the range of55 nm. The front and rear contacts are screen printed using Ag-paste and Al-pase respectively.


After drying, rapid thermal firing is employed for contact formation. The RTF process includes aburn out of the organics which remained in the paste and a subsequent firing step at 780°C for fewseconds. The final width and height of the front contacts were measured to 100 µm and 8 µmrespectively.

580

600

620

640

V OC [

mV]

60

65

70

75

80

85

FF [%

]

25

26

27

28

29

5a43a211 2 3a 4 5a

JSC

[mA/

cm²]

11

12

13

14

Effi

cien

cy [%

]

Figure 6.5: Mean values of illuminated I/V parameters calculated for all process types.

The mean values for the solar cell parameters determined from illuminated characteristics werecalculated for all solar cell types. Figure 6.5 gives an overview on the results. For solar cells withscreen printed contacts but without SiNx layer (3b and 5b) no statistical evaluation was carried out.

As expected, the standard cleanroom process 1 shows the overall best solar cell performance with anelectrical efficiency of 14.8% due to an optimized emitter and contact grid. Only slightly lower meanefficiencies were achieved for solar cells with CBF emitter and screen printed contacts (4) while theefficiencies of the remaining solar cell types are all in the range of 12%.

Solar cells with screen printed contacts (3a and 5a) feature lower fill factors compared to solar cellswith evaporated contacts. This is a typical characteristic associated to contact formation by screenprinting which results in increased contact and series resistance. From fitted dark I/V characteristicsthe series resistance was determined to values well above 1 Ωcm² for solar cells with screen printedcontacts. The application of evaporated contacts led to constant fill factors above 78%, comparable tothose determined for process 1 and independent from emitter formation technique.

Considering the open-circuit voltage, the combination of CBF emitter with SPC (5a) results in a meanvalue comparable to process 1. The lowest VOC is observed for solar cells with TF emitter and EC (2)with a loss of -16 mV compared to process 5a. Keeping the emitter formation technique fixed, it canbe observed that the application of screen printing for contact formation instead of evaporation leadsin general to larger open-circuit voltages (2 vs. 3a and 4 vs. 5a). For TF and CBF emitter an increaseof 11 mV and 7 mV respectively is calculated for screen printing compared to evaporation.


On the other hand, if the contact formation technique is fixed, an increased VOC is achieved if a CBFemitter is used instead of a TF emitter (2 vs. 4 and 3a vs. 5a). In this case, a rise of 9 mV and 6 mV isobserved in VOC for evaporated contacts and screen printed contacts respectively, when replacing theTF emitter by a CBF emitter.

Both features can be readily explained by the different contact and emitter formation techniques. Theapplication of a SiNx layer in case of screen printed contacts leads to an effective passivation of thesurface, emitter and bulk region thus reducing the recombination activity and therefore increasing VOC.The results further show that the application of a CBF emitter is beneficial for VOC, indicating that ageneral difference exists between the characteristics of the two emitter types. A possible explanationfor the low performance of the TF emitter might be that high phosphorus surface concentrations or alarge density of phosphorus precipitates led to an enhanced recombination in the emitter and spacecharge region.

The mean values in short-circuit current are equal for process 4 and process 1 while process 2, 3a and5a feature considerably lower values, all in a similar range. Using screen printed contacts, the emitterformation technique has only little impact on JSC. CBF and TF emitter result in almost identical meanvalues (3a vs. 5a). On the other hand, a significant boost in JSC can be observed for evaporatedcontacts, if a CBF emitter is used instead of a TF emitter (4 vs. 2).

Increased shadowing and series resistance loss determine the short-circuit current densities if contactformation is done by screen printing. This characteristic is clearly reflected when comparing process 4and 5a, where a difference of almost 3 mA/cm² in JSC is observed in favor of the solar cells withevaporated contacts. A similar difference is expected for process 2 and 3, where both emitters areformed by POCl3 diffusion but different contact formation techniques are applied. Instead, bothprocesses result in similar short-circuit current densities. To explain this discrepancy the followingassumption concerning TF and CBF emitter is made: compared to the CBF emitter the POCl3 diffusedemitter features an increased surface concentration and is less deep. In addition the sheet resistancemight be slightly different for both emitters, with the CBF emitter probably featuring a lower value.Considering process 2 and 4 the detrimental decrease in JSC for the TF emitter can then be attributed toan enhanced recombination velocity in the emitter region. The internal quantum efficiencymeasurements graphed in Figure 6.6 confirm this statement. The solar cell with CBF emitter shows anoverall better internal quantum efficiency compared to the solar cell with TF emitter. While theincrease in red response is comparatively low and might be either a consequence of the CBF diffusionor a slight deviation in base layer thickness, the difference in the short-wavelength range is apparent.Up to a wavelength of 600 nm the solar cell with CBF emitter shows a substantially higher IQE thanthe solar cell with TF emitter, possibly due to different emitter characteristics.

In Figure 6.7 the IQE characteristics for solar cells prepared by process 3a and 5a are compared.Again, the CBF emitter shows an overall better spectral response. However, compared to Figure 6.6the difference between both emitter types is less pronounced and in the mid-wavelength range theyeven show almost identical values.


400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

EC with TF emitter (2) CBF emitter (4)

IQE

λ [nm]

Figure 6.6: Internal quantum efficiency measured for epitaxial solar cells with different emitterdiffusion techniques. In both cases, contact formation was done by evaporation.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

SPC with RTF through SiNx TF emitter (3a) CBF emitter (5a)

IQE

λ [nm]

Figure 6.7: IQE for solar cells with screen printed metallization and different emitter types.

To evaluate the effect of the passivating SiNx layer on spectral response, IQE measurements were alsocarried out on solar cells of process 3b and 5b. The resulting curves are depicted in Figure 6.8 andcompared to the IQE characteristics obtained for corresponding solar cells with SiNx (type a).

The application of a SiNx layer on a TF emitter leads only to a minor improvement in IQE for shortwavelengths (Figure 6.8, left). In contrast, a substantial rise in blue response is obtained for the CBFemitter, if a passivating silicon nitride layer is deposited on the solar cell surface (Figure 6.8, right). Inboth cases, a slight increase in red response is observed if a SiNx layer is applied, indicating a bulkpassivation of the base layer region. Similar to the improvement in the short-wavelength range theeffect is more pronounced for the CBF emitter.


400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

TF emitter RTF through SiNx (3a) RTF without SiNx (3b)

IQE

λ [nm]400 600 800 1000 1200

0.0

0.2

0.4

0.6

0.8

1.0

CBF emitter RTF through SiNx (5a) RTF without SiNx (5b)

IQE

λ [nm]

Figure 6.8: Effect of RTF through SiNx on internal quantum efficiency studied for two differentemitter formation techniques. Left: TF emitter with screen printed contacts. Right: CBFemitter with screen printed contacts.

Considering the solar cell parameters for TF emitter, contact formation with RTF through SiNx yieldsan increase in VOC by 29 mV and an increase in JSC by 7.3 mA/cm² compared to contact formation byevaporation. For the CBF emitter the improvement is even more drastic with a rise in VOC by 35 mVand in JSC by 8.2 mA/cm².

The results from IQE and illuminated I/V characteristics show that the CBF emitter can be betterpassivated by the SiNx layer, indicating a lower surface concentration compared to the TF emitter andthus further confirming the assumption made on the shape of the emitter profiles.

In Figure 6.9 the impact of contact formation on spectral response can separately be studied for bothemitter types. Concerning the TF emitter the internal quantum efficiency characteristics suggests thatthe mere process of contact formation by screen printing (without RTF through SiNx) considerablyimproves the emitter and bulk region of the solar cell. For the CBF emitter almost the inverse effect isobserved: the process of screen printing deteriorates the emitter but not the bulk.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

TF emitter EC (2) SPC without SiNx (3b)

IQE

λ [nm]400 600 800 1000 1200

0.0

0.2

0.4

0.6

0.8

1.0

CBF emitter EC (4) SPC without SiNx (5b)

IQE

λ [nm]

Figure 6.9: Internal quantum efficiency for solar cells with TF emitter (left) and CBF emitter (right)and evaporated as well as screen printed contacts.


A conclusions which can be drawn from these results is that the process of screen printing seems toinfluence the solar cells with TF emitter in terms of an improved minority carrier lifetime in emitterand bulk. Temperature and duration of the firing step are very short compared to the emitter diffusionfrom POCl3 source and therefore a change of the emitter properties as a consequence of the firingprocess seems to be unlikely. At present, the mechanism leading to the observed improvement is notclear.

To quantify the CBF and TF emitter profiles, SIMS and Stripping Hall measurements were orderedbut not completed at the end of this work.

6.2.5 Overview on solar cell efficienciesIn Table 6.5 the best solar cell efficiencies achieved for each solar cell process for all three differentmaterial types are listed. The illuminated I/V parameters for samples marked with an asterisk areconfirmed measurements by the Fraunhofer ISE Calibration Laboratory. Solar cells with epilayersdeposited at Fraunhofer ISE are denoted Epi (ISE) while those with epilayers grown in a commercialCVD system are denoted Epi-Ref.

Area Sample VOC JSC FF EfficiencyProcess[cm²] [mV] [mA/cm²] [%] [%]

1 21.2 Epi (ISE)* 635 28.9 80.8 14.8

Epi-Ref. 631 30.7 78.9 15.3

FZ-Si Ref.* 633 34.2 81.1 17.6

2 21.6 Epi (ISE)* 613 26.8 78.4 12.9

Epi-Ref. 612 27.5 79.9 13.4

FZ-Si Ref. 620 33.6 79.8 16.6

3a 23.0 Epi (ISE)* 621 25.5 77.1 12.2

Epi-Ref.* 625 26.5 78.7 13.1

FZ-Si Ref. 621 30.7 76.7 14.6

4 21.2 Epi (ISE)* 626 29.0 80.5 14.6

Epi-Ref. 622 29.4 80.4 14.7

Cz-Si Ref. 549 33.6 75.9 14.0

5a 23.0 Epi (ISE)* 628 25.9 74.0 12.0

Epi-Ref.* 628 26.5 72.8 12.1

Cz-Si 589 31.5 68.2 12.6

* Confirmed measurement by ISE Calibration Laboratory

Table 6.5: Summary of the best solar cell results achieved for all process routes. The parametersfor the epitaxial cells, the epitaxial references (Epi-Ref.) and the FZ- and Cz-Sireferences are listed for comparison.


The list is aimed to give an overview on the best results gained for each solar cell process type. Thebasic differences between each material type and each solar cell process route have already beendiscussed in previous sections and therefore only some outstanding features will be highlighted here.

In general, the silicon wafer references feature the best solar cell performance for each process type.Exceptions are process 4a and 5a, where the Cz-Si reference cells suffer from low VOC and low fillfactor compared to the epitaxial cells. This property seems to be related to the applied emitterformation technique by in-line diffusion from a screen printed source. Typically, process 5a yieldsefficiencies of 14.3% with open-circuit voltages and fill factors well above 600 mV and 77%respectively for Cz-Si wafers [119]. The deviation from this standard result must be caused by adifference in the emitter diffusion process. Surprisingly, the epitaxial cells are not affected, possiblybecause of different material properties.

The general differences in short-circuit current reflect the deviations in base layer thickness, which islargest for the silicon wafer material and lowest for the ISE epi-cells.

For the epitaxial thin-film solar cells with epitaxy done at Fraunhofer ISE a maximum efficiency of14.8% is obtained for the standard cleanroom process 1. The solar cell parameters determined for thissolar cell clearly show the potential of the epitaxial thin-film concept: the measured open-circuitvoltage is slightly larger than for the epitaxial reference and especially larger than for the FZ-Si waferreference. On the other hand, the lowest short-circuit current is observed for epi (ISE) as aconsequence of the small thickness of the active base layer and a reduced minority carrier lifetime inthe base (see section 6.2.8). The fill factors for epi (ISE) and FZ-Si reference cell are in the samerange. For the epitaxial solar cells, the application of an adequate optical confinement couldsubstantially increase JSC thus leading to efficiencies comparable to silicon wafer material.

A record efficiency of 13.1% was achieved for an epitaxial thin-film solar cell of 35 µm thicknessprepared by industrial relevant screen printing technologies (3a). For epitaxial layers grown in theRTCVD100 reactor, a maximum efficiency of 12.2% could be reached for a 25 µm base layer usingthe same solar cell process.

6.2.6 Characterization by lock-in thermographyLock-in thermography [120] was applied to analyze the shunts affecting the solar cell performance ofall solar cell types presented in the last sections. Local shunts may influence the I/V characteristics andcan lead to a loss in fill factor and VOC [121]. Figure 6.10 shows lock-in thermograms (amplitudeimage) measured at 0.5 V forward bias for epitaxial solar cells prepared by solar cell process 3a, 4 and5a. Solar cells on epilayers deposited in a commercial system and in the RTCVD100 are compared.Brighter contrasts correspond to higher local current densities.

Edge shunts resulting from an incomplete separation of emitter and base are common to all solar cellsand dominate the thermograms in Figure 6.10. Considering process 3a no significant difference can beobserved between the thermograms of the solar cells with epilayer grown in different CVD systems. Inaddition, it can be stated that the screen printing process does not affect the formation of shunts forsolar cells with TF emitter.

CBF emitter and TF emitter feature similar homogeneity as the thermograms for solar cells of process3a and 4 reveal. No negative interaction between material properties and CBF emitter is observed.


Point-like shunts within the area of the solar cell are visible in the thermogram in the lower left cornerof Figure 6.10 which corresponds to a solar cell with epilayer grown in the RTCVD100, an emitterprepared by conveyor-belt furnace diffusion and screen printed contacts. The shunts were found to bemainly located underneath the emitter grid lines. The equivalent solar cell with commercial epilayer isnot affected by such shunts. Taking into consideration all the information gained from lock-inthermography it is obvious that the formation of shunts for solar cells of process 5 must be associatedto a combined interaction between epitaxial material, CBF emitter and screen printed contacts.

RTCVD100 Commercial reactor

Process 3a

TF emitter

Screen printed contacts

Process 4

CBF emitter

Evaporated contacts

No measurement

Process 5a

CBF emitter


Figure 6.10: Thermograms (amplitude image) of epitaxial cells prepared by different epitaxyprocesses and solar cell technologies. The measurements were carried out at 0.5 Vforward bias.


The occurrence of shunts located underneath the emitter grid lines was already observed in earlierexperiments where CBF emitter and screen printed metallization were applied to epitaxial materialprepared under similar conditions as presented in the previous sections [122]. For state-of-the-artmulticrystalline solar cells, an increased occurrence of shunts underneath emitter grid lines has alsobeen reported in [123]. In [122], the formation of these shunts could be associated to an interactionbetween epitaxial defects and screen printed metallization. However, at this stage the influence ofemitter formation technique could not be determined unambiguously. With the new experimentsdiscussed herein, it is clear that an enhanced formation of shunts depends not only on the properties ofthe epitaxial material and the contact formation technique but also on the type of emitter diffusion.

To understand possible interactions between these three counterparts a detailed knowledge of theindividual characteristics of each component is essential. According to recent studies [124] the contactformation by screen printing can be described as follows: the silver paste which is used for screenprinting contains glas frit, which etches into the antireflection coating and subsequently into theemitter upon heating. Silicon and silver are dissolved in the glas frit during the firing process andrecrystallize upon cooling down thus forming Ag crystallites at the interface. The penetration of Agcrystallites into the silicon emitter region is assumed to contribute to leakage currents of the pn-junction.

For epitaxial solar cells, the observed accumulation of shunts underneath the emitter grid lines couldbe explained by the following mechanism: screen printing of Ag-paste over defective regions (e.g.epitaxial spikes) or grain boundaries can result in an enhanced etching of silicon in these regions bythe glas frit [125] thus affecting the space charge region or even leading to the formation of holes inthe emitter structure. An increased penetration of interfacial Ag crystallites into the silicon emitter ofdefective regions might also explain the correlation between screen printed contacts, epitaxial defectsand the formation of shunts. However, at present the influence of emitter formation technique on thedevelopment of shunts is not clear.

6.2.7 SummaryAn extensive study on the application of different emitter and contact formation techniques wascarried out for epitaxial thin-film solar cells. Emitter structures were realized by diffusion from POCl3

source in a closed tube furnace and by conveyor-belt furnace diffusion from a screen printedphosphorus source. Evaporated and screen printed contacts with and without firing through SiNx wereapplied to both emitter types. Epitaxial solar cells were also prepared by a standard cleanroom processfor material quality monitoring. The quality of epilayers grown in the RTCVD100 reactor atFraunhofer ISE was evaluated with respect to epilayers grown in a commercial CVD system. Inaddition, the influence of very fast silicon growth velocities on solar cell performance wasinvestigated.

The results show, that solar cells processed on epilayers grown at a rate of 5 µm/min are only slightlysuperior to those grown at a doubled rate of 10 µm/min. The difference is assumed to be attributed toan increased defect density in case of the fast growing films leading to an enhanced saturation current.Epitaxial thin-film solar cells prepared in a cleanroom process on fast grown epilayers resulted in amaximum efficiency of 13.9%, with VOC=632 mV, ISC=28.0 mA/cm² and FF=78.8%. Summarizing allsolar cell results it can be stated that epilayers deposited in the RTCVD100 are of sufficient quality toreach high solar cell efficiencies.


The analysis of solar cell parameters and IQE characteristics for epitaxial solar cells prepared bydifferent process types led to the assumption that TF emitter and CBF emitter feature different dopingprofiles. A CBF emitter with lower surface concentration, larger junction depth and larger sheetresistance compared to the TF emitter could explain the observed characteristics. An analysis of bothemitters is currently carried out by Stripping Hall and SIMS measurements to verify the assumptionsmade. IQE measurements showed that the application of a CBF emitter results in a slight increase inred response, indicating a gettering or anneal effect on the epitaxial base layer. Concerning contactformation by screen printing, both emitter types can be equally well applied. A significant passivationof the emitter region is obtained by firing through SiNx.

Screen printing of emitter contacts combined with in-line emitter diffusion was found to result inenhanced shunt formation on sites of epitaxial defects. While a plausible explanation for a possibleinteraction between metallization and defects could be given, the influence of the emitter formationtechnique on the formation of shunts remains to be clarified.

Using industrial relevant screen printing technologies a record efficiency of 13.1% was achieved for a35 µm epitaxial thin-film solar cell. For epilayers grown in the non-commercial lab-type RTCVD100reactor a remarkable efficiency of 12% could be reached for a 25 µm thick base layer using the samesolar cell process.

6.2.8 Solar cell simulationAccording to the solar cell results presented in the previous section a simulation was carried out toevaluate the potential of the solar cell structure. The one dimensional simulation program PC1D [126]was used to calculate the solar cell performance for different material parameters. The solar cell modelis based on the characteristics of an epitaxial thin-film solar cell corresponding to type 3a in previoussections with epilayer grown in the RTCVD100 and industrial type solar cell process technologies.The simulated solar cell structure is illustrated in Figure 6.11: it is divided into three regionscorresponding to emitter, epitaxial base and substrate. The transition zone between substrate and basehas been approximated by an ideal step function.

substrate

emitterbase

ARC

Al rear contact

Sfront

front contact grid

Sinterface

Sbacksubstratebaseemitter

1016

1017

1018

1019

1020

Car

rier d

ensi

ty [c

m-3]

Figure 6.11: Simulated solar cell structure and corresponding carrier density profile.

A correct simulation of any epitaxial solar cell requires knowledge of material parameters for theemitter, base and substrate region:


• The emitter structure was simulated assuming a sheet resistance of 45 Ω/sq as measured by 4-point probe on a FZ-Si reference. The emitter doping profile was designed by a Gauss curve witha junction depth of 0.45 µm and a peak surface concentration of 1.2x1020 cm-3. The front surfacerecombination velocity was fixed to a value of 1x105 cm/s [127]. The simulated emittercorresponds to a highly doped emitter diffused from a POCl3 source as used for solar cell process2 and 3.

• Thickness, doping density and minority carrier lifetime are the most important input parametersfor the base region. In addition, the rear surface recombination velocity of the base (the interfacebetween substrate and epilayer) has to be accounted for in the simulation. The deposition of lowlydoped epilayers on highly doped substrates induces strain at the substrate/epilayer interface due tothe different lattice constants [128], [129]. The lattice mismatch can be relieved by the formationof dislocations building recombination centers.

While thickness and doping density can be estimated from SRP measurements on comparablesamples, neither minority carrier lifetime of the base layer nor interface recombination velocitycan be separately measured. In our case, the epilayer thickness was determined to 25 ± 3 µm witha carrier density of 5x1016 ± 1x1016cm-3.

• Similar to the base region, thickness, doping density and minority carrier lifetime have also to beknown for the substrate region. The aluminum rear surface of the substrate is simulated by arecombination velocity of 1x107 cm/s.

The substrate thickness of 600 µm was taken from the producers information. The specificresistivity of 0.015 Ωcm (4x1018 cm-3) was measured by SRP and 4-point probe. Due to the largedoping density the effect of band gap narrowing has to be accounted for [11]. The lifetime of theminority carriers in the substrate could not be experimentally determined.

In Table 6.6 the relevant parameters of epitaxial layer and substrate material used for the simulationare summarized. Layer thickness, doping density and minority carrier diffusion constant are denotedby d, NA and De respectively. ∆Eg describes the apparent band gap narrowing, which has to be takeninto account for doping densities exceeding 1x1017 cm-3.

d [µm] NA [cm-3] De [cm²/s] ∆Eg [meV]

Base 25 5x1016 20.98 0

Substrate 600 4x1018 6.07 46.9

Table 6.6: Material parameters used for the modeling of an epitaxial thin-film solar cell accordingto experimental values.

The difficulty in simulating the solar cell structure lies in the uncertainty concerning minority carrierlifetime in the base and in the substrate region as well as the unknown recombination velocity at theinterface between substrate and epilayer. All these parameters have significant influence on the solarcell parameters but a separate measurement of these values is not trivial.


Interface recombination velocity, carrier lifetime in the substrate and base

In our case a high-low epitaxy deposition process has been used, with the doping density of the highlydoped layer being identical to the substrate doping level. Therefore, the lattice mismatch at theinterface epilayer/substrate can in a first approximation be assumed as negligible and the simulationproblem reduces to a determination of τepi and τsubstrate.

The degraded lifetime of boron-doped Cz-Si material is limited by Shockley-Read-Hallrecombination. In [130] an empirical model for the bulk lifetime in boron-doped Cz-Si material isgiven. Extrapolating the model to high doping densities allows a confinement of the bulk lifetime forthe Cz-Si substrates used for the epitaxial solar cells under consideration. For a doping density of4x1018 cm-3 bulk lifetimes of 6x10-4 µs and 4.5x10-2 µs are obtained for the degraded and annealedstate respectively.

To determine a range for the lifetime in the epilayer, effective minority carrier diffusion lengths werecalculated from IQE measurements and analyzed according to [131]:

)tanh(

)tanh(1

Ld

LL

Ld

LL

LDS

eff

eff

−

−⋅= (6.1)

where S denotes the effective rear recombination velocity at the back side of the cell which is in ourcase the interface substrate/base. Leff is the effective minority carrier diffusion length, d, L and Ddenote thickness, minority carrier diffusion length and diffusion constant in the base. Thus aseparation of diffusion length in the base and rear surface recombination velocity is possible.

Assuming d/L<0.5 and solving for L, eqn. (6.1) can be approximated by

)(1 eff

eff

LdDS

dLL

−+= (6.2)

This yields a lower limit for the bulk diffusion length Lmin and an upper limit for the back siderecombination velocity Smax of the base layer according to

effdLL =min for scmS /0= (6.3)

dLDS

eff −=max (6.4)

In Table 6.7 the experimentally determined value for Leff and the calculated values for Lmin, Smax andLmin/d are listed for an epitaxial thin-film solar cell prepared by process 3.

The value for Lmin/d is below 0.5, verifying the validity of the approximation made in eqn. (6.2). Forthe diffusion length in the base and the rear side recombination velocity, a minimum of 39 µm and amaximum of 5670 cm/s respectively were obtained. The diffusion length of 39 µm corresponds to a


minority carrier lifetime of 0.73 µs and represents a lower boundary for the lifetime in the epitaxialbase layer.

Taking into consideration these results, a simulated IQE curve fits well to the experimental data forτepi=2 µs and τsub=0.016 µs.

Leff [µm] Lmin [µm] Smax [cm/s] Lmin/d d/Lmin

75 ± 13 43 ± 4 4500 ± 1170 0.34 ± 0.06 3.0 ± 0.54

Table 6.7: Effective minority carrier diffusion length as determined from IQE measurements forepitaxial thin-film cells prepared by solar cell process 3. Lmin, Smax and Lmin/d werederived from Leff.

For a two layer system, the influence of the underlying substrate on the minority carrier lifetime in thebase can be approximated by an effective recombination velocity, if the minority carrier lifetime in thebase layer is greater than the lifetime in the substrate. According to [132] this effective recombinationvelocity Seff represents an upper limit for the interface recombination velocity and is given by:

)tanh(1

)tanh(1

sub

sub

sub

subsub

sub

sub

sub

subsub

sub

subeff

Ld

DLS

Ld

DLS

LD

S⋅+

+⋅

Φ⋅= (6.5)

with )exp( ,,,

,subgepig

epiA

subA EENN

∆−∆⋅=Φ

Where dsub, Dsub and Lsub denote thickness, minority carrier diffusion constant and diffusion length inthe substrate. The rear surface recombination velocity at the back of the substrate is given by Ssub. Theparameter Φ takes the band gap narrowing into account: NA,sub/epi and ∆Eg,sub/epi denote the acceptordensity and the apparent band gap narrowing for substrate and epilayer. Equation (6.5) shows thatapart from the epilayer doping, Seff depends only on substrate properties.

In Figure 6.12 the correlation between Seff and Lsub according to eqn. (6.5) is graphed. For thecalculation, the material parameters were taken from Table 6.6 and the minority carrier diffusionlength in the substrate was varied within the range of 0.1-19.4 µm (Auger-limit). For a maximumdiffusion length of 19.4 µm an effective recombination velocity of 240 cm/s was calculated. LSRH,x

denotes the minority carrier diffusion length for Cz-Si material limited by SRH recombination. Thecorresponding effective surface recombination velocity can be taken from the graph. Smax,Leff is themaximum rear surface recombination velocity as calculated from experimental Leff values (Table 6.7).For the PC1D simulation Lsub was set to 3.1 µm, represented by the filled square.

Using equation (6.5) it can be shown that the solar cell structure can equally well be modeled by onlyone region with an effective rear surface recombination velocity of 1248 cm/s. In this case, thecontributions to photocurrent coming from the substrate region are negligible.


0.1 1 10

102

103

104

105

PC1D Simulation

LSRH, annealedLSRH, degraded

Smax,Leff

Lsub,Auger

S eff [

cm/s

]

Lsub [µm]

Figure 6.12: Calculated effective recombination velocity as a function of minority carrier diffusionlength in the substrate according to eqn. (6.5).

To evaluate the effect of an interface recombination velocity unequal to zero, the solar cell wasmodeled in close relation to experimental conditions: instead of a sharp step-like change in dopingconcentration between substrate and epilayer a transition-zone was implemented where the slowchange in doping density due to autodoping is taken into account. In accordance to experimental datagained from SRP measurements, the width of the transition zone was set to 4 µm. The diffusion lengthin this region was assumed to be slightly larger than the Auger limited diffusion length in thesubstrate. The surface recombination velocity at the interface between base and transition region wasset to zero while the recombination velocity at the crystallographic interface between transition-zoneand substrate was varied from 0 to 106 cm/s. Figure 6.13 shows the calculated loss in efficiency as afunction of interface recombination velocity.

101 102 103 104 105 1060

1

2

3

4

5

6

Rel

ativ

e lo

ss in

effi

cien

cy [%

]

Sinterface [cm/s]

Figure 6.13: Relative loss in efficiency depending on the recombination velocity at thecrystallographic interface between substrate and epilayer.


For a maximum interface recombination velocity in the range of 104 cm/s as determined fromeqn. (6.5) for a degraded Cz-Si substrate with a boron concentration of 4x1018 cm-3, the relative loss inefficiency comes up to 1.6% which is still in an acceptable range. For large interface recombinationvelocities of 106 cm/s the influence on solar cell performance becomes significant and cannot betolerated if high efficiencies are to be achieved.

Optimization of epilayer properties

For an optimization of solar cell efficiency, epilayer thickness and doping level were varied for thesimulated solar cell structure. In Figure 6.14 the results are illustrated.

Within the range of 1x1016cm-3 to 1x1017 cm-3 the base doping density has only little effect on solarcell efficiency for fixed base layer thickness. A further increase in doping concentration leads to areduction in efficiency because of an increased Auger recombination. Greater base layer thicknessesare beneficial for the solar cell performance independent from base layer doping, due to the largervolume of the active device. Within a doping range of 2x1016 cm-3 to 1x1017 cm-3 the efficiency doesnot change significantly for a base thickness exceeding 35 µm. In this case, the solar cell performanceis limited by the minority carrier lifetime in the base.

10 20 30 40 50 60

2

4

6

8

10

12

14

Base Thickness [µm]

NA,

bas

e [10

16 c

m-3]

9.5

10.0

10.5

11.0

11.5

12.0

12.5

13.0

9.5 - 10.010.0 - 10.510.5 - 11.011.0 - 11.511.5 - 12.012.0 - 12.512.5 - 13.0

Efficiency [%]

Figure 6.14: Solar cell efficiency as a function of base layer thickness and doping concentration.

The effect of surface texture on short-circuit current has been investigated by simulating an invertedpyramid texture with a depth of 7 µm. Figure 6.15 shows the influence of a textured front surface onshort-circuit current density.

Three different settings are compared: first, the surface is assumed to be plane with a correspondingexperimental reflection curve used for the simulation (1). Second, the same reflection curve is applied,but a pyramidal texture is simulated on the front surface (2). Third, the front surface is modeled astextured and a reflection curve corresponding to a random texturing with a 7 µm deep pyramidalstructure has been implemented (3). While simulation (2) only considers the enhancement in short-circuit current density by a greater optical path length, simulation no.3 also accounts for the reducedoptical reflection associated to the pyramidal structure. The experimental reflection curves weremeasured on samples without antireflection coating.

Comparing the characteristics in Figure 6.15 the benefit of a textured front surface on short-circuitcurrent density is clearly visible. Considering a base layer thickness of 25 µm, a gain in short-circuit

6.3 Solar cells on mc-silicon substrates 111

current of 3% is calculated, if front texturing is applied and only the geometric effect by an enhancedoptical path length is considered (2). The total reflection of an experimental random texturing wascalculated to 12%, compared to 36% for a plane silicon surface. Taking into account the changedoptical reflection (3), an increase by approximately 29% is obtained compared to (2). Last but notleast, the reflection can be further reduced by the deposition of an antireflection coating. Combiningan antireflection SiNx layer and a textured front surface a total reflectance of only 4% can be achieved.

10 20 30 40 50 60

18

20

22

24

26

28

30

1 2 3

J SC [m

A/cm

²]

Base Thickness [µm]

Figure 6.15: Effect of optical confinement by surface texturing on short-circuit current density forsimulated epitaxial thin-film solar cell.

Summing up, the simulations show that the efficiency of the epitaxial solar cell under considerationcan be increased by slightly increasing the base layer thickness and/or the application of surfacetexturing for optical confinement.

6.3 Solar cells on mc-silicon substratesIn the last section ideal single-crystal, electrically inactive Cz-Si wafers have been used as substratematerial. The influence of different solar cell process steps as well as the quality of two differentCVD-processes could be studied on these epitaxial cells. Compared to this ideal system the solar cellprocess technology is confronted with the challenge of an uneven surface morphology and grainboundaries when applied to multicrystalline wafers. In general, multicrystalline material ischaracterized by the presence of grain boundaries which can act as effective recombination centers andby the presence of other crystallographic defects which are often decorated by impurities [11]. Anenhanced diffusion of impurities along grain boundaries can be expected.

Highly doped (0.01-0.02 Ωcm) Wacker-Silso multicrystalline-Si substrates cut from successivepositions in the block were used as substrate material. The epitaxial samples were prepared accordingto the process sequence described in section 6.2.1. Epilayers of 35 µm thickness and 5x1016 cm-3

doping density were deposited using epitaxy process A. Two solar cell process routes were appliedidentical to process 1 and 3, described in the previous section. The process sequence is depicted inFigure 6.16. The cleanroom process 1 was used for monitoring while process 3 represents a typicalindustrial solar cell process with heavily doped emitter and screen printed contacts. Samples from


successive substrate wafers were introduced in both batches in alternating order to enable a directcomparison of both process types.

Table 6.8 gives the mean values for the illuminated I/V parameters calculated for both process types.For comparison the results obtained for epi-cells on Cz-Si substrates are added.

TF-diffusion from POCl3source (80 Ω/sq)

Definition of front contactsby photolithography

Evaporation and electro-plating of contacts

Deposition of double layerantireflection coating

Process 1 Process 3

TF-diffusion from POCl3source (40 Ω/sq)

PECVD of antireflection SiNx

Screen printing of front andrear contacts

Rapid Thermal Firing (RTF)through SiNx

Figure 6.16: Process sequence of the two solar cell processes applied to epitaxial thin-film solar cellson multicrystalline silicon substrates.

Area Substrate VOC JSC FF EfficiencyProcess[cm²] [mV] [mA/cm²] [%] [%]

1 21.2 mc 591 ± 9 28.5 ± 0.1 69.9 ± 2.6 11.8 ± 0.6

Cz 627 ± 6 28.6 ± 0.4 78.5 ± 1.1 14.0 ± 0.2

3 23.0 mc 595 ± 10 24.4 ± 0.1 75.2 ± 1.5 10.9 ± 0.4

Cz 619 ± 1 25.9 ± 0.3 76.1 ± 0.3 12.2 ± 0.2

Table 6.8: Mean solar cell parameters calculated for epitaxial thin-film solar cells on mc-Si andCz-Si substrates.

The largest fill factors are obtained for solar cells on Cz-Si substrates prepared by process 1. Thereduction in fill factor for equivalent solar cells prepared by process 3 is a direct consequence ofcontact formation by screen printing. However, while solar cells on mc-Si substrates of process 3feature a fill factor of 75% comparable to their monocrystalline counterpart, a significant reduction isobserved for process 1, where only about 70% are reached for solar cells on mc-Si substratescompared to 78.5% for Cz-Si substrates.


The series resistance Rs,light was calculated from illuminated and dark current characteristics for bothmulticrystalline cell types [133]. Since no significant difference between Rs,light and the seriesresistance determined from fitted dark I/V-characteristics was observed, the reason for the lower fillfactor in process 1 must be traced back to a lower parallel resistance and greater saturation current.This can be attributed to the absence of bulk passivation schemes for process 1 and the influence ofcrystallographic defects on the second diode. The large defect density in multicrystalline materialmakes an effective bulk passivation obligatory, if high efficiencies are to be reached. In process 3 thisis realized by the deposition of a passivating SiNx layer.

A reduction in open-circuit voltage can be observed for the mc-Si solar cells of both process types,compared to their corresponding Cz-Si counterpart. For process 1 and 3 the difference amounts to38 mV and 24 mV respectively, in favor of the monocrystalline solar cells. Again, the deviationsbetween both process types can be traced back to the passivation scheme applied for process 3.

Considering the short-circuit current densities, process 3 in general results in lower values due tohigher shadowing for screen printed contacts. Comparing the mean values for both monocrystallinecell types an increase of 2.7 mA/cm² can be observed for process 1. For their multicrystallinecounterparts, an even larger increase of 4.1 mA/cm² is obtained. Assuming that both contact griddesigns always result in the same shadowing loss, the difference in JSC for process 1 and process 3should be equal or at least in the same range for different solar cell materials. The experimental valuescontradict this conclusion. The reason for this discrepancy was found to originate from a variation inemitter contact width for Cz- and mc-Si solar cells prepared by process 1. While screen printingresults in nearly equal finger width for both material types, a deviation is observed for solar cells withevaporated contacts. In this case, the solar cells on multicrystalline substrate feature a very smallcontact width compared to the corresponding monocrystalline solar cells leading to a reduced loss inJSC by shadowing. In process 1, the definition of contact width is done by photolithography, which canbe affected by irregularities in surface morphology and reflectivity.

The morphology of epitaxied multicrystalline substrates imposes high demands on the front contactformation technique. The typical characteristics of epilayers grown on multicrystalline siliconsubstrates have already been discussed in chapter 4. The most important features are the dependenceof growth rate on crystal orientation and the resulting difference in epilayer thickness, the growth-induced texture of certain grain orientations and the trenches, which develop in most cases on sites ofgrain boundaries. Figure 6.17 shows the image of two epitaxial cells prepared by process 1 and 3 onsuccessive mc-Si wafers. A position has been chosen where the finger grid crosses a grain boundary.

Definition of the emitter grid by photolithography resulted in a straight line nearly undisturbed by thegrain boundary. The underlying morphology is reproduced in the contact finger. Nonetheless,photolithography on this material is not straightforward: the presence of an uneven surface texture anddifferent layer thickness of neighboring grains imposes high challenges on the spin-on of etch resistand on the definition of adequate exposure times. Concerning the screen printed grid a smearing out ofthe metallization paste is observed on sites of grain boundaries, where trenches are present or theneighboring grains differ in height. On more elevated grains the grid fingers are typically more narrowbecause of the reduced distance to the screen printing mask. Both features – smearing out and differentwidth of contact fingers – are related to the application of screen printing on rough surfaces.Comparing the two images in Figure 6.17, the significant difference in contact width becomesapparent.


Figure 6.17: Emitter contact crossing grain boundaries. Left: Contact definition by photolithography.Right: Screen printed contact.

The effect of different base layer thicknesses and surface morphology on short-circuit current densityhas been studied by SR-LBIC13 measurements. Figure 6.18 shows a mapping of effective minoritycarrier diffusion length determined from SR-LBIC and corresponding reflection measurements for anepitaxial solar cell prepared by the standard cleanroom process 1. The grain boundaries are clearlyvisible as regions of low minority carrier diffusion lengths. Crystal imperfections already present inthe substrate continue in the epitaxial layer and are visible in the map as spots or lines (scratches) withlocally reduced diffusion length. Deviations in Leff for different grains were found to correlate todifferent epilayer thicknesses and to the presence of growth-induced texturing. The greatest diffusionlengths were measured for grains with thick, textured epilayers.

46 mm

10

65

Leff [µm]

Figure 6.18: Mapping of effective minority carrier diffusion length for an epitaxial thin-film solarcell on multicrystalline silicon substrate.

13 SR-LBIC: Spectrally Resolved Light Beam Induced Current.


Lock-in thermography was applied to analyze the shunts effecting the solar cell performance. InFigure 6.19 the lock-in thermograms (amplitude image) measured at 0.5 V forward bias formulticrystalline and monocrystalline epitaxial solar cells prepared by process 1 and 3 are depicted.

Independent on solar cell process technology the thermograms for monocrystalline solar cells aredominated by edge shunts. This is a feature commonly observed in solar cell thermograms and isrelated to technological instead of material imperfections [134]. Point-like shunts located within thecell area and edge shunts are visible in the thermograms of the corresponding multicrystalline solarcells. In fact, such shunts clearly dominate the thermogram of the multicrystalline solar cell preparedby process 1.

The formation of point-like shunts for multicrystalline solar cells can be attributed to the imperfectcrystal structure of the material. The thermograms in Figure 6.19 show that the occurrence of leakagecurrents is also affected by the solar cell process. The passivation of emitter and bulk by the SiNx layeris assumed to be responsible for the reduction in shunt formation for the mc-Si solar cell with screenprinted contacts. However, the measurements do not allow an unambiguous determination of the mainfactor responsible for the increased formation of shunts in case of process 1.

Epitaxial solar cells onmc-Si

Epitaxial solar cells onCz-Si

Process 1

TF emitter (80 Ω/sq)

Evaporated contacts

Process 3

TF emitter (40 Ω/sq)


Figure 6.19: Thermograms measured for epitaxial thin-film solar cells on mc-Si (left) and Cz-Si(right) substrates (amplitude image, 0.5 forward bias). Solar cell process 1 and 3 arecompared.

In conclusion, it has been demonstrated that industrial screen printing processes could be successfullytransferred to epitaxial cells on multicrystalline substrates. The surface morphology of epitaxied mc-Si


substrates was found to impose high challenges on both contact formation techniques,photolithography and screen printing. The multicrystalline structure of the material requires theapplication of suitable passivation schemes e.g. hydrogen passivation or the deposition of apassivating SiNx layer, as done for the formation of screen printed contacts. For epitaxial thin-filmsolar cells on heavily doped multicrystalline Silso material the best solar cell prepared by screenprinting technologies featured a VOC=610 mV, JSC=25.0 mA/cm² and a FF=76.8% resulting in anefficiency of 11.7%, confirmed by Fraunhofer ISE Calibration Laboratory.

6.4 Solar cells on reclaimed silicon wafersIn microelectronic production lines, reclaimed silicon wafers are often used for process monitoring outof cost-saving reasons. To make a re-utilization possible, the reclaim process must accomplish acomplete removal of all layers (dielectric, metallic or other) deposited on the original silicon wafer andensure a contamination-free surface. Furthermore, the recycling process aims to remove only littlematerial from the wafer to make a multiple re-use possible.

Reclaimed wafers from microelectronic industry represent an interesting option as potential low-costsubstrate material for epitaxial silicon thin-film solar cells. The preparation of a thin-film solar cell ona reclaimed silicon wafer is less sensible to substrate properties compared to microelectronic devices.A less sophisticated reclaim procedure might be sufficient thus further contributing to the aspect ofcost-saving.

Single-crystal silicon reclaim wafers from microelectronics industry were supplied by the companyAstroPower (Delaware, USA) for a re-use as substrates in epitaxial thin-film solar cells. The reclaimprocedure included a mechanical removal of all devices by sand-blasting and a wet-chemical surfacecleaning in a NaOH solution. The specific resistivity and the thickness of the electronic grade waferswas determined to 0.01 Ωcm and 600 µm respectively. Prior to further processing, the 6” wafers werecut into 50x50 mm² samples by laser scribing.

The wafers were treated by different cleaning methods, resulting in different surface morphologies:

a. No additional treatment. Mean roughness: 3.7 µm.

b. Removal of 100 µm from the surface by wet-chemical CP133-damage etch. Mean roughness:1.6 µm. The strong etching led to an increased fragility of the edges and a significant reduction inwafer area. The latter aspect presented a severe problem to the formation of the front contact gridwhich is defined to a specific area.

c. Mechanical grinding of one surface with a final wafer thickness of 400 µm. The surface damageintroduced by the grinding was removed by KOH etching. Mean roughness: 0.6 µm. The epitaxiallayer is grown on the ground surface.

d. Mechanical grinding of both surfaces with a final wafer thickness of 400 µm. Further treatmentand mean roughness are identical to c.

The main characteristic for pre-treatment b to d is that a large amount of material is removed from thesurface prior to epitaxy. All samples were RCA-cleaned prior to epitaxy. Solar cells were preparedusing process 3 with industrial screen printing technology and for reference, a selection of sampleswas introduced into the standard cleanroom process 1.

6.4 Solar cells on reclaimed silicon wafers 117

For an evaluation of the pre-treatment methods, solar cells from process 3 were analyzed. Within eachpre-treatment group, samples with similar or equal epilayer thickness were used for the calculation ofthe mean values which are depicted in Table 6.9. For an interpretation of the different pre-treatmentmethods the difference in epilayer thickness between each group has to be accounted for.

Best efficiencies were obtained for epitaxial thin-film solar cells on ground reclaim substrates. Solarcells of type c and d feature similar characteristics, indicating that the condition of the rear surfacedoes not affect the solar cell performance. The difference in short-circuit current density can beattributed to the different epilayer thickness. The high reproducibility of the grinding and the epitaxyprocess respectively are reflected in the comparatively low standard deviations.

Comparing solar cells of type b and d a decrease in VOC, JSC and FF can be observed for the wet-chemically treated samples. The mean epilayer thickness is larger for type b and therefore the decreasein short-circuit current cannot be traced back to a thinner base layer. The same feature can be foundfor solar cells with type a pre-treatment. This characteristic (reduced JSC and VOC with increasingepilayer thickness) can be explained if low minority carrier lifetimes in the base are assumed. Thecomparatively low fill factor for solar cells with pre-treatment b is attributed to technological problemsin contact formation and edge isolation due to the fragility of the samples.

Pre-Treatment dbase VOC JSC FF Efficiency[µm] [mV] [mA/cm²] [%] [%]

a none 37 597 ± 5 22.3 ± 0.4 77.5 ± 0.6 10.3 ± 0.4

b CP-133 35 610 ± 3 23.0 ± 0.2 74.6 ± 3.8 10.5 ± 0.5

c 1 side ground 33 614 ± 1 24.4 ± 0.1 77.1 ± 0.1 11.6 ± 0.1

d 2 sides ground 30 613 ± 2 23.6 ± 0.4 78.1 ± 0.1 11.3 ± 0.2

Table 6.9: Mean values for epitaxial solar cells on reclaimed Cz-Si wafers prepared by solar cellprocess 3. The different substrate pre-treatments are compared.

Figure 6.20 shows internal quantum efficiency characteristics measured for solar cells of type a, b andd. The epilayer thickness of 25 µm is the same for all cells. For comparison, the IQE curve for a solarcell on epitaxial reference material (30 µm epilayer grown on highly doped Cz-Si in a commercialsystem) prepared in the same solar cell process is included.

For the entire spectral range, the solar cell without additional pre-treatment (type a) reveals the lowestresponse. The characteristics for type b and d are similar with type d being slightly superior. Thespectral response is clearly correlated to the pre-treatment of the samples. Wet-chemical CP-133damage-etch and a grinding of the surface result in a comparable epilayer quality. The mechanicalremoval of the devices by sand-blasting and the subsequent NaOH treatment possibly results in ahighly defected wafer surface, inadequate for high-quality epitaxy. Another explanation for the lowresponse of type a solar cells might be that surface near regions are still contaminated by impuritiesafter the reclaim procedure. During high-temperature CVD these impurities could easily diffuse intothe epilayer leading to reduced carrier lifetime. Future work on reclaim material will have to deal witha characterization of impurities in the substrate material and in the epilayers e.g. by means of GDMS(Glow-Discharge Mass Spectrometry).


Compared to the internal quantum efficiency measured for the epitaxial reference cell, the CP-etchedor ground samples show a similar blue response and are only slightly inferior in the mid-wavelengthrange. The superiority of the epitaxial reference cell in red response is attributed to a combination ofbetter minority carrier diffusion length, thicker base layer and probably a reduced interfacerecombination velocity.

The best efficiencies were reached on ground substrates for both solar cell process types. In Table 6.10the illuminated I/V solar cell parameters of the best solar cells are summed up.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

Epitaxial Ref. a - as received b - CP133 d - ground on both sides

IQE

λ [nm]

Figure 6.20: Internal quantum efficiency for epitaxial thin-film solar cells on highly doped reclaimwafers with different epitaxial pre-treatment.

Area Sample dbase VOC JSC FF EfficiencyProcess[cm²] [µm] [mV] [mA/cm²] [%] [%]

1 21.2 Reclaim (d)* 22 630 28.6 74.5 13.4

FZ-Si Ref. 634 35.9 78.5 17.8

3 23.0 Reclaim (d) 35 615 23.9 78.3 11.5

FZ-Si Ref. 621 30.7 76.7 14.6

* Confirmed measurement by ISE Calibration Laboratory

Table 6.10: Solar cell parameters of best solar cells achieved on epilayers grown on ground, highlydoped reclaim wafers.

Comparing the solar cell results of the epitaxial cells to the FZ-Si reference cells shows the potentialof the realized concept. Apart from small reductions in open-circuit voltage, the main loss for theepitaxial cells can be observed in short-circuit current.

Future activities will focus on the optimization of the reclaim procedure for an application of reclaimwafers as substrate material for epitaxial thin-film solar cells.

6.5 Front surface texturing for epitaxial cells 119

6.5 Front surface texturing for epitaxial cellsFor epitaxial thin-film solar cells the short circuit current and thus the efficiency can be increased bytexturing the front surface. Conventional lab-type solar cell processing of single-crystal wafersemploys anisotropic random texturing to reduce the optical front side reflectance. Because of theanisotropy this technique is less effective on mc-Si wafers. In this case, mechanical V-grooving orReactive Ion Etching (RIE) can be alternatively used for texturing.

Considering epitaxial cells these techniques can similarly be utilized. Random pyramids are mosteffective if the depth extends to several microns. Application of such a texture on an epitaxied samplemeans that part of the epitaxy has to be removed or in fact wasted. V-grooving of the substrate resultsin a structure with a typical scale length of 50 to 100 µm and epitaxial films are typically grown onalready V-grooved substrates. However, the front metallization on these deep grooves still represents achallenge to solar cell processing [135].

Following the concept of an epitaxial thin-film solar cell on a low-cost single-crystal silicon substratea texturization method which allows for good optical properties, no or low consumption of the epilayerand industrial feasibility is the most attractive.

Instead of applying an anisotropic etching step after epitaxy Cz-Si substrates were textured before theepitaxial growth of the base. The etch rate of the applied KOH solution strongly depends on thedoping density and silicon wafers with boron concentrations exceeding ~1x1019 cm-3 act as an etchstop [136]. For <100>-oriented Cz-Si wafers with doping level of 4x1018 cm-3 the texturization processcould be successfully optimized to yield low reflecting surfaces. Texturing was done using aKOH/IPA14 solution at elevated temperature. Subsequently epitaxial layers of 30 µm thickness weregrown on these textured substrates. In Figure 6.21 measured reflection curves and corresponding SEMimages of a textured substrate with and without epitaxial layer are shown.

400 600 800 1000 120010

20

30

40

50

60

70

Ref

lect

ion

[%]

λ [nm]

Substrate plane textured textured with 30 µm epilayer

Figure 6.21: SEM image (left) and reflectivity measurement (right) of a KOH textured substrate withand without epitaxy.

14 IPA: Isopropanol.


The SEM image in Figure 6.21 (left) show that the texturing resulted in random pyramids with a meanbase length of 8 to 10 µm. The corresponding reflection curve proves the effectiveness of the texturingin terms of a significantly reduced overall reflectivity of 12%. After epitaxy, the surfaces of thesamples were nearly planar and the optical properties were only slightly improved compared to theplane substrate. The smoothing of the textured surface is a typical characteristic of high temperatureCVD at atmospheric pressure [24].

The experiment verifies that structures on a significantly larger scale than the epilayer thickness arenecessary if the texture is to be transferred from substrate to epitaxial layer.

6.6 Innovative solar cell technology by CVDThis section aims to give a preview on possible alternative applications of high-temperature APCVDdepositions and reactors. The basic ideas of three different innovative CVD processes are outlined.While preliminary experiments and considerations have already been carried out, the verification oftechnological and economical feasibility has still to be accomplished in future work.

6.6.1 Emitter epitaxyUp to now, only little research has been done on the application of n-type epitaxial layers for solarcells. In [137] n-epitaxy has been performed by LPE and a multilayer junction thin-film solar cell hasbeen prepared on a stack of six layers with alternating doping type grown on a highly doped p-typesubstrate. Another example is given in [24], where a n-type APCVD epilayer serves as base layer forcrystalline silicon thin-film solar cells prepared by the PSI-process.

Conventional emitter formation is done by diffusion from a POCl3 source in a tube furnace andsubsequent PSG etching. The entire process step is time consuming and wet chemicals have to beused. The epitaxial deposition of n-type phosphorus doped layers by CVD represents an interestingalternative to conventional emitter formation. Epitaxial layers can be grown at high rates up to10 µm/min, the layers can be doped in situ by adding the appropriate dopant gas, doping profiles canbe adjusted and no additional wet-chemical treatment is necessary.

In [138] the technical and economical feasibility of epitaxial emitters was investigated. Solar cellsimulations assuming a standard high-efficiency solar cell process showed that epitaxial emitters canindeed compete with conventional diffusion. Assuming a high throughput reactor as presented insection 3.4.4 the cost-effectiveness of the entire process was demonstrated.

6.6.2 Boron BSF epitaxy and diffusionThe effectiveness of a back surface field depends on the surface concentration, on the profile of the p+

layer and on the recombination activity of the interface at the high-low junction [10]. The p/p+ junctionis typically prepared by diffusion or alloying, using aluminum or boron as dopants. In industrialprocessing, the back surface field is formed by screen printing of Al on the rear side of the cell and asubsequent anneal above the eutectic temperature. The gettering effect or BSF effect of the Al backsurface or a combination of both are assumed to be responsible for the improvement in solar cellperformance [139].

Compared to Al greater surface concentrations can be achieved if boron is used as dopant thus makingboron a more attractive choice for BSF formation. The diffusion coefficient of boron in silicon is

6.7 Summary 121

much smaller compared to aluminum making larger temperatures (>1000°C) and increased processtimes necessary for the diffusion step. As an alternative, boron BSF layers can also be formed by ion-implantation. However, neither technology is suitable for industrial scale production.

CVD offers the possibility to deposit heavily boron-doped silicon layers on any kind of substrate thuscreating large doping gradients beneficial for an effective BSF. A surface doping concentrationexceeding 1x1019 cm-3 can easily be achieved and high deposition rates above 5 µm/min enable a fastprocessing. For the epitaxial deposition the wafers have to be exposed to high temperatures above1100°C. The applicability of an epitaxial boron-BSF to conventional Cz-Si wafers depends on theimpact of such a high-temperature treatment on the electrical properties of high-quality material.

In section 5.3.1 a diffusion of boron from the gas phase has been observed leading to high surfacepeak concentrations of 6x1019 cm-3 and a junction depth in the micron range. A diffusion time of 5 minwas sufficient to generate this profile. The diffusion has been carried out in the RTCVD100 reactorusing high temperatures above 1100°C and B2H6 diluted in hydrogen as dopant source. Using thisdiffusion method, the diffused boron profiles are assumed to be tunable by variation of dopant gasflow, diffusion temperature and diffusion time. In [99] the application of this diffusion technique forthe preparation of ultra-thin-base Si bipolar transistors has been reported. Compared to the epitaxialdeposition of a highly-doped boron layer, lower junction depth can be more easily achieved, lowerprocess temperatures can be used and no trichlorosilane is consumed. For the preparation of lowjunction depth the vapor phase diffusion of boron from B2H6 is therefore superior to the epitaxy of lowresistivity silicon layers.

6.6.3 In-situ HCl texturingIn-situ HCl texturization represents an interesting alternative to wet-chemical texturing of epilayers.Traditionally HCl in-situ etching is an additional step within the epitaxy process of silicon wafers. Athin surface layer is removed from the substrate preparing it for silicon epitaxy. For this applicationthe HCl in-situ etch step is optimized to result in a smooth substrate surface. Under different processconditions a texturing or roughening of the substrate surface can also be achieved [57]. This effectcould be utilized for a front surface texturing of epitaxial layers. Considering a continuous CVDreactor, the HCl texturing step could be implemented in an in-line CVD process by adding anadditional reaction chamber to the reactor.

6.7 SummaryThe successful application of industrial screen printing technologies on epitaxial silicon thin-filmmaterial was highlighted in this chapter. Highly doped Cz-Si substrates were used to characterize thequality of epilayers grown in the lab-type RTCVD100 reactor and to evaluate the effect of differentsolar cell process technologies on the epitaxial material. Subsequently, industrial solar cell processtechnologies were applied to epilayers on highly-doped mc-Si wafers and on potential low-costreclaimed wafers. Epitaxy and solar cell processing were successfully accomplished on all substratetypes and the results show that the quality of epitaxial films deposited in the RTCVD100 reactor atFraunhofer ISE is sufficient to reach high solar cell efficiencies. It was demonstrated that epitaxialthin-film solar cells can equally well be processed by screen printing technologies and standardcleanroom techniques irrespective of substrate material making a direct introduction of epitaxial waferequivalents into standard industrial production lines possible.


Doubling of the silicon deposition growth rate from 5 to 10 µm/min results only in minor losses inefficiency but a substantial increase in throughput, making the fast growth mode an attractive choicefor high throughput manufacturing.

A record efficiency of 13.1% was obtained for a 35 µm epitaxial base layer on highly doped Cz-Sisubstrate prepared by screen printing technologies. For the first time reclaimed single-crystal waferswere used as substrate material. The best solar cell on this substrate type reached an efficiency of11.5% with VOC=615 mV, JSC=23.9 mA/cm² and FF=78.3% using screen printing techniques.

Solar cell results and device simulation demonstrated that optical confinement schemes are essentialfor epitaxial thin-film cells. A significant increase in short-circuit current can be expected if e.g. frontside texturing is applied.

Finally, innovative future applications for epitaxial CVD layers were suggested e.g. epitaxy of emitterlayers and formation of boron BSF by epitaxy or vapor-phase diffusion.

123

7 Silicon thin-film solar cells on insulating substrates

Silicon thin-film solar cells on low-cost substrates can significantly reducecost for photovoltaics due to their potential for high efficiencies comparableto wafer silicon solar cells. The application of insulating substrates enablesan integrated series connection of solar cells simultaneously processed onone large substrate, thus eliminating the necessity for e.g. cell connectors.

The principle layer structure and solar cell process technologies for thin-film solar cells on insulating substrates are described with respect to thehigh-temperature approach. Within this work various ceramic materialshave been investigated as potential low-cost substrates. Multicrystallinesilicon thin-films were prepared on these materials and characterized interms of crystallographic, chemical and electrical properties. Based on thesefindings and on solar cell results the suitability of the examined ceramicsubstrates is discussed.

7.1 Solar Cell principle and technologyThe concept of crystalline silicon thin-film solar cells on insulating substrates is based on thepreparation of a thin, active silicon base layer on a low-cost, electrically insulating substrate. Typicalfeatures of a thin-film solar cell on insulating substrate are the implementation of diffusion barriers orhighly reflective intermediate layers between substrate and silicon film, the application ofrecrystallization steps to enlarge the grain size of polycrystalline silicon layers grown on the non-silicon substrate, bulk and surface passivation schemes, effective optical confinement features and acontact scheme, where emitter and base contacts are both located on the front side of the cell.

Compared to epitaxial thin-film solar cells this cell structure is much more complex but in return itenables a series interconnection of several cells processed on the same substrate. Other advantages arethe possibility to realize effective optical confinement features e.g. by using highly reflectivesubstrates, and the independence from the use of silicon as substrate material.

At Fraunhofer ISE the high-temperature approach is pursued for the preparation of silicon thin-filmsolar cells. This approach allows the application of APCVD for a fast deposition of silicon films,liquid-phase recrystallization of silicon layers by zone-melting and the use of conventional solar cellprocessing technologies.

7.1.1 Layer systemWithin the high-temperature approach stringent requirements are imposed on the physical propertiesof potential substrate materials: high-temperature stability, thermo-shock resistivity, homogeneousthermal conductivity and matching of thermal expansion coefficient (TEC) to silicon are the mostimportant demands to be fulfilled. Combined with the request for low production cost the choice of

7.1 Solar Cell principle and technology124

substrate materials is limited to silicon wafers or ribbons from metallurgical grade silicon powders anddifferent types of low-cost ceramics.

The production cost for ceramic materials can be substantially reduced if inexpensive manufacturingtechnologies and low-cost starting powders are used. With respect to process technology the tapecasting technique represents an attractive option to produce large area ceramic sheets at comparativelylow expenses. The cost for ceramic powders is determined by their purity and low-cost is thereforecorrelated to large, mostly metallic, impurity concentrations.

In silicon solar cell materials, impurities like oxygen and carbon can be tolerated in the base layer athigh concentrations and are typically present up to their solubility level in commercial Cz-Si wafers15.In contrast, transition metals like e.g. vanadium or titanium are detrimental for minority carrierlifetime and cannot be accepted even in concentrations below 1 ppba [140]. Using substrates with highimpurity concentrations, the active silicon layer is endangered to be contaminated during high-temperature processing by impurities diffusing out of the substrate. Such a contamination can bereduced or entirely avoided if adequate diffusion barriers are implemented.

Similar to the substrate material, the barrier layers must be chemically and mechanically stable duringthe entire sample preparation and solar cell process. In addition the deposition of these layers must beindustrially feasible and inexpensive. A combination of silicon dioxide and silicon nitride layerseffectively prevents the diffusion of many harmful transition metals and is known to resist hightemperatures [141]. Using APCVD these layers can be deposited at comparatively low cost. PECVDSiO2 or SiO2/SiNx layer stacks are used as standard barrier layers at Fraunhofer ISE.

The direct deposition of a silicon layer onto a foreign substrate by CVD results in polycrystalline filmsfeaturing small grain sizes in the range of 1 µm. Solar cells prepared on such low-quality layers aretypically limited in performance by large saturation currents and shunts. Most thin-film conceptstherefore apply a recrystallization step, where the polycrystalline silicon is transformed into a layerwith coarse grained crystal structure. Recrystallization can be done e.g. by laser or optical systems,with the latter technique being used within the frame of this work. A detailed description of the ZMRapparatus constructed and used at Fraunhofer ISE can be found in [142].

The recrystallized layer is usually heavily doped and represents the back surface field and the basecontact of the cell. Finally, the active base layer with thickness below 50 µm is epitaxially grown ontothe recrystallized multicrystalline layer.

Excellent efficiencies of 16% have been reported by Mitsubishi Electric Corporation for a large area100x100 mm2 silicon thin-film solar cell on a SOI16 structure prepared by ZMR demonstrating thepotential of this technique [143].

7.1.2 Cell technologyFor solar cell processing samples based on contaminated substrate materials have to be encapsulated toprevent an out-diffusion of harmful impurities. Using porous substrates, the encapsulation at the sametime serves as a shield against penetration of chemicals and filling of the open pores during wet

15 Impurity concentrations in Cz: C(O2) ≤ 2x1018 cm-3, C(C) ≤ 5x1017cm-3 [103].16 SOI: Silicon On Insulator.


chemical processing. Alternatively, a completely dry solar cell process can be applied, where noadditional encapsulation is necessary. In [144] the successful dry processing of a silicon thin-film solarcell on graphite substrate was reported.

The application of insulating substrates requires a contact scheme where both, emitter and basecontacts, are located on the front side of the solar cell. Alternatively, electrical contact to the base canalso be provided by a highly conductive layer at the back of the base. In [145] an interdigitated griddesign has been applied to thin-film solar cells prepared by the SIMOX17 technology leading to highefficiencies of up to 19.2%.

In [146] the concept of interdigitated grid has been transferred to industrial relevant processingtechniques. Within this study different technological realizations of an interdigitated grid wereinvestigated and in conclusion best results were achieved using the BBC-concept (Buried BaseContacts). This concept employs homogeneous emitter diffusion, screen printing of an etch resistpattern for the definition of the base region, local etching of the emitter by RIE, stripping of the etchresist, surface cleaning by oxygen plasma and screen printing of both contact grids. Using thistechnique efficiencies of up to 11.5% could be achieved on Cz-Si wafers [119].

Typical thin-film systems based on recrystallized and epitaxially thickened silicon layers feature anincreased surface roughness which imposes high demands on the technology of contact formation.Recent results on the application of the BBC-concept to silicon thin-film structures showed thatsurface roughness in fact represents a severe problem for contact formation and that large shadinglosses due to the two front contact grids limit the cell efficiency [147].

7.2 Silicon thin-film solar cells on ceramic substratesDuring the last decade, a large variety of different potential low-cost ceramics including graphite[148], SiSiC [149], Mullite18 [150], SiAlON [151], Al2O3 [152], SiN [141] and ZrSiO4 [153] has beentested as substrate material. Table 7.1 gives an overview on the best efficiencies achieved so far forsilicon thin-film solar cells on ceramic substrates. Zone-melting recrystallization has been applied forthe preparation of all solar cells. For comparison, the best result obtained for a thin-film solar cell withrecrystallized layer on a SiO2 encapsulated single-crystal silicon substrate is added.

The work presented in this chapter has been accomplished within the frame of the EuropeanSUBARO19 project. One of the major objectives of this project is to evaluate the application ofdifferent ceramics as substrate materials for a cost-effective preparation of silicon thin-film solar cells.

17 SIMOX: Separation by Implanted Oxygen.18 Mullite: Stable phase in the SiO2-Al2O3 system.19 SUBARO: Substrate and barrier layer optimization for CVD-grown thin-film crystalline Si solar cells.

7.2 Silicon thin-film solar cells on ceramic substrates126

Substrate Barrier layer Base[µm]

Area[cm²]

Solar cell process Efficiency[%]

Ref.

Single crystal Si Thermal SiO2 50-60 4 Conventional contacts by via-holesTexture, hydrogen passivation

16.45 [20]

Graphite LPCVD-SiC(conductive)

30 1 Conventional contact schemeRPHP20

11.0 [144]

Mullite ONO 49 1 Hydrogen passivation 8.2 [150]

ZrSiO4 ONO 30 1 Texture, RPHP 8.3 [153]

Si3N4 ONO 30 1 Texture, RPHP 9.4 [141]

SiSiC ONO/µc-Si/ONO 30-90 1 Dry solar cell process 9.3 [149]

Table 7.1: Efficiency table for crystalline silicon thin-film solar cells on ceramic substrates.

7.2.1 Material and solar cell preparationWithin this work, tape cast SiAlON and Si3N4 ceramics, hot-pressed Si3N4 and reaction-bondedsilicon-infiltrated SiC (SiSiC) ceramics have been investigated as substrate material. All of theseceramics feature a thermal expansion coefficient close to silicon and are known to resist hightemperatures. The suitability of the materials in terms of cost-effectiveness is evaluated within theSUBARO project.

All samples were treated by the same process steps and were characterized by the same methods toallow for a direct comparison of sample properties. In Figure 7.1 the sample structure (left) andprocess sequence for sample preparation (right) are illustrated.

Wet chemical cleaning

High-temperature anneal

Wet chemical cleaning

Characterization

PECVD of SiO2 capping layer

Zone-meltingrecrystallization (ZMR)

Removal of capping layer andpre-epitaxial cleaning

CVD of epitaxial base layer

Solar Cell ProcessCeramic substrate

1 µm SiO2

Recrystallized silicon layer (BSF)10 µm

Epitaxial base25 µm

100 nm SiNx

1 µm SiO2 ONO

PECVD of ONO barrier layer

CVD of silicon seeding layer

Figure 7.1: Schematic of realized sample structure (left) and process sequence for the preparation ofsilicon thin-films on ceramic substrates (right).

20 RPHP: Remote Plasma Hydrogen Passivation.


After a wet chemical cleaning all ceramic substrates were treated by a high-temperature annealing stepat 1200°C under nitrogen atmosphere. A second cleaning step was included to remove any impuritieswhich might have formed on the sample surface during thermal anneal. Subsequently the ceramicsubstrates were encapsulated by an oxide-nitride-oxide (ONO) barrier layer system of 1 µm SiO2,100 nm SiNx and 1 µm SiO2 deposited by PECVD. The application of an ONO system as intermediatelayer is based on results presented in [154], where its effectiveness as diffusion barrier for differenttransition metals is reported. For part of the samples a 2 µm PECVD SiO2 layer has been used insteadof the ONO stack for comparison. On top of the intermediate layer a thin (10-15 µm), highly dopedsilicon film was grown by APCVD at 950°C (seeding layer). Because of the high doping level above1x1018 cm-3 this layer serves as back surface field in the final solar cell structure. Prior to ZMR thesilicon film was covered by a 2 µm thick SiO2 capping layer deposited by PECVD to prevent balling-up of the liquid silicon during recrystallization. After ZMR the capping layer was removed byhydrofluoric acid and a short CP-133 etch was applied for pre-epitaxial cleaning of the silicon surface.Finally, the active base layer was grown epitaxially onto the recrystallized silicon film by APCVD.

After seeding layer deposition and epitaxy the samples were characterized by optical Nomarski-interference microscopy and SEM on cross sections and surfaces. Doping and impurity concentrationwere measured across the entire layer system using SRP and Glow-Discharge Mass Spectrometry(GDMS). During ZMR two CCD cameras enabled an in situ observation of the zone-melting process.The shape of the solidification front, the width and the shape of the molten zone gave additionalinformation on the crystal quality of the recrystallized layers but also on thermal properties of thesubstrate or the entire sample.

ceramic substrate

DLARC

emitter contact grid

barrier layers

base contact

p+p-type base n+

Photolithographic definitionof base contacts

Evaporation of Al for baseframe contact

RPHP

Deposition of DLARC

Alkaline texturing

Emitter formation by POCl3-diffusion

Photolithographic definitionof emitter contact grid

Separation of base andemitter by RIE

Evaporation and electroplating of emitter contacts

Photolithographic definitionof solar cell area

Figure 7.2: Solar cell scheme and processing sequence for one-side contacted solar cells oninsulating substrates prepared within this work.

Solar cells were prepared on samples based on Si3N4 and SiSiC ceramic substrates using a cleanroomprocess with photolithographic process steps. Figure 7.2 shows the mesa-like solar cell structurerealized on all samples. The solar cell formation included alkaline etching of the silicon base layer forlight trapping, homogeneous emitter diffusion in a closed tube furnace from POCl3 source (100 Ω/sq),photolithographic definition of emitter contact grid, evaporation of TiPdAg and electro plating ofemitter contacts, photolithographic definition of solar cell area and separation of emitter and base byRIE, photolithographic definition of base frame contact, evaporation of Al for base contact, Remote


Plasma Hydrogen Passivation (RPHP) and deposition of a double layer antireflection coating(DLARC) of TiO2/MgF2. Solar cells with an area of 1 cm2 were prepared. Using this solar cell processan efficiency of 13.5% has already been reached for a recrystallized silicon film on SiO2-encapsulatedmc-Si substrate [69].

The rough surface induced by the alkaline texture made the application of photolithographic stepsdifficult. Local accumulation of etch resist, inhomogeneous thickness of the masking oxide layer andnon-optimized exposure times lead to an incomplete exposure, leaving locally undeveloped areas. As aconsequence the emitter grid lines were partly interrupted, very thin or sometimes even separated fromthe bus bar. Neither hydrogen passivation nor antireflection coating were optimized for this solar cellstructure. Altogether there is still room for improvement from the viewpoint of solar cell processingtechnology.

The resulting solar cells were analyzed by illuminated and dark I/V-characteristics, spectral responseand SR-LBIC measurements. Combined with the results obtained from sample materialcharacterization, an evaluation of the different ceramic materials for an application in thin-film siliconsolar cells was accomplished.

7.2.2 Silicon thin-films on silicon-infiltrated silicon carbide ceramics (SiSiC)Reaction bonded silicon-infiltrated silicon carbide (SiSiC) substrates were provided by the companyH.C. Starck Ceramics (Selb, Germany). According to the manufacturer the SiSiC contained 0.34 wt%of boron making the ceramic electrically conductive. The 900 µm thick samples were single-sidepolished and featured an open porosity below 1%.

In general, SiSiC is resistant to temperatures up to the melting point of silicon, it is very hard and itsthermal expansion coefficient is close to that of silicon21. The silicon-infiltrated silicon carbideconsists of a SiC matrix with silicon filling up the pores thus giving a low bulk porosity.

Sample preparation and characterization

Silicon layers deposited on ONO and SiO2-encapsulated SiSiC ceramic substrates featured ahomogeneous surface morphology. A microscopic characterization of cross sections revealed smoothsubstrate surfaces covered by undamaged and equally smooth intermediate layers (Figure 7.3),indicating that substrate, barrier and silicon layer fit together in terms of thermal, mechanical andchemical stability for process temperatures up to 950°C.

Recrystallization of the silicon seeding layers was successful and partly dendritic and cellular growthfronts dominated the recrystallization process. The dendritic growth mode could be associated to asupercooling in the silicon melt caused e.g. by high impurity concentrations in the melt [156]. Acellular (or facetted) growth front generally indicates an oriented growth of high-quality crystallites.Although the dendritic growth mode is less favorable than the cellular one, large grains could beobtained.

21 TEC of silicon: 2.616-4.5x10-6 K-1 (300-1400K) [155].


10 µm

p+-Si

SiSiC ceramic

ONO

Figure 7.3: Cross section micrograph of SiSiC ceramic substrate with ONO barrier layer and siliconseeding layer (p+-Si).

Chemical and electrical analysis

To evaluate the efficiency of the applied barrier layers (SiO2 and ONO) the chemical composition ofthe entire layer stack from epitaxial base to substrate was characterized by GDMS. Figure 7.4 (left)shows the impurity concentration profile measured for a silicon film on SiSiC ceramic substrateencapsulated by a 2 µm SiO2 barrier layer.

The highly doped recrystallized silicon seeding layer is denoted by p+-Si (BSF) while the epitaxiallayer corresponds to the p-Si region. The location of the BSF can be easily identified by an increase ofthe boron signal. The onset of the substrate is visible as a rise in the characteristic impurityconcentration of the corresponding substrate material, which is carbon for SiSiC. Because of themeasurement principle the depth resolution is limited and the location of the interface betweendifferent regions can only be approximated. Hollow symbols denote measurement signals below thedetection limit.

0 1 2 3 4 5 6 7 8 9 1010-3

10-2

10-1

100

101

102

103

104

105

106

SiO2

Subs

trate

B11 C12 N14 P31 Ti48 V51 Cr52 Mn55 Fe56 Ni58 Cu63

Con

cent

ratio

n [p

pma]

Sputter time [A.U.]

p+-Sip-Si

5 10 15 20 25 301016

1017

1018

1019

1020

BSFBase

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Figure 7.4: Left: GDMS impurity profile of a silicon film prepared on a SiO2 encapsulated SiSiCceramic substrate. Right: Corresponding carrier density profile.

The GDMS measurement reveals a large contamination of the ceramic substrate by boron, phosphorusand various transition metals. Concentrations of 103 ppma and 20 ppma were determined for boronand iron respectively with the boron corresponding to the suppliers specification of 0.34wt%.


Noticeable amounts of phosphorus and the transition metals titanium, vanadium, chromium,manganese and nickel in the order of 0.1-2 ppma were detected in the SiSiC substrate.

Within the barrier and BSF layer the concentration of all impurity elements decreases substantially andin the base layer only iron and nickel are still detected in concentrations in the range of 0.01 ppma.This corresponds to a reduction by three and two orders of magnitude respectively, compared to thesubstrate concentration.

With the application of an ONO intermediate layer, the signal for the transition metals similarlydecreases in the p+-region and is below the detection limit within the epilayer. An exception to thisgeneral feature is iron: while no iron can be detected in the bulk of the base, a concentration in therange of 4 ppba is measured in the surface-near region. This result indicates that a transfer ofimpurities has occurred from substrate to silicon layer system in spite of the ONO barrier. Assuming adamage of the ONO layer such a transfer can either occur by diffusion or by a mixing of liquid siliconcoming from the substrate and the seeding layer during ZMR. Since no damage was observed byoptical microscopy, the scale length of the perforation must be in a range below the resolution limit ofthe microscope. The accumulation of iron near the sample surface might be caused by segregation.

In Figure 7.4 (right) the carrier concentration profile measured for a silicon film on SiSiC with ONObarrier layer is shown. The measured data correspond to the concentrations determined by GDMS. Thecarrier density in the BSF layer exceeds 1019 cm-3 although the seeding layer deposition processtypically results in concentrations in the range of several 1018 cm-3. The increased doping densityconfirms that a diffusion of impurities must have occurred from substrate to silicon layer system.

Solar cells on SiSiC ceramic substrates

A maximum efficiency of 10.7% was achieved for a 25 µm silicon base layer on SiSiC ceramicsubstrate with ONO barrier layer. This solar cell was measured at the Fraunhofer ISE CalibrationLaboratory and featured a VOC of 554 mV, JSC=28.9 mA/cm² and FF=66.8%. This represents anexcellent result for a thin-film solar cell on ceramic substrate (compare Table 7.1).

Because of the dendritic growth mode affecting the recrystallization process and the resulting regionsof minor crystal quality, the obtained efficiencies varied over a wide range from 3.4 to 10.7%. The lowquality of part of the silicon layers gave rise to high saturation currents of the space charge region andlow parallel resistance leading to fill factors below 50%.

In the following the characteristics of the best solar cell is discussed in more detail. In Figure 7.5 thedark I/V characteristic (left) and internal quantum efficiency curve (right) are illustrated for the bestsolar cell. The dark current characteristics shows that the solar cell performance is mainly affected bya large saturation current of the space charge region, thus reducing the fill factor. The series resistanceis comparatively low, indicating a sufficient thickness and doping level of the back surface field whichalso serves as back side contact.

In the short-wavelength range, the internal quantum efficiency (Figure 7.5, right) reaches high valuesabove 90%. The drop in spectral response around a wavelength of 600 nm is determined by the lowminority carrier lifetime in the base. In the range of 900-1000 nm an increase in IQE is obtained due tothe optical confinement induced by the ONO intermediate layer. Light reflected by the ONO layer isabsorbed in the base layer and contributes to short-circuit current.


0.0 0.2 0.4 0.6

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

Cur

rent

den

sity

[A/c

m²]

Voltage [V]400 600 800 1000 1200

0.0

0.2

0.4

0.6

0.8

1.0

IQE

λ [nm]

Figure 7.5: Dark current characteristic (left) and internal quantum efficiency (right) for the bestsilicon thin-film solar cell on SiSiC ceramic substrate.

Figure 7.6 shows a map of effective minority carrier diffusion length calculated from SR-LBIC andreflection measurements (left) and the corresponding histogram (right). The topography of Leff verifiesthat regions which were affected by dendritic growth (“branches” covering the bottom and part of theright side of the cell) result in low minority carrier diffusion lengths. The average effective minoritycarrier diffusion length of 24 µm calculated from the histogram is in the range of the base layerthickness, in accordance to the comparatively large efficiency obtained for this cell.

0

>50

Leff [µm]

0 2 4 6 8 10mm

0 10 20 30 40 50 60 700

2000

4000

6000

8000

10000

average Leff = 24µm

Cou

nts

Leff [µm]

Figure 7.6: Topography of effective minority carrier diffusion length as calculated from SR-LBICand reflection measurements (left) and corresponding histogram (right).

To examine the assumption of a damaged barrier layer, an aluminum back contact was evaporated onpart of the solar cells to enable conventional 2-side contacting. Independent from contact scheme thesame illuminated I/V-characteristics were measured, proving the permeability of the intermediatelayer.


Summary

Sample preparation and solar cell processing were successfully accomplished on SiSiC ceramicsubstrates. Chemical analysis of the substrate material revealed a high contamination level oftransition metals, phosphorus and boron. An improved barrier effect against these impurities wasdemonstrated for the ONO intermediate layer compared to SiO2. However, the detection of anincreased boron concentration in the recrystallized silicon layer, contamination of surface-near regionsof the epilayer by iron and finally the possibility to use a conventional 2-side solar cell contact schemeshowed that the ONO layer was not completely stable to all process steps.

During recrystallization the silicon layers were mainly affected by a dendritic growth mode, probablyinduced by inhomogeneous thermal properties of the substrate or a contamination of the siliconseeding layer by iron. Areas affected by dendritic growth featured low local short-circuit currentdensities. A confirmed efficiency of 10.7% was obtained for the best solar cell. This efficiencyexceeds the record value which has been published up to now for a similar solar cell structure [149] by1.4% absolute.

7.2.3 Silicon thin-films on hot-pressed silicon nitride ceramicsHigh density, non-conductive hot-pressed Si3N4 ceramic substrates were provided by H.C. StarckCeramics (Selb, Germany). The 530 µm thick samples were polished on one side to give optimalsurface conditions and an open porosity below 1% was specified.

Silicon nitride ceramics in general are known for their excellent mechanical stability even at hightemperatures and their resistance to thermal shock. The thermal expansion coefficient of silicon nitridelies between 2.9x10-6-3.6x10-6 K-1 for a temperature range of 273-1473K, which is slightly lowercompared to silicon. The manufacturing of Si3N4 by hot pressing allows the preparation of very densematerials.


The deposition of silicon seeding layers on encapsulated hot-pressed Si3N4 ceramic substrates resultedin homogeneous films. The cross section image in Figure 7.7 shows a planar substrate surface withclosed ONO layer.

10 µm

p+-Si

Hot-pressed Si3N4 ceramic

ONO

Figure 7.7: Nomarski microscope image of a sample cross section after silicon seeding layerdeposition (Secco etched).


The samples were found to respond well to the recrystallization process: cellular or planar growthfronts indicating an oriented crystal growth with low defect density, were the dominating features. Thewidth of the molten zone remained constant and stable during most recrystallization processes whichmeans that the thermal properties of the entire sample and especially the substrate are homogeneous.Large grains up to several millimeters in width and several centimeters in length were obtained byZMR.

After epitaxy, cracks were found to penetrate the entire silicon film from barrier layer to epilayersurface (Figure 7.8). The development of these cracks could be a consequence of a difference inthermal expansion coefficient between substrate and silicon films. Stress, which might have built upduring the cooling period of the epitaxy process could result in the formation of cracks. An analysis ofsample cross sections revealed a damage of both barrier layer types - SiO2 and ONO - after epitaxy.

p-Si

10 µm

p+-Si

Hot-pressed Si3N4 ceramic

ONO

Crack

Figure 7.8: After epitaxy, cracks penetrate the entire silicon film. Left: SEM image of samplesurface. Right: Optical micrograph of sample cross section (Secco etched).

Chemical analysis

The chemical analysis of silicon layer system and substrate by GDMS (Figure 7.9) revealedcomparatively low impurity concentrations in the ceramic substrate: phosphorus and iron are detectedwith concentrations of 0.1 ppma, while other metallic transition elements like e.g. titanium, chromium,vanadium and nickel occur in concentrations below 0.1 ppma. Except for iron no other transitionelement was detected in the silicon film, independent from the applied barrier layer. With aconcentration in the range of 1 ppba, the iron content in the silicon is comparatively low but can stillbe harmful to minority carrier lifetime.

The detection of iron in the silicon film is consistent with the observed perforation of both barrierlayer types which enables a diffusion of impurity atoms from the substrate into the silicon layer duringhigh-temperature processing.


0 1 2 3 4 5 6 7 8 9 10 1110-3

10-2

10-1

100

101

102

103

104

105

SiO2

Subs

trate

Con

cent

ratio

n [p

pma]

Sputter time [A.U.]

B11 C12 N14 P31 Ti48 V51 Cr52 Mn55 Fe56 Ni58 Cu63

p+-Sip-Si

Figure 7.9: GDMS measurement for a silicon thin-film prepared on hot-pressed silicon nitrideceramic substrate with SiO2 barrier layer.

Solar cells on hot-pressed Si3N4 ceramic substrates

Solar cells prepared on silicon films on hot-pressed Si3N4 ceramic substrates showed only littlephotovoltaic activity, if any at all. The best solar cell reached an efficiency of 2% with VOC=398 mV,JSC=15.9 mA/cm2 and FF=32%. The characteristics of this cell are discussed in the following.

Considering the dark current characteristics graphed in Figure 7.10 (left) it is evident, that the solarcell under consideration suffers from extremely low parallel resistance and an increased seriesresistance. In addition, large saturation currents affect the solar cell performance. Parallel and seriesresistance were determined to RP=32 Ωcm2 and RS=2.4 Ωcm2 by fitting the dark I/V curve

The internal quantum efficiency measurement (Figure 7.10, right) reveals a low response across theentire spectral range, confirming the measured low short-circuit current density. In the long-wavelength range the optical confinement by the ONO barrier layer is visible as a slight increasearound a wavelength of 1000 nm.

In Figure 7.11 (left) a topography of effective minority carrier diffusion lengths and a correspondingmicroscope image of sample surface and cross section (Figure 7.11, right) are depicted. The Leff

mapping shows that distinct regions of the solar cell suffer from low effective minority carrierdiffusion lengths. The right-angled network visible in the map was identified as cracks in the siliconfilm. Similar observations were already reported in [141].

The penetration of the cracks from epilayer surface to isolating barrier layer results in a splitting up ofthe entire solar cell area in single regions, which are electrically isolated from each other. As aconsequence, the emitter contacts are partly interrupted, a complete electro plating of evaporatedcontacts becomes impossible and the solar cell suffers from large series resistance.

Areas which are completely isolated are characterized by a zero effective diffusion length. Theseregions cannot contribute to photocurrent.


0.0 0.2 0.4 0.610-4

10-3

10-2

10-1

100

Cur

rent

den

sity

[A/c

m²]

Voltage [V]400 600 800 1000 1200

0.0

0.2

0.4

0.6

0.8

1.0

IQE

λ [nm]

Figure 7.10: Left: Dark current characteristics for thin-film solar cell on hot-pressed Si3N4 ceramicwith ONO barrier layer. Right: Corresponding internal quantum efficiency curve.

100 µm

Contact finger

Crack

0

>30

Leff [µm]

0 2 4 6 8 10mm

10 µm

Si-film

Contact finger

Crack

Figure 7.11: Left: Topography of effective minority carrier diffusion length as calculated from SR-LBIC measurements. The straight lines with increased values of Leff correspond tocracks, visible in the micrograph of the solar cell surface (right, top) and cross section(right, bottom).

An increased effective diffusion length is observed on sites of cracks. This phenomenon can probablybe explained by the formation of vertical pn-junctions during emitter diffusion. For carriers generatednear the crack, lower diffusion lengths are necessary to reach the vertical pn-channel instead of thehomogeneous emitter on the front surface, thus increasing the collection efficiency in these areas. In


Figure 7.11 (right, bottom) a filling of the gaps by contact metal is visible. If the emitter does notcover the flanks of the cracks, this would give rise to a short circuit of emitter and base.

Summary

Silicon seeding layer deposition and recrystallization process worked well for hot-pressed Si3N4

ceramic substrates. During epitaxy, cracks developed in the silicon layer system, possibly due to adifference in thermal expansion coefficient between substrate and silicon. In addition, a perforation ofthe barrier layers was observed after epitaxy. Iron was found to contaminate the base layerindependent from barrier layer system. A concentration in the range of 1 ppb was detected, indicatinga diffusion of iron from the ceramic substrate into the silicon film. The performance of the processedsolar cells is limited by the presence of electrically isolated regions generated by the cracks.

7.2.4 Silicon thin-films on tape cast silicon nitride ceramicsTape cast Si3N4 ceramic substrates were supplied by the Netherlands Energy Research foundationECN (Petten, The Netherlands). After sintering, the tape cast samples featured a thickness of only240 µm. Compared to the preparation of Si3N4 by hot pressing, the tape casting method represents anindustrially relevant technique for the manufacturing of large-area ceramic sheets at low cost.


Figure 7.12 shows an optical microscope image of a sample cross section after silicon seeding layerdeposition. The substrate surface is comparatively rough, but barrier layer and silicon film follow thegiven surface topology. The ONO intermediate layer is damaged, with the gaps being filled up withsilicon, indicating that they probably developed during the heating up phase of the silicon depositionprocess. Chemical reactions or mechanical stress between substrate and intermediate layer might havecaused this damage.

After seeding layer deposition the samples were slightly bowed. This bending deteriorated with everyadditional high-temperature step during the entire process sequence. A difference in TEC betweenceramic substrate and silicon layer is assumed to result in a tensile stress in the silicon layer whichsubsequently causes the thin sample to bend.

10 µm

Crack

p+-Si

Tape cast Si3N4 ceramic

ONO

Figure 7.12: Cross section of tape cast Si3N4 ceramic substrate with ONO barrier and silicon seedinglayer (Nomarski microscope image).


An inhomogeneous width of the molten zone dominated the recrystallization process. In some areasthe molten zone even reached the back of the sample i.e. the whole substrate was molten through. Dueto the resulting low temperature gradient, the crystal structure of the recrystallized silicon film wascharacterized by small grains in these regions. A facetted growth front was observed on part of thesamples, indicating oriented crystal growth. In this case, large grains of several mm in width andseveral cm in length developed.

In general, an inhomogeneous width of the molten zone reflects inhomogeneous thermal properties ofthe substrate, assuming uniform properties of the silicon film and barrier layer. Incomplete mixing ofthe starting powders or non-uniform sintering conditions may cause such inhomogeneities when tapecast Si3N4 is used as substrate material. Because of the severe bending of the samples, the sample backside was only in local contact to the carrier quartz plate during ZMR, thus generating “hot spots”where a melting through was facilitated. To prevent such hot spots a quartz plate with cut-out in thecenter was used such that the samples were only supported at the edges by the quartz plate.

The image in Figure 7.13 (left) shows the cross section of a sample after epitaxial deposition of thebase. On elevated sites of the substrate surface the seeding layer is no longer present and apolycrystalline silicon layer has grown on the exposed barrier layer during epitaxy. The holes in theseeding layer are assumed to develop during ZMR and subsequent etching. During ZMR liquid siliconcan accumulate in the lower seated parts of the substrate surface, thus reducing the film thickness onelevated sites. In the following pre-epitaxial cleaning step a thin layer is removed from the surfaceleading to the formation of holes on these sites. For substrates featuring a very large surface roughnessholes can also form during the recrystallization step already, if the deposited silicon seeding layer isvery thin. As a general rule, the seeding layer thickness should exceed the surface roughness of thesubstrate.

Figure 7.13: Left: Cross section of recrystallized and epitaxied silicon film on tape-cast Si3N4 (Seccoetched, microscope image). Right: Image of a sample surface after epitaxy. The whitecontour marks an area which was molten through during ZMR.

Figure 7.13 (right) shows the surface of a recrystallized and epitaxied silicon film on tape cast Si3N4.The white contour encloses a region, which has been molten through during ZMR. Small grains andlarge defect densities characterize this area, while large grains were obtained for the remaining siliconfilm. In some areas, the epitaxial layer is affected by whisker growth, probably induced by acontaminated surface of the recrystallized layer.


Chemical and electrical analysis

In Figure 7.14 (left) the GDMS impurity profile for a silicon film prepared on tape cast Si3N4 isdepicted. The boron concentration remains on a more or less constant level throughout the entireprofile, which means that either no BSF is present or the sputter depth was too low. The correspondingSRP measurement (Figure 7.14, right) shows, that the back surface field features a doping level of2x1018 cm-3, compared to a carrier density of 8x1016 cm-3 in the base layer. Both regions can be clearlyidentified in the SRP profile, thus verifying that only the epilayer was characterized by the GDMSmeasurement.

With increasing depth the impurity concentration of nitrogen, iron and chromium in the silicon baselayer increases by one to three orders of magnitude. For the transition metals iron and chromiummaximum concentration of 1.4 ppma (6x1016 cm-3) and 0.1 ppma (5x1015 cm-3) were measuredrespectively. These values are in the range of their solubility limit in silicon given in literature22. Thepresence of these impurities in the silicon film can be traced back to the perforation of the ONObarrier layer, which was already observed after seeding layer deposition. During high-temperatureprocesses like epitaxy and especially ZMR fast diffusing elements like iron and chromium can easilyovercome the barrier layer and contaminate the silicon film.

1 2 3 4 5 6 710-3

10-2

10-1

100

101

102

103

104

105 B11 C12 N14 P31 Ti48 V51 Cr52 Mn55 Fe56 Ni58 Cu63

Con

cent

ratio

n [p

pma]

Sputter time [A.U.]5 10 15 20 25 30 35 40

1016

1017

1018

1019

Base BSF

Car

rier D

ensi

ty [c

m-3]

Depth [µm]

Figure 7.14: GDMS (left) and SRP (right) measurement carried out for a silicon film based on tapecast Si3N4 ceramic substrate.

Solar cells on tape cast Si3N4 ceramic substrates

A batch of solar cells containing 15 samples has been prepared on silicon thin-films on tape castsilicon nitride ceramics. The severe bending of the samples made the entire processing and especiallythe photolithographic steps difficult.

The batch turned out to be very inhomogeneous with efficiencies ranging from 3 to 8.1%. Low fillfactors of 36 to 61% and short-circuit current densities of 18.4 to 25.9 mA/cm² determine the solar cellperformance, with the fill factor being mostly the limiting factor. The best solar cell featured anefficiency of 8.1%, with VOC=530 mV, JSC=24.9 mA/cm² and FF=61.2%.

22 CFe(1300°C) = 5x1016 cm-3, CCr(1280°C) = 2.5x1015 cm-3, according to [77].


An analysis of dark I/V-curves showed that the prepared solar cells suffer from low parallel resistance,increased values for I02 and high series resistance, resulting in the observed low fill factors. Fitted I/V-parameters yield values for RP and RS below 1000 Ωcm2 and above 3 Ωcm2 respectively.

Low parallel resistance and high saturation currents are attributed to a minor crystal quality of therecrystallized and epitaxially thickened silicon layers. The large series resistance might be caused byan increased contact resistance as a result of defective photolithography processes associated to thebending of the samples. Apart from that, the low doping density and thickness of the BSF layer mightcause an increase in series resistance.

The graph in Figure 7.15 visualizes the inhomogeneity of the entire batch in terms of solar cellefficiency and demonstrates the effect of hydrogen passivation and double layer antireflection coating.The application of hydrogen passivation resulted in an average increase in efficiency by 5% relative.The samples show a large scatter in their response to the passivation step. Typically the improvementin open-circuit voltage and fill factor by hydrogen passivation increases with decreasing crystal qualityfor silicon films prepared by ZMR [69] i.e. a larger boost in efficiency can be expected for solar cellsbased on low quality films. This characteristic does not apply in this case. The open-circuit voltage ofall solar cells benefits from the passivation step leading to an increase between 9 and 37 mV. Similarlylarger short-circuit currents are measured for most cells after passivation. However, significantimprovements in fill factor are observed only for a few cells. The defective emitter contact grid mightbe the reason for this result.

0123456789

1011121314

FZ-Ref.Solar cells on tape cast Si3N4

Effic

ienc

y [%

]

After ARC After RPHP Before RPHP

Figure 7.15: Impact of hydrogen passivation and antireflection coating on solar cell efficiency.

A gain of 11% relative in short-circuit current density was obtained by the deposition of a double layerantireflection coating. A larger boost in short-circuit current is observed for the FZ-Si reference solarcell because no texturing has been applied in this case.

The internal quantum efficiency was calculated from spectral response and reflection measurementsfor the best solar cell prepared within this batch. The characteristic in Figure 7.16 reveals an effectiveblue response exceeding 90%. The curve features a decrease in IQE at a comparatively lowwavelength of 500-600 nm due to a low minority carrier lifetime in the base. At a wavelength of


1000 nm an enhanced response is obtained as a result from optical confinement introduced by theONO barrier layer.

400 600 800 1000 12000.0

0.2

0.4

0.6

0.8

1.0

IQE

λ [nm]

Figure 7.16: Internal quantum efficiency for silicon thin-film solar cell on tape cast Si3N4 ceramicsubstrate.

In addition, the SR-LBIC technique was applied to create a mapping of effective minority carrierdiffusion lengths, calculated from local short-circuit currents and corresponding reflectivity. In Figure7.17 the mapping and the corresponding histogram are given. A fairly homogeneous distribution inminority carrier diffusion length across the entire cell area is obtained. On the left-hand side of the cella region with increased diffusion length is observed indicating a better crystal quality of thecorresponding grain compared to the remaining area. The histogram shows that only a small fractionof diffusion lengths exceeds the thickness of the base layer. An average value of 11 µm was calculatedfrom the histogram.

0 2 4 6 8 10mm

0

>24

Leff [µm]

0 5 10 15 20 25 30 35 400

2000400060008000

10000120001400016000

average Leff = 11µm

Cou

nts

Leff [µm]

Figure 7.17: Mapping of effective minority carrier diffusion length (left) and correspondinghistogram (right) of the solar cell with best efficiency.

The large concentration of the transition metals chromium and especially iron within the silicon film isassumed to cause a severe reduction in minority carrier diffusion length, thus being the limiting factorfor solar cells with complete and undamaged contact grids.


Summary

The preparation of silicon thin-films on tape cast Si3N4 ceramic substrates was affected by aperforation of the ONO barrier layer after seeding layer deposition, inhomogeneous recrystallizationbehavior and melting through of the samples. The silicon layers were found to be contaminated bymetallic impurities (mainly iron) which diffused from the substrate into the silicon layer during high-temperature processing. A severe bending of the samples was observed, which might be attributed to amismatch in thermal expansion coefficient between substrate and silicon film.

For the first time, silicon thin-film solar cells have been prepared on tape cast Si3N4 ceramicsubstrates. A maximum efficiency of 8.1% was achieved, which represents a remarkable resultconsidering that neither substrate properties nor solar cell processing were optimized. Theoptimization of the tape cast Si3N4 ceramic material in terms of thermal and chemical propertiesrepresents a major challenge for future activities in this area.

7.2.5 Silicon thin-films on SiAlON ceramicsTape cast SiAlON ceramic substrates were provided by the Netherlands Energy Research foundationECN (Petten, The Netherlands). The non conductive sheets were made from commercial Si3N4, AlNand Al2O3 powders. After sintering, open and bulk porosity were determined to values below 1% and10% respectively. The substrate thickness was specified to 460±30 µm and according to suppliersinformation the TEC ranged between 4 to 5x10-6 K-1.

Seeding layer deposition and zone-melting recrystallization

Silicon CVD on ONO encapsulated SiAlON substrates was non-ideal and resulted in inhomogeneoussilicon layer thickness. Severe whisker growth affected the quality of the deposited silicon films. Afterseeding layer deposition the layer system was analyzed by microscopy on cross sections and samplesurfaces. The SEM cross section image in Figure 7.18 reveals a severe damage of the ONO barrierlayer. At intervals of few microns, the intermediate layer is interrupted by cracks.

p+-Si

Crack

SiO2

SiO2

SiNx

SiAlON substrate

Figure 7.18: Cross section image of a silicon seeding layer grown on SiAlON substrate with ONObarrier layer (Secco etched, SEM image).

The development of fissures may be explained by thermal stress which builds up between the substrateand the layer system during the heating or the cooling phase of the silicon deposition process. Second,


some kind of chemical reaction could have take place between the substrate components and theintermediate layer during the CVD process, where the samples are heated to 950°C.

The observed growth of whiskers might be caused by the diffusion of impurities from the substrate tothe sample surface, where they act as nucleation centers for a defective growth mode [157].

The recrystallization process was characterized by an inhomogeneous width of the molten zone,balling up of the liquid silicon, infiltration-like features and in general little oriented crystal growth.The bone-shaped, inhomogeneous width of the molten zone might be caused by inhomogeneousthermal properties across the substrate area. The already damaged barrier layer and the large bulkporosity may in fact lead to an infiltration of the liquid silicon into the substrate material. The siliconseeding layers were only partly recrystallized and in most cases a peeling off of the silicon layeroccurred. In conclusion, the entire layer system proved to be unstable during ZMR.

The removal of the capping layer by hydrofluoric acid activated a chemical reaction between substrateand acid making the samples very brittle. This observation is in correlation with the perforated barrierlayer and the bulk porosity, which enables any fluid to penetrate the substrate material.

Epitaxy of the base layer

Optical microscopy and SEM were applied to analyze the crystallographic properties of the samplesafter epitaxy of the base layer. Figure 7.19 illustrates typical properties of the recrystallized andepitaxially thickened silicon films on SiAlON ceramics.

Cracks were found to penetrate the silicon film down to the barrier layer (Figure 7.19, left). Theperforation of the intermediate layer is also clearly visible. The surfaces of the epitaxial layers weretypically covered with whiskers as the SEM image in Figure 7.19 (right) shows.

p-Si

p+-Si

SiO2

SiAlON substrate

Crack

Figure 7.19: Left: Cross section of recrystallized and epitaxially thickened silicon layer on SiO2

encapsulated SiAlON substrate. A crack penetrates the entire silicon layer system.Right: Surface of the same sample featuring severe whisker growth (SEM images).

The occurrence of cracks in the silicon layer may be attributed to a mismatch in TEC for SiAlONsubstrate and silicon film. The extension of the cracks from base layer to intermediate layer indicatesthat they developed during the cool-down phase of the epitaxy process.


An incomplete surface cleaning or the diffusion of impurities from the bulk to the silicon surfaceduring the heating-up phase of the epitaxy process are possibly responsible for the enhanced growth ofwhiskers. Because of the large density of whiskers the samples on SiAlON ceramic substrates werenot further processed.

7.3 SummaryThe evaluation of different potential low-cost ceramic material for an application as substrates insilicon thin-film solar cells was subject of this chapter. For this purpose, silicon thin-films wereprepared on silicon-infiltrated SiC, hot-pressed Si3N4, tape cast Si3N4 and tape cast SiAlON ceramicsubstrates with dielectric ONO barrier layer. An extensive characterization of sample and solar cellproperties was carried out to allow for an assessment of the suitability of the ceramic materials.

The best result in terms of efficiency was obtained for a crystalline silicon thin-film solar cell on SiSiCceramic substrate. A maximum efficiency of 10.7% was reached, exceeding the best efficiencypublished so far for a similar solar cell structure using SiSiC as substrate material.

A remarkable efficiency of 8.1% was achieved on tape cast Si3N4 ceramic substrates. These are thevery first solar cells prepared on this type of material and further improvement can be expected ifsubstrate material properties and solar cell process are optimized.

Silicon-film and solar cell preparation on hot-pressed Si3N4 and tape cast SiAlON ceramic substrateswere not successful. Thermal and chemical properties of these substrates hindered an effective samplepreparation making them unsuitable as potential substrate for silicon thin-film solar cells.

The matching of thermal, chemical and mechanical properties of the substrate material with theremaining layer system was found to be crucial for a success of the presented solar cell concept. All ofthe investigated combinations of ceramic substrate and dielectric intermediate layer were affected bymore or less harmful interactions between different components of the layer stack during sampleprocessing. Nonetheless, the results obtained for SiSiC and tape cast Si3N4 ceramics show, that thesematerials have the potential for a successful application as substrates for thin-film solar cells, if theirmaterial properties can be further tailored to the requirements imposed by sample and solar cellpreparation.

Solar cell processing of silicon thin-films on insulating substrates is a very complex issue because ofthe necessity for a one-side contacting scheme. Recent publications show [147] that the realization of asolar cell process on insulating substrates using industrial relevant technologies is a great challengewhich is still to be solved.

145

8 Summary

The aim of this work was to push the concept of crystalline silicon thin-film solar cells closer towardslarge-scale production. Two major aspects were considered: fast silicon deposition and preparation ofepitaxial thin-film solar cells by industrial-type technologies.

Research activities in the field of silicon thin-film solar cells are motivated by the demand for lowercost per Wp and reduced silicon consumption. A discussion of existing silicon thin-film solar cellapproaches showed that most low-temperature routes suffer from low efficiencies or degradation.Considering the transfer techniques, the questions of wafer recycling, layer detachment and high-throughput silicon deposition are not yet solved. Within the high-temperature route, silicon thin-filmsolar cells on low-cost silicon substrates or foreign substrates are promising concepts to achieveefficiencies similar to conventional bulk solar cells but at lower cost and reduced silicon usage. Acrucial issue for the success of this approach is the availability of high throughput silicon depositionreactors.

In the past, a large variety of silicon deposition techniques has been developed according to the needimposed by microelectronic industry. Low-temperature deposition techniques suffer from lowdeposition rates at high technological effort while high-temperature CVD at atmospheric pressure is asuitable tool for the growth of high-quality layers at high rates. APCVD reactors used inmicroelectronic production are optimized to yield high-quality layers, irrespective of throughput andtherefore the design of new deposition systems is inevitable. The RTCVD100 reactor, developed andbuilt at Fraunhofer ISE, is based on a reactor and deposition concept which is expected to meet therequirements on high throughput and layer quality. Characteristic features of the RTCVD100 are theusage of trichlorosilane as silicon precursor gas, the optical heating system and the wafer setup whichallows for a large chemical yield. While the RTCVD100 is a laboratory type reactor, an up-scaledversion (RTCVD160) with larger wafer size capacity and improved process flexibility has recentlybeen set up at Fraunhofer ISE. Finally, a continuous CVD (ConCVD) was presented, which is adeposition system on the cusp of industrial scale production. Within this work the reactor concept wasevaluated using the RTCVD100 reactor.

A thorough characterization and optimization of epilayers and seeding layers grown on foreignsubstrates in the RTCVD100 was one major issue within this work. Suitable characterization toolswere defined and silicon layer properties were analyzed with respect to thickness and dopinghomogeneity, carrier concentration, impurity concentration, electrical and crystallographic quality.With increasing wafer size and throughput, new large-area characterization tools especially for anevaluation of thickness and doping distribution are necessary. Automatic surface profiling and highspeed, large-area sheet resistance mapping were tested and to the author’s opinion both techniqueshave the potential for a successful application in large-area silicon film characterization.

For silicon deposition, the design of the gas inlet was found to substantially effect the gas flowbehavior in the deposition chamber and consequently the deposition rate and thickness uniformity. Theimplementation of gas diffusers or more generally a gas inlet which enables an efficient distribution ofthe incoming gas across the entire deposition cross section is essential for the growth of homogeneous

8 Summary146

films. This requirement becomes even more stringent for the up-scaled RTCVD160 reactor. Withinthis work, the gas distribution and thickness homogeneity could be improved by the application of anozzle. Further improvement is expected, if more sophisticated injection systems like showerheads ormasks are used. Two optimized epitaxy processes and one seeding layer deposition process werefinally defined which served as a base for the following investigations. The deposited layers were ofhigh purity, with thickness and doping homogeneity and minority carrier lifetime sufficient for anapplication in thin-film solar cells. For the RTCVD160 a standard seeding layer deposition process hassimilarly been set up. Future work in this area will concentrate on the development of depositionprocesses for the RTCVD160 and especially for the continuous CVD system.

During epilayer analysis, Spreading Resistance Profiling has proved to be a powerful tool for themeasurement of carrier density profiles. Based on this characterization method, carrier concentrationsand profiles were characterized for epilayers grown under different deposition conditions. The analysisby SRP allowed an insight on the mechanisms of boron incorporation and the impact of the gas systemon doping profiles. A change of the gas system was proposed to prevent the observed unwanted effectsof delayed diborane injection and large dead capacities on doping density profiles. The carrierconcentration was found to depend only on the initial diborane concentration in the gas phase. Inliterature, a dependence on growth rate and diborane concentration is widely reported. The differentdeposition conditions used in the RTCVD100 compared to commercial APCVD reactors is assumed tobe responsible for this deviation. For a deeper understanding of the doping incorporation processadditional experiments are desirable. The same holds for the observed boron diffusion from a diboranecontaining gas phase, an effect which is only little discussed in literature.

The epitaxial silicon thin-film solar cell represents an attractive thin-film concept because it can inprinciple be processed by common industrial solar cell technologies. An extensive investigation wascarried out with respect to an application of industrial relevant solar cell processing techniques toepitaxial thin-film solar cells. For this aim, epilayers were grown on different electrically inactivesilicon substrates and thin-film solar cells were prepared by cleanroom and screen printing techniques.The effects of emitter formation by POCl3 and in-line diffusion, and the impact of contact formationby evaporation and screen printing with and without firing through silicon nitride were investigatedand compared. It was demonstrated that epitaxial thin-film solar cells can equally well be processed byeither technology irrespective of substrate material, making a direct introduction of epitaxial waferequivalents into standard industrial production lines possible. Using screen printing techniques,efficiencies of up to 12.2% and 11.7% were obtained for epitaxial thin-film solar cells on Cz-Si andmc-Si substrates respectively. For the first time single-crystal reclaimed wafers have been used assubstrate material. The best solar cell reached an efficiency of 11.5% using screen printing techniques.It was demonstrated, that a doubling of the growth rate from 5 to 10 µm/min results only in minorefficiency losses and for high throughput production the fast growth mode represents an interestingoption. The implementation of surface texture was found to be indispensable for epitaxial thin-filmsolar cells to increase photocurrent and efficiency. The development of efficient light trappingschemes, implementation of adequate bulk and surface passivation schemes and the evaluation ofother potential low-cost silicon substrate materials (e.g. metallurgical grade silicon substrates) areamongst the most important issues to be solved in the future.

The second solar cell structure under investigation followed the concept of silicon thin-films onforeign insulating substrates. Four high-temperature ceramics were tested as substrate material: hot-pressed silicon nitride and silicon infiltrated silicon carbide (“ideal” substrates) and tape cast silicon

8 Summary 147

nitride and SiAlON (“realistic” substrates). Solar cells were prepared according to the followingsequence: deposition of diffusion barrier layer, silicon seeding layer deposition, zone-meltingrecrystallization, epitaxy of the base and solar cell processing with one-side contact scheme. Duringprocessing the ONO barrier layer got more or less damaged for all sample types, with the tape castsubstrates being affected the most. The perforated intermediate layer allowed for a diffusion ofmetallic impurities from the substrates into the silicon film i.e. the silicon base layers were allcontaminated by harmful impurities, thereby reducing minority carrier lifetime. Silicon film and solarcell preparation were not successful for hot-pressed silicon nitride and SiAlON ceramics due to amismatch in thermal and chemical properties. Efficiencies of up to 8.1% were achieved for first thin-film solar cells on tape cast silicon nitride ceramics. This is a remarkable result, considering that theceramic material properties were not optimized for this application. Using SiSiC ceramic substrates,an efficiency of 10.7% has been reached, exceeding the best efficiency published so far for a similarsolar cell structure based on SiSiC substrate.

At present the concept of silicon thin-film solar cells on insulating substrates suffers from the lack ofsuitable substrate/barrier layer systems. Moreover, the necessity for a one-side contact schemerepresents a great challenge to industrial solar cell processing technologies. A challenge, which is stillto be solved. A solution to the latter aspect is given by the use of electrically conductivesubstrate/barrier layer systems. These thin-film structures could be processed by conventionaltechniques. At Fraunhofer ISE, current research activities in this area focus on the development anduse of conductive silicon carbide intermediate layers.


Deutsche Zusammenfassung

Die vorliegende Arbeit beschäftigt sich mit dem Ansatz der kristallinen Silizium-Dünnschichtsolarzelle. Dieses Konzept ermöglicht eine wesentliche Einsparung an Silizium-Materialund trägt damit zur Reduktion der Modulkosten und zur Vermeidung oder Verzögerung einesdrohenden Silizium-Engpasses in der PV-Industrie bei. Das Solarzellenkonzept basiert auf derVerwendung dünner Siliziumschichten, die auf ein geeignetes kostengünstiges Trägersubstratabgeschieden werden. Gegenüber herkömmlichen Wafer-Solarzellen ist die aktive Siliziumschichttypischerweise auf etwa 1/10 reduziert. Gleichzeitig kann der teure Sägeschritt, der zur Herstellungder Silizium-Wafer notwendig ist und bei dem etwa die Hälfte des Ausgangsmaterials durchSägeverschnitt verloren geht, umgangen werden und damit weiteres Material und Kosten gespartwerden.

Traditionell werden die Konzepte für die Herstellung von kristallinen Silizium-Dünnschichtsolarzellenin Hochtemperatur- und Niedertemperatur-Ansätze unterschieden, abhängig von derMaximaltemperatur, die für das Substrat noch tolerierbar ist. Die verschiedenen Ansätze zurRealisierung dieser Solarzellenstrukturen werden in der vorliegenden Arbeit vorgestellt undverglichen. Am Fraunhofer ISE wird an verschiedenen Hochtemperatur-Ansätze geforscht, da dieseKonzepte eine Anwendung schneller Silizium-Abscheidetechniken bei hohen Temperaturenermöglichen. Weiterhin können auf Fremdsubstrate abgeschiedene feinkristalline Siliziumschichtendurch einen Kristallisationsprozess über die flüssige Phase in Schichten mit großkörnigerKristallstruktur überführt werden. Die elektrische Qualität der Schichten wird dadurch verbessert undhöhere Wirkungsgrade können erreicht werden. Im wesentlichen werden zwei Konzepte verfolgt:epitaktische Dünnschichtsolarzellen auf kostengünstigen Silizium-Substraten undDünnschichtsolarzellen auf Fremdsubstraten. Ein Erfolg dieser Konzepte hinsichtlich industriellerFertigung ist unter anderem abhängig von der Entwicklung geeigneter Silizium-Abscheideanlagen mithohem Durchsatz.

Im Rahmen dieser Arbeit wurden zwei Schwerpunkte behandelt: die Weiterentwicklung vonHochleistungs-Silizium-Abscheidereaktoren und die Prozessierung epitaktischer SiliziumDünnschichtsolarzellen mit industriell relevanten Fertigungstechnologien.

Zunächst werden gängige Methoden zur Abscheidung von Silizium beschrieben und diskutiert. DieAbscheidung aus der Gasphase unter Atmosphärendruck (APCVD23) ist für schnelle Abscheidungenbei hohen Temperaturen bestens geeignet. Konventionelle APCVD Abscheidereaktoren, wie sie in derMikroelektronik zur Herstellung elektronischer Bauteile verwendet werden, arbeiten in der Regel imBatch-Betrieb bei hohen Gasflüssen, relativ geringen Wachstumsraten, hohem Gasverbrauch unddamit hohen Kosten. Siliziumschichten mit exzellenter Schicht- und Dotierungshomogenität und vonsehr guter Kristallqualität werden damit hergestellt. Für eine Anwendung in der Photovoltaik sind dieAnforderungen an die Schichteigenschaften weniger strikt, dafür ist hoher Durchsatz undkosteneffektiver Betrieb der Anlage umso wichtiger. Am Fraunhofer ISE wird verstärkt an der 23 APCVD: Atmospheric Pressure Chemical Vapor Deposition.

Deutsche Zusammenfassung150

Entwicklung von geeigneten APCVD-Reaktoren gearbeitet. Die erste Anlage, die in diesemZusammenhang vor etwa 8 Jahren entwickelt wurde ist die RTCVD10024, die in dieser Arbeitgewissermaßen als Zugpferd verwendet wurde. Die Anlage arbeitet unter Atmosphärendruck und istmit einem optischen Heizsystem ausgestattet. Die Abscheidung erfolgt aus der Gasphase, wobeiTrichlorsilan und Wasserstoff als Prozessgase und Diboran zur Abscheidung Bor-dotierter Schichteneingesetzt werden. Ein weiteres charakteristisches Element ist der Substrathalter, auf den die Probenzur Beschichtung aufgelegt werden: zwei horizontale parallele Wafer-Reihen bilden zusammen mitdem Quarzträger ein abgeschlossenes Volumen. Durch eine Öffnung in der Frontplatte des Trägerswird das Prozessgas eingeführt und gleichermaßen durch eine Öffnung in der Endplatte wiederabgeführt. Das Prozessgas kommt somit nur mit den Waferflächen und mit den Bestandteilen desQuarzträgers in Berührung. Parasitäre Abscheidungen auf dem umgebenden Reaktor-Quarzrohrwerden damit vermieden und die chemische Effizienz der Abscheidung verbessert. Die RTCVD100 isteine Laboranlage, an der das Reaktorkonzept erprobt wurde. Das Nachfolgemodell RTCVD160basiert auf den gleichen Prinzipien wie die RTCVD100, erlaubt aber die Bearbeitung größerer Probenund entsprechend höherem Durchsatz. Die kontinuierliche Silizium CVD-Anlage, die am FraunhoferISE innerhalb eines Forschungsprojektes entwickelt und dort Ende 2002 aufgebaut worden ist, stellteinen weiteren wichtigen Schritt in Richtung industrieller Fertigung dar. Alle drei Anlagen werdenbeschrieben, wobei der Schwerpunkt auf eine Ausführung der technischen Details der RTCVD100gelegt wurde.

Die Charakterisierung und Optimierung von Silizium-Abscheideprozessen für die RTCVD100 istwesentlicher Bestandteil dieser Arbeit. Geeignete Charakterisierungsmethoden wurden evaluiert undepitaktische Siliziumschichten wurden hinsichtlich Schicht- und Dotierungshomogenität, elektrischer,kristallographischer und chemischer Eigenschaften analysiert. Verfahren zur Charakterisierung vonSiliziumschichten auf großen Flächen wurden vorgeschlagen und getestet. Zwei Epitaxie-Prozesse undein Prozess zur Abscheidung von Siliziumschichten auf Fremdsubstraten wurden optimiert undstandardisiert. Die abgeschiedenen Schichten waren in all ihren Eigenschaften gut geeignet für eineAnwendung in Dünnschichtsolarzellen. Das erfolgversprechende Prinzip der RTCVD100 konntedamit bestätigt werden. Zukünftige Arbeiten in diesem Bereich werden sich auf die Optimierung vonCVD-Prozessen in der RTCVD160 und vor allem in der Durchlaufanlage konzentrieren.

Weiterer Punkt dieser Arbeit ist eine detaillierte Analyse von Dotierprofilen in Siliziumschichten, dieunter verschiedenen Prozessbedingungen hergestellt worden waren. Die Mechanismen des Einbausvon Bor in die wachsende Siliziumschicht während der Epitaxie und die Diffusion von Bor aus derGasphase wurde studiert. Unter anderem wurden dabei wichtige Einblicke in die Zusammenhängezwischen Gassystem und Dotierprofil gewonnen. Basierend auf diesen Untersuchungen wird eineModifikation des vorhandenen Gassystems vorgeschlagen.

Epitaktische Silizium-Dünnschichtsolarzellen können auf direktem Wege in bereits bestehendenFertigungslinien verarbeitet werden. Zusammen mit dem Kostensparpotenzial des Ansatzes ist diesesZellkonzept besonders attraktiv. Die Anwendung industrienaher Solarzellentechnologien aufepitaktisches Material wird in dieser Arbeit intensiv diskutiert. Zu diesem Zweck wurden in derRTCVD100 dünne (ca. 20-30 µm) Siliziumschichten auf elektrisch inaktive Silizium-Substrateabgeschieden. Die Einflüsse von Emitterbildung durch POCl3 und Durchlaufdiffusion, und von

24 RTCVD: Rapid Thermal CVD (schnelle thermische Abscheidung aus der Gasphase).


Kontaktbildung durch Aufdampfen und Siebdruck mit und ohne Feuern durch Siliziumnitrid wurdenseparat verglichen und beurteilt. Im Zuge dessen konnte gezeigt werden, dass sich epitaktische Zellensowohl mit Reinraum- als auch mit Siebdruck-Prozessen gleich gut prozessieren lassen. UnterVerwendung von Siebdrucktechniken wurden Wirkungsgrade von 12.2% und 11.7% auf inaktiven Cz-Si und mc-Si Substraten erreicht. Zum erstenmal wurden einkristalline Reclaim-Wafer alsSubstratmaterial verwendet. Bei diesem Material handelt es sich um wiederverwertete Wafer aus derMikroelektronik, bei denen alle Bauelemente entfernt wurden. Wirkungsgrade bis zu 11.5% konntenhiermit erzielt werden (Siebdrucktechnik). Weiterhin konnte gezeigt werden, dass eine Erhöhung derAbscheiderate von 5 auf 10 µm/min nur einen geringen Verlust der Solarzelleneffizienz nach sichzieht und damit für eine industrielle Fertigung interessant wird. Die Entwicklung von Strukturen füreine effiziente Lichteinkopplung, effektive Passivierungstechniken von Oberflächen und Bulk und dieUntersuchung weiterer potenzieller kostengünstiger Silizium-Materialien wie z.B. Substrate ausmetallurgischem Silizium, stellen zukünftige Forschungsschwerpunkte auf dem Gebiet derepitaktischen Dünnschichtsolarzelle dar.

In einem letzten Arbeitspunkt wurden kristalline Dünnschichtsolarzellen auf isolierendenFremdsubstraten hergestellt. Dazu wurden vier Keramiken als Substrat-Material verwendet: heißgepresstes Siliziumnitrid und Silizium-infiltriertes Siliziumcarbid mit polierten Oberflächen („ideale“Materialien), und foliengezogenes Siliziumnitrid sowie foliengezogenes SiAlON („realistische“kostengünstige Materialien). Die Solarzellen wurden nach folgendem Prozess hergestellt:Abscheidung einer Barriereschicht, Abscheidung einer hochdotierten Siliziumschicht, Rekristallisationder Siliziumschicht durch Zonenschmelzen, Epitaxie der aktiven Basis und Solarzellenprozessierungmit einseitiger Kontaktierung. Die Barriereschichten wurden bei allen Schichtsystemen durch dieProzessierung teilweise beschädigt. Heiß gepresste Siliziumnitrid und foliengezogene SiAlONSubstrate erwiesen sich aufgrund ihrer thermischen, mechanischen und chemischen Eigenschaften alsungeeignet für eine Anwendung als Substrat. Erste Dünnschichtsolarzellen auf foliengezogenenSiliziumnitrid Substraten erreichten Wirkungsgrade bis zu 8.1%. Weitere Steigerungen sind zuerwarten, wenn das Substrat auf die Anforderungen optimiert wird. Die beste Solarzelle aufSiliziumcarbid Substrat zeigte einen Wirkungsgrad von 10.7%, der sogar den bisher veröffentlichtenhöchsten Wirkungsgrad auf diesem Substrat um 1.4% absolut übersteigt.

Die Entwicklung geeigneter Substrat/Barriereschicht-Kombinationen und die Einseitenkontaktierungauf Ebene der industriellen Fertigung stellen zwei herausragende Herausforderungen an das Konzeptder kristallinen Dünnschichtsolarzelle auf isolierenden Fremdsubstraten dar. Letzteres Problem kanndurch die Entwicklung elektrisch leitfähiger Substrat/Zwischenschicht-Systeme umgangen werden,wodurch eine konventionelle Prozessierung ermöglicht würde. Am Fraunhofer ISE wird daher derzeitverstärkt an der Entwicklung leitfähiger Siliziumcarbidschichten gearbeitet.

Appendix A Abbreviations 153

Appendix A Abbreviations

APCVD Atmospheric Pressure Chemical Vapor Deposition

ARC Antireflection Coating

BBC Buried Base Contacts

BSF Back Surface Field

CMOS Complementary Metal-Oxide Semiconductor

CVD Chemical Vapor Deposition

Cz-Si Czochralski silicon

DLARC Double Layer Antireflection Coating

EBIC Electron Beam Induced Current

EFG Edge-defined Film-fed Growth

EQE External Quantum Efficiency

FF Fill Factor

FTIR Fourier Transform Infrared Reflectrometry

FZ-Si Float-Zone silicon

GDMS Glow-Discharge Mass Spectrometry

HWCVD Hot-Wire Chemical Vapor Deposition

IAD Ion-Assisted Deposition

IQE Internal Quantum Efficiency

LPCVD Low-Pressure Chemical Vapor Deposition

LPE Liquid-Phase Epitaxy

MBE Molecular Beam Epitaxy

MG Metallurgical-Grade

MOS Metal-Oxide Semiconductor

MOSFET Metal-Oxide Semiconductor Field-Effect Transistor

MW-PCD Microwave Photo-Current-Decay

PECVD Plasma-Enhanced Chemical Vapor Deposition

PSG Phosphorus Silicate Glass

PSI Porous Silicon

PVD Physical Vapor Deposition

RGS Ribbon Growth on Substrate

Appendix A Abbreviations154

RIE Reactive Ion Etching

RPCVD Reduced Pressure Chemical Vapor Deposition

RPHP Remote Plasma Hydrogen Passivation

RTA Rapid Thermal Anneal

RTF Rapid Thermal Firing

RTCVD Rapid Thermal Chemical Vapor Deposition

RTP Rapid Thermal Processing

SEM Secondary Electron Microscopy

SIMOX Separation by Implanted Oxygen

SIMS Secondary Ion Mass Spectroscopy

SOI Silicon On Insulator

SR-LBIC Spectrally Resolved Light Beam Induced Current

SRP Spreading Resistance Profiling

SSP Silicon Sheets from Powder

TCS Trichlorosilane, SiHCl3

TEC Thermal Expansion Coefficient

TFT Thin-Film Transistor

UHV-CVD Ultrahigh-Vacuum Chemical Vapor Deposition

UMG Upgraded Metallurgical Grade

QMS Quasi-Monocrystalline Silicon

VHF-PECVD Very High Frequency Plasma-Enhanced Chemical Vapor Deposition

VLSI Very-Large-Scale Integration

ZMR Zone-Melting Recrystallization


Appendix B Solar cell fundamentals

Solar cell devices incorporate a large area pn junction in a semiconductor with emitter and base beingcontacted by metal electrodes. Incident photons, when absorbed in the semiconductor, can generateelectron hole pairs (photoeffect). Provided a sufficient lifetime, the generated minority carriers candiffuse to the pn-junction, where charge separation occurs by the incorporated electric field. Thecarriers are subsequently collected by the contacts, leading to a current flow in an external circuit.

Treating the solar cell as an ideal infinite diode, its current-voltage characteristics can be described bythe ideal diode model:

PCkTqV IeIVI −−= )1()( /

0 (B.1)

where I0, q, V, k, T and IPC denote the saturation current of emitter and base, elementary charge,voltage, Boltzmann’s constant, device temperature and generated photocurrent. The thermalphotovoltage is given by VT=kT/q. From eqn. (B.1) the short-circuit current density ISC and open-circuit voltage VOC can be deduced:

)1/ln(, 0 +=−= IIVVII PCTOCPCSC(B.2)

The maximum output power of the cell depends on open-circuit voltage, short-circuit current and fillfactor (FF):

FFIVIVP SCOCmppmpp ==max(B.3)

Where Vmpp and Impp denote the voltage and current at the maximum power point. The fill factor FFdenotes the ratio of maximum output power to the product of VOC and ISC. The efficiency of a solar cellis given by the ratio of maximum output power to the solar radiation power provided by the incidentsunlight.

Eqn. (B.2) shows that low saturation currents are needed for large open-circuit voltages andsubsequently large output power. The saturation current density of the base is given by

FnA

nib G

LNDqn

VI2

0 )( = (B.4)

where ni, Dn, NA, Ln, and GF are intrinsic carrier concentration, minority carrier (electrons for a p-typebase) diffusion constant, acceptor density, minority carrier diffusion length and the so-called geometryfactor. The latter depends on the recombination velocity at the surfaces S, base thickness W and“recombination velocity” in the crystal S∞=Dn/Ln:

)/sinh()/cosh()/()/sinh()/()/cosh(

nn

nnF LWLWSS

LWSSLWG

++

=∞

∞ (B.5)

For a reduction of the saturation current, large diffusion lengths, large acceptor concentrations and lowgeometry factors are beneficial. The increase in acceptor concentration is limited by the associated

Appendix B Solar cell fundamentals156

increase in Auger recombination and enhanced band gap narrowing. Figure B.1 illustrates thedependence of the geometry factor on the ratio of W/Ln for different values of S/S∞.

For base thickness larger than the minority carrier diffusion length (W≥3Ln) the geometry factor isequal to one, independent on surface and volume recombination velocity. If the surface recombinationvelocity exceeds the recombination velocity in the volume (S/S∞>1) the geometry factor is larger thanone and increases with rising ratio of S/S∞. A reduction in open-circuit voltage is the consequence. Theopposite effect results, if the surface recombination velocity is reduced such that S/S∞<1. To achievehigh open-circuit voltages, minority carrier diffusion lengths exceeding the base thickness and wellpassivated surfaces are necessary.

In the limit of W<<Ln and S=0 (ideal passivation) eqn. (B.4) can be approximated by

n

nn

nA

ib D

Lwith

NWqn

VI2

0 )( == ττ

(B.6)

where τn denotes the minority carrier lifetime in the base. This relation demonstrates that a reductionof base thickness W lowers the saturation current, if the minority carrier lifetime is held constant.

0.1 1 1010-2

10-1

100

101

102

S/S∞

∞

1/2

1/20

= 0

1/5

21

5

20

Geo

met

ry fa

ctor

W/Ln

Figure B.1: Geometry factor as a function of W/Ln for different ratios of S/S∞.

In a real solar cell device, recombination losses have to be accounted for, leading to the two-diodemodel:

PCP

SVnIRsVVnIRsV IR

IRVeIeIVI TT −

−+−+−= −− )1()1()( 21 /)(

02/)(

01 (B.7)

I01 is the saturation current of emitter and base and corresponds to I0 in eqn. (B.1). I02 denotes thesaturation current of the space charge region and is induced by the presence of trap levels. In bothcases, an increase in saturation current results in a decrease of open-circuit voltage.

The series resistance RS combines the resistance of the semiconductor material, emitter and base metalcontacts and the contact resistance between metal electrode and semiconductor. The shunt resistance


RP is caused by leakage currents. Both parasitic resistances reduce the fill factor and large seriesresistances can also lower the short-circuit current of the device.

n1 and n2 are ideality factors which are equal to 1 and 2 respectively for ideal cell behavior but maydiffer from their theoretical values for real solar cells.

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Publications 171

Publications

S. Bau, T. Kieliba, D. Oßwald, A. Hurrle, Chemical Vapour Deposition of Silicon on CeramicSubstrates for Crystalline Silicon Thin-Film Solar Cells, 17th European Photovoltaic Solar EnergyConference (2001) 1575-1577.

S. Reber, J. Dicker, D.M. Huljić, S. Bau, Epitaxy of Emitters for Crystalline Silicon Solar Cells, 17th


S. Bau, D.M. Huljić, J. Isenberg, J. Rentsch, Shunt-Analysis of Epitaxial Silicon Thin-Film Solar Cellsby Lock-In Thermography, 29th IEEE Photovoltaic Specialists Conference (2002) 1335-1338.

T. Kieliba, S. Bau, R. Schober, D. Oßwald, S. Reber, A. Eyer, G. Willeke, Crystalline silicon thin-filmsolar cells on ZrSiO4 ceramic substrates, Solar Energy Materials & Solar Cells 74 (2002) 261-266.

S. Bau, J. Rentsch, D.M. Huljić, S. Reber, A. Hurrle, G. Willeke, Application of Screen PrintingProcesses for Epitaxial Silicon Thin-Film Solar Cells, 3rd World Conference on Photovoltaic EnergyConversion (2003).

S. Bau, S. Janz, T. Kieliba, S. Reber, C. Schetter, F. Lutz, Application of PECVD-SiC as IntermediateLayer in Crystalline Silicon Thin-Film Solar Cells, 3rd World Conference on Photovoltaic EnergyConversion (2003).

S. Reber, C. Haase, N. Schillinger, S. Bau, A. Hurrle, The RTCVD160 – A new lab-type silicon CVDprocessor for silicon deposition on large area substrates, 3rd World Conference on PhotovoltaicEnergy Conversion (2003).

A. Slaoui, A. Focsa, S. Bau, S. Reber, T. Kieliba, A. Gutjahr, R. Bilyalov, J. Poortmans, Silicon Filmson Ceramic Substrates (SOCS): Growth and Solar Cells, 3rd World Conference on PhotovoltaicEnergy Conversion (2003).

J. Rentsch, S. Bau, D.M. Huljić, Screen printed epitaxial thin-film solar cells with 13.1% efficiency,Progress in Photovoltaics, to be published.

Acknowledgements 173

Acknowledgements

At the end of this work, I would like to express my gratitude to all the people who supported me in mystudies during the past four years. My colleges, friends and family encouraged this work in manifoldways and contributed to its success. I thank you all.

_________________________________________

Mein Dank gilt zuallererst Herrn PD. Dr. Willeke für die Vergabe dieser spannenden Arbeit.

Stefan Reber möchte ich ganz besonders danken für seine unermüdliche Unterstützung während derletzten Jahre, sein Vertrauen in diese Arbeit, sein Engagement und seine mitreißende Begeisterungnicht nur für die kristalline Silizium-Dünnschichtsolarzelle. Sein oft ungetrübter Enthusiasmus undEinsatz bleibt der Dünnschicht-Gruppe hoffentlich noch lange erhalten.

Dank auch an Albert Hurrle für etliche Erklärungen zum Thema Gasphasen-Abscheidung. SeinVersuch, alles möglichst objektiv zu sehen und zu beurteilen und seine wunderbar logischeHerangehensweise an Probleme – egal ob physikalischer, technischer oder politischer Art – waren mirimmer ein Vorbild.

Norbert Schillinger möchte ich danken für die Einweisung in das Innenleben unserer schnellen CVD-Anlagen und für unzählige Reparatur-, Flaschenwechsel- und Quarzarbeiten. Die gemeinsame Arbeithat mir großen Spaß gemacht und hat mich gelehrt, auch scheinbar Selbstverständliches zuhinterfragen und Vor- und Nachteile aller Dinge ganz genau abzuwägen.

Für die vielen Arbeiten im Chemielabor sei Frau Mira Kwiatkowska gedankt. Ihre Bereitschaft,besonders dringende Dinge auch sofort zu erledigen, haben die weitere Bearbeitung vieler Proben oftwesentlich vorangetrieben.

Meinem Promotions-Kollegen Thomas Kieliba verdanke ich viele gute Stunden gemeinsamerDiskussion zum Thema Dünnschicht, viele wertvolle Tipps bei diversen EDV-Problemen, überausangenehme Kaffee- und Schoko-Pausen und eine tolle Büro-Zeit. Über unsere ausgeglichene,zuverlässige und gut funktionierende Zusammenarbeit habe ich mich sehr gefreut. Auch den KollegenJochen Rentsch, Dominik Huljić, Jörg Isenberg und Stefan Janz sei für ihre Unterstützung undZusammenarbeit im Dünnschichtbereich gedankt.

Dem Einsatz des gesamten Tech-II Teams habe ich es zu verdanken, dass viele meiner Dünnschicht-Solarzellen den Weg ans Licht gefunden haben. Dieser Dank gilt allen voran Harald Lautenschlagerund Christian Schetter für ihre Mühen bei der Solarzellenprozessierung und diversen Spezial-Anfertigungen.

Die prompten Erledigungen sämtlicher Hell-/Dunkel-, SR- und SR-LBIC-Messungen, vor allem inden letzten Monaten, haben mir in meiner Arbeit sehr geholfen. Hierfür und für ihre vielen anderenHilfen möchte ich mich bei Elisabeth Schäffer sehr herzlich bedanken. Die sonnige Atmosphäre imMesslabor war mir oft ein Grund, dort zu einer kleinen Pause vorbei zu schauen.

Acknowledgements174

Für wegweisende und konstruktive Diskussionen zur Theorie und Analyse der Dünnschichtzelle dankeich Stefan Glunz und Wilhelm Warta.

Vielen Dank auch an Daniel Spinner für seine überaus unkomplizierte, schnelle und zuverlässige Hilfebei kleinen und großen Soft- und Hardware-Problemen.

Jörn Denter gebührt ein herzliches Dankeschön für die tolle Zusammenarbeit im CVD-Labor und dieunvergessenen Reisen und Unternehmungen mit Meier-Tours.

Meiner Lebenspartnerin Anna danke ich für all die kleinen und großen Aufregungen, die unserenAlltag ausmachen, für ihre Offenheit, gemeinsam Neues auszuprobieren und für ihre unendlich großeGeduld und Unterstützung nicht nur während der letzten Monate.

Schließlich möchte ich meinen Eltern danken, die mich in all meinen Entscheidungen undLebensweisen stets unterstützt haben und mir die Freiheit gaben, meine eigenen Wege zu suchen undzu gehen.

Documents

High-temperature CVD silicon films for crystalline silicon