High Speed Digital Systems LabHigh Speed Digital Systems LabSpring/Winter 2010Spring/Winter 2010

Project definitionProject definition

Instructor: Instructor: Rolf HilgendorfRolf HilgendorfStudents: Students: Elad Mor, Ilya ZavolskyElad Mor, Ilya Zavolsky

Integration of an A/D Integration of an A/D Converter Converter

Into The Sub-Nyquist Xampling Into The Sub-Nyquist Xampling SystemSystem

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TopicsTopics Sub-Nyquist Xampling system OverviewSub-Nyquist Xampling system Overview The main goalThe main goal Review of the Texas Instruments ADS6423 Review of the Texas Instruments ADS6423 LVDS BackgroundLVDS Background I/O schemeI/O scheme A/D chip diagram and output interfaceA/D chip diagram and output interface FPGA receiver block diagramFPGA receiver block diagram A/D control interfaceA/D control interface Time table of semester ATime table of semester A

Integration of an A/D into Xampling System

Sub-Nyquist Xampling system Sub-Nyquist Xampling system OverviewOverview

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System

Our goal is to integrate a sub-system that would Our goal is to integrate a sub-system that would convert the incoming analog samples to digital convert the incoming analog samples to digital signals. Then they will be processed and signals. Then they will be processed and reconstructed in the sub-Nyquist Sampling reconstructed in the sub-Nyquist Sampling system.system.

For this purpose we shall use the TI ADS6423 For this purpose we shall use the TI ADS6423 Evaluation module. Evaluation module.

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The main goalThe main goal To configure and integrate the ADS6423 A/D card to To configure and integrate the ADS6423 A/D card to

the sub-Nyquist experimental Xampling system .the sub-Nyquist experimental Xampling system . The A/D converter will receive wide spectrum signal The A/D converter will receive wide spectrum signal

by four channels and will transmit serial high speed by four channels and will transmit serial high speed digital outputs (LVDS).digital outputs (LVDS).

To design and implement an I/O adapter card which To design and implement an I/O adapter card which will assign the correct pins between the A/D and the will assign the correct pins between the A/D and the Gidel cardGidel card

To create a control environment to set-up and To create a control environment to set-up and monitor the A/D which will be integrated onto an monitor the A/D which will be integrated onto an ALTERA FPGA and monitored from a PC.ALTERA FPGA and monitored from a PC.

To create an initial and a permanent testing To create an initial and a permanent testing environment for the module. environment for the module.

Integration of an A/D into Xampling System

Review of Texas Instruments Review of Texas Instruments ADS6423 EVMADS6423 EVM

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The ADS6423 is a The ADS6423 is a high performance high performance 12 bit, 105/80 MSPS 12 bit, 105/80 MSPS , quad channel A-D , quad channel A-D converter.converter.

It is configured to It is configured to accept 4 single accept 4 single ended input sources ended input sources (Through COAX (Through COAX cables).cables).

The ADC outputs The ADC outputs are serialized data, are serialized data, a bit clock and a a bit clock and a frame clock which frame clock which are brought to a are brought to a high density high density connector. connector.

LVDS BackgroundLVDS Background LVDS – Low Voltage Differential Signaling, is a signaling LVDS – Low Voltage Differential Signaling, is a signaling

method which uses a pair of inductors to transmit two method which uses a pair of inductors to transmit two different voltages that are compared at the receiver. different voltages that are compared at the receiver.

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A typical LVDS driver – receiver pair is shown above; nominal 3.5 mA current A typical LVDS driver – receiver pair is shown above; nominal 3.5 mA current source is located in the driver. Since the input impedance of the receiver is high, source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a the entire current effectively flows through the 100Ω termination resulting in a 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V. mode from 0V to 2.4V.

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The 350 mV typical signal swing of LVDS The 350 mV typical signal swing of LVDS consumes only a small amount of power and consumes only a small amount of power and therefore LVDS is a very efficient technology, therefore LVDS is a very efficient technology, delivering performance at data rates up to delivering performance at data rates up to 3.125 Gbps.3.125 Gbps.

The simple termination, low power, and low The simple termination, low power, and low noise generation generally make LVDS the noise generation generally make LVDS the technology of choice for data rates from tens of technology of choice for data rates from tens of Mbps up to 3 Gbps and beyondMbps up to 3 Gbps and beyond..

I/O schemeI/O scheme

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a)a) 4 incoming channels of analog input signal, 60 MHz each, 1 4 incoming channels of analog input signal, 60 MHz each, 1 Volt peak-to-peak.Volt peak-to-peak.

b)b) 8 LVDS Pairs that enters the Gidel Card after being assigned 8 LVDS Pairs that enters the Gidel Card after being assigned inside the pin adapter (390 Mbit/sec). We also transmit a inside the pin adapter (390 Mbit/sec). We also transmit a Frame clock out of the A/D device.Frame clock out of the A/D device.

c)c) Clock and control signals that are generated on the Gidel Clock and control signals that are generated on the Gidel ProcStarIII.ProcStarIII.

d)d) 4 channels x12 bit of de-serialized output which will be sent to 4 channels x12 bit of de-serialized output which will be sent to the expand sequence module.the expand sequence module.

e)e) Pin Adapter card which we are going to design and Pin Adapter card which we are going to design and implement. It’s purpose is to connect the correct pins on the implement. It’s purpose is to connect the correct pins on the PSDB connection on the Gidel card onto the ADS6423. (Meet PSDB connection on the Gidel card onto the ADS6423. (Meet Gidel Personnel to inquire about this solution and determine if Gidel Personnel to inquire about this solution and determine if LVDS+Non LVDS combination is possible on same PSDB slot.) LVDS+Non LVDS combination is possible on same PSDB slot.)

A/D chip block diagramA/D chip block diagram

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FPGA receiver block diagramFPGA receiver block diagram

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The Altera Stratix III Differential The Altera Stratix III Differential signals Receiversignals Receiver

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The Stratix III device has dedicated The Stratix III device has dedicated circuitry to receive high-speed differential circuitry to receive high-speed differential signals. signals.

The receiver has a differential buffer, PLL, The receiver has a differential buffer, PLL, DPA block, synchronization FIFO buffer, DPA block, synchronization FIFO buffer, data realignment block, and a data realignment block, and a deserializer.deserializer.

A/D Card and ALTERA LVDS A/D Card and ALTERA LVDS common-modecommon-mode

Since the ALTERA Differential Voltage receiver Since the ALTERA Differential Voltage receiver top speed is 500 Mbit/sec, the A/D most top speed is 500 Mbit/sec, the A/D most appropriate interface option is the 2-wire, SDR appropriate interface option is the 2-wire, SDR bit clock, 12x serialization. This option will bit clock, 12x serialization. This option will produce an output serial data rate of 390 produce an output serial data rate of 390 Mbit/sec. Mbit/sec.

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A/D digital ouput InterfaceA/D digital ouput Interface

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The Most suitable option is 2-Wire, 1 × The Most suitable option is 2-Wire, 1 × frame clock, 12 × serialization, with SDR frame clock, 12 × serialization, with SDR bit clock, byte wise/bit wise/word wise.bit clock, byte wise/bit wise/word wise.

A/D control interfaceA/D control interface

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ADS6423 offers flexibility with several programmable ADS6423 offers flexibility with several programmable features.features.

At first, we intend to use both the serial interface and At first, we intend to use both the serial interface and parallel controls (combination of jumpers and serial parallel controls (combination of jumpers and serial interface), due to its simplicity.interface), due to its simplicity.

As the project evolves, we will upgrade to serial As the project evolves, we will upgrade to serial interface programming only.interface programming only.

Serial interface programming mode are used to Serial interface programming mode are used to access the internal registers of ADC.access the internal registers of ADC.

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Time table (Semester A)Time table (Semester A)Task \ WeekTask \ Week 11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414

Exploring the problem Exploring the problem 8/3                          

Definition presentation Definition presentation         22/4                

Explore Altera LVDS Explore Altera LVDS receiverreceiver                            

Acquire tool knowledge*Acquire tool knowledge*                            

Define A/D configurationDefine A/D configuration                            

Midterm presentationMidterm presentation                          

Define an initial test env.                            

Design an adapter card                            

Design of the A/D Controller                            

Design of LVDS Receiver logic                          

Integration of the system                            

Form a debug strategy                            

                         30-01

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Questions / AnswersQuestions / Answers

Thank you!Thank you!

Integration of an A/D into Xampling System

(Task List(Task List forfor Semester Semester B)B)

Forming a debug strategyForming a debug strategy To Define and Implement a To Define and Implement a

permanent test environment.permanent test environment. To Build a PC control interface using To Build a PC control interface using

PROC-wizard.PROC-wizard. To create a configuration and To create a configuration and

operation protocol for the sub-operation protocol for the sub-Nyquist sampling system user.Nyquist sampling system user.

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